1 /*arch/powerpc/platforms/8xx/mpc885ads_setup.c
3 * Platform setup for the Freescale mpc885ads board
5 * Vitaly Bordug <vbordug@ru.mvista.com>
7 * Copyright 2005 MontaVista Software Inc.
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/param.h>
17 #include <linux/string.h>
18 #include <linux/ioport.h>
19 #include <linux/device.h>
20 #include <linux/delay.h>
21 #include <linux/root_dev.h>
23 #include <linux/fs_enet_pd.h>
24 #include <linux/fs_uart_pd.h>
25 #include <linux/fsl_devices.h>
26 #include <linux/mii.h>
28 #include <asm/delay.h>
30 #include <asm/machdep.h>
32 #include <asm/processor.h>
33 #include <asm/system.h>
35 #include <asm/mpc8xx.h>
36 #include <asm/8xx_immap.h>
37 #include <asm/commproc.h>
38 #include <asm/fs_pd.h>
41 #include <sysdev/commproc.h>
43 static void init_smc1_uart_ioports(struct fs_uart_platform_info *fpi);
44 static void init_smc2_uart_ioports(struct fs_uart_platform_info *fpi);
45 static void init_scc3_ioports(struct fs_platform_info *ptr);
47 #ifdef CONFIG_PCMCIA_M8XX
48 static void pcmcia_hw_setup(int slot, int enable)
52 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
54 clrbits32(bcsr_io, BCSR1_PCCEN);
56 setbits32(bcsr_io, BCSR1_PCCEN);
61 static int pcmcia_set_voltage(int slot, int vcc, int vpp)
66 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
92 if ((vcc == 33) || (vcc == 50))
100 /* first, turn off all power */
101 clrbits32(bcsr_io, 0x00610000);
103 /* enable new powersettings */
104 setbits32(bcsr_io, reg);
111 void __init mpc885ads_board_setup(void)
114 unsigned int *bcsr_io;
117 #ifdef CONFIG_FS_ENET
121 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
122 cp = (cpm8xx_t *) immr_map(im_cpm);
124 if (bcsr_io == NULL) {
125 printk(KERN_CRIT "Could not remap BCSR\n");
128 #ifdef CONFIG_SERIAL_CPM_SMC1
129 clrbits32(bcsr_io, BCSR1_RS232EN_1);
130 clrbits32(&cp->cp_simode, 0xe0000000 >> 17); /* brg1 */
131 tmpval8 = in_8(&(cp->cp_smc[0].smc_smcm)) | (SMCM_RX | SMCM_TX);
132 out_8(&(cp->cp_smc[0].smc_smcm), tmpval8);
133 clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN); /* brg1 */
135 setbits32(bcsr_io, BCSR1_RS232EN_1);
136 out_be16(&cp->cp_smc[0].smc_smcmr, 0);
137 out_8(&cp->cp_smc[0].smc_smce, 0);
140 #ifdef CONFIG_SERIAL_CPM_SMC2
141 clrbits32(bcsr_io, BCSR1_RS232EN_2);
142 clrbits32(&cp->cp_simode, 0xe0000000 >> 1);
143 setbits32(&cp->cp_simode, 0x20000000 >> 1); /* brg2 */
144 tmpval8 = in_8(&(cp->cp_smc[1].smc_smcm)) | (SMCM_RX | SMCM_TX);
145 out_8(&(cp->cp_smc[1].smc_smcm), tmpval8);
146 clrbits16(&cp->cp_smc[1].smc_smcmr, SMCMR_REN | SMCMR_TEN);
148 init_smc2_uart_ioports(0);
150 setbits32(bcsr_io, BCSR1_RS232EN_2);
151 out_be16(&cp->cp_smc[1].smc_smcmr, 0);
152 out_8(&cp->cp_smc[1].smc_smce, 0);
157 #ifdef CONFIG_FS_ENET
158 /* use MDC for MII (common) */
159 io_port = (iop8xx_t *) immr_map(im_ioport);
160 setbits16(&io_port->iop_pdpar, 0x0080);
161 clrbits16(&io_port->iop_pddir, 0x0080);
163 bcsr_io = ioremap(BCSR5, sizeof(unsigned long));
164 clrbits32(bcsr_io, BCSR5_MII1_EN);
165 clrbits32(bcsr_io, BCSR5_MII1_RST);
166 #ifndef CONFIG_FC_ENET_HAS_SCC
167 clrbits32(bcsr_io, BCSR5_MII2_EN);
168 clrbits32(bcsr_io, BCSR5_MII2_RST);
176 #ifdef CONFIG_PCMCIA_M8XX
177 /*Set up board specific hook-ups */
178 m8xx_pcmcia_ops.hw_ctrl = pcmcia_hw_setup;
179 m8xx_pcmcia_ops.voltage_set = pcmcia_set_voltage;
183 static void init_fec1_ioports(struct fs_platform_info *ptr)
185 cpm8xx_t *cp = (cpm8xx_t *) immr_map(im_cpm);
186 iop8xx_t *io_port = (iop8xx_t *) immr_map(im_ioport);
188 /* configure FEC1 pins */
189 setbits16(&io_port->iop_papar, 0xf830);
190 setbits16(&io_port->iop_padir, 0x0830);
191 clrbits16(&io_port->iop_padir, 0xf000);
193 setbits32(&cp->cp_pbpar, 0x00001001);
194 clrbits32(&cp->cp_pbdir, 0x00001001);
196 setbits16(&io_port->iop_pcpar, 0x000c);
197 clrbits16(&io_port->iop_pcdir, 0x000c);
199 setbits32(&cp->cp_pepar, 0x00000003);
200 setbits32(&cp->cp_pedir, 0x00000003);
201 clrbits32(&cp->cp_peso, 0x00000003);
202 clrbits32(&cp->cp_cptr, 0x00000100);
208 static void init_fec2_ioports(struct fs_platform_info *ptr)
210 cpm8xx_t *cp = (cpm8xx_t *) immr_map(im_cpm);
211 iop8xx_t *io_port = (iop8xx_t *) immr_map(im_ioport);
213 /* configure FEC2 pins */
214 setbits32(&cp->cp_pepar, 0x0003fffc);
215 setbits32(&cp->cp_pedir, 0x0003fffc);
216 clrbits32(&cp->cp_peso, 0x000087fc);
217 setbits32(&cp->cp_peso, 0x00037800);
218 clrbits32(&cp->cp_cptr, 0x00000080);
224 void init_fec_ioports(struct fs_platform_info *fpi)
226 int fec_no = fs_get_fec_index(fpi->fs_no);
230 init_fec1_ioports(fpi);
233 init_fec2_ioports(fpi);
236 printk(KERN_ERR "init_fec_ioports: invalid FEC number\n");
241 static void init_scc3_ioports(struct fs_platform_info *fpi)
247 bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE);
248 io_port = (iop8xx_t *) immr_map(im_ioport);
249 cp = (cpm8xx_t *) immr_map(im_cpm);
251 if (bcsr_io == NULL) {
252 printk(KERN_CRIT "Could not remap BCSR\n");
258 clrbits32(bcsr_io + 4, BCSR4_ETH10_RST);
260 setbits32(bcsr_io + 4, BCSR4_ETH10_RST);
261 /* Configure port A pins for Txd and Rxd.
263 setbits16(&io_port->iop_papar, PA_ENET_RXD | PA_ENET_TXD);
264 clrbits16(&io_port->iop_padir, PA_ENET_RXD | PA_ENET_TXD);
266 /* Configure port C pins to enable CLSN and RENA.
268 clrbits16(&io_port->iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
269 clrbits16(&io_port->iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
270 setbits16(&io_port->iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
272 /* Configure port E for TCLK and RCLK.
274 setbits32(&cp->cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK);
275 clrbits32(&cp->cp_pepar, PE_ENET_TENA);
276 clrbits32(&cp->cp_pedir, PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA);
277 clrbits32(&cp->cp_peso, PE_ENET_TCLK | PE_ENET_RCLK);
278 setbits32(&cp->cp_peso, PE_ENET_TENA);
280 /* Configure Serial Interface clock routing.
281 * First, clear all SCC bits to zero, then set the ones we want.
283 clrbits32(&cp->cp_sicr, SICR_ENET_MASK);
284 setbits32(&cp->cp_sicr, SICR_ENET_CLKRT);
286 /* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used.
288 clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN);
289 /* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode
290 * by H/W setting after reset. SCC ethernet controller support only half duplex.
291 * This discrepancy of modes causes a lot of carrier lost errors.
294 /* In the original SCC enet driver the following code is placed at
295 the end of the initialization */
296 setbits32(&cp->cp_pepar, PE_ENET_TENA);
297 clrbits32(&cp->cp_pedir, PE_ENET_TENA);
298 setbits32(&cp->cp_peso, PE_ENET_TENA);
300 setbits32(bcsr_io + 4, BCSR1_ETHEN);
306 void init_scc_ioports(struct fs_platform_info *fpi)
308 int scc_no = fs_get_scc_index(fpi->fs_no);
312 init_scc3_ioports(fpi);
315 printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
320 static void init_smc1_uart_ioports(struct fs_uart_platform_info *ptr)
325 cp = (cpm8xx_t *) immr_map(im_cpm);
326 setbits32(&cp->cp_pepar, 0x000000c0);
327 clrbits32(&cp->cp_pedir, 0x000000c0);
328 clrbits32(&cp->cp_peso, 0x00000040);
329 setbits32(&cp->cp_peso, 0x00000080);
332 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
334 if (bcsr_io == NULL) {
335 printk(KERN_CRIT "Could not remap BCSR1\n");
338 clrbits32(bcsr_io, BCSR1_RS232EN_1);
342 static void init_smc2_uart_ioports(struct fs_uart_platform_info *fpi)
347 cp = (cpm8xx_t *) immr_map(im_cpm);
348 setbits32(&cp->cp_pepar, 0x00000c00);
349 clrbits32(&cp->cp_pedir, 0x00000c00);
350 clrbits32(&cp->cp_peso, 0x00000400);
351 setbits32(&cp->cp_peso, 0x00000800);
354 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
356 if (bcsr_io == NULL) {
357 printk(KERN_CRIT "Could not remap BCSR1\n");
360 clrbits32(bcsr_io, BCSR1_RS232EN_2);
364 void init_smc_ioports(struct fs_uart_platform_info *data)
366 int smc_no = fs_uart_id_fsid2smc(data->fs_no);
370 init_smc1_uart_ioports(data);
371 data->brg = data->clk_rx;
374 init_smc2_uart_ioports(data);
375 data->brg = data->clk_rx;
378 printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
383 int platform_device_skip(const char *model, int id)
385 #ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
386 const char *dev = "FEC";
389 const char *dev = "SCC";
393 if (!strcmp(model, dev) && n == id)
399 static void __init mpc885ads_setup_arch(void)
403 mpc885ads_board_setup();
408 static int __init mpc885ads_probe(void)
410 char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
414 if (strcmp(model, "MPC885ADS"))
420 define_machine(mpc885_ads)
422 .name = "MPC885 ADS",
423 .probe = mpc885ads_probe,
424 .setup_arch = mpc885ads_setup_arch,
425 .init_IRQ = m8xx_pic_init,
426 .get_irq = mpc8xx_get_irq,
427 .restart = mpc8xx_restart,
428 .calibrate_decr = mpc8xx_calibrate_decr,
429 .set_rtc_time = mpc8xx_set_rtc_time,
430 .get_rtc_time = mpc8xx_get_rtc_time,