2 * MPC86xx HPCN board specific routines
4 * Recode: ZHANG WEI <wei.zhang@freescale.com>
5 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
7 * Copyright 2006 Freescale Semiconductor Inc.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
15 #include <linux/stddef.h>
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/kdev_t.h>
19 #include <linux/delay.h>
20 #include <linux/seq_file.h>
21 #include <linux/root_dev.h>
23 #include <asm/system.h>
25 #include <asm/machdep.h>
26 #include <asm/pci-bridge.h>
27 #include <asm/mpc86xx.h>
29 #include <mm/mmu_decl.h>
31 #include <asm/i8259.h>
35 #include <sysdev/fsl_soc.h>
38 #include "mpc8641_hpcn.h"
43 #define DBG(fmt...) do { printk(KERN_ERR fmt); } while(0)
45 #define DBG(fmt...) do { } while(0)
49 unsigned long isa_io_base = 0;
50 unsigned long isa_mem_base = 0;
51 unsigned long pci_dram_offset = 0;
56 static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc,
59 unsigned int cascade_irq = i8259_irq(regs);
60 if (cascade_irq != NO_IRQ)
61 generic_handle_irq(cascade_irq, regs);
64 #endif /* CONFIG_PCI */
67 mpc86xx_hpcn_init_irq(void)
70 struct device_node *np;
71 phys_addr_t openpic_paddr;
73 struct device_node *cascade_node = NULL;
77 np = of_find_node_by_type(NULL, "open-pic");
81 /* Determine the Physical Address of the OpenPIC regs */
82 openpic_paddr = get_immrbase() + MPC86xx_OPENPIC_OFFSET;
84 /* Alloc mpic structure and per isu has 16 INT entries. */
85 mpic1 = mpic_alloc(np, openpic_paddr,
86 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
89 BUG_ON(mpic1 == NULL);
91 mpic_assign_isu(mpic1, 0, openpic_paddr + 0x10000);
93 /* 48 Internal Interrupts */
94 mpic_assign_isu(mpic1, 1, openpic_paddr + 0x10200);
95 mpic_assign_isu(mpic1, 2, openpic_paddr + 0x10400);
96 mpic_assign_isu(mpic1, 3, openpic_paddr + 0x10600);
98 /* 16 External interrupts
99 * Moving them from [0 - 15] to [64 - 79]
101 mpic_assign_isu(mpic1, 4, openpic_paddr + 0x10000);
106 /* Initialize i8259 controller */
107 for_each_node_by_type(np, "interrupt-controller")
108 if (device_is_compatible(np, "chrp,iic")) {
112 if (cascade_node == NULL) {
113 printk(KERN_DEBUG "mpc86xxhpcn: no ISA interrupt controller\n");
117 cascade_irq = irq_of_parse_and_map(cascade_node, 0);
118 if (cascade_irq == NO_IRQ) {
119 printk(KERN_ERR "mpc86xxhpcn: failed to map cascade interrupt");
122 DBG("mpc86xxhpcn: cascade mapped to irq %d\n", cascade_irq);
124 i8259_init(cascade_node, 0);
125 set_irq_chained_handler(cascade_irq, mpc86xx_8259_cascade);
131 enum pirq{PIRQA = 8, PIRQB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, PIRQH};
132 const unsigned char uli1575_irq_route_table[16] = {
143 0x3, /* 10: 0b0011 */
144 0x9, /* 11: 0b1001 */
145 0xb, /* 12: 0b1011 */
146 0, /* 13: Reserved */
147 0xd, /* 14, 0b1101 */
148 0xf, /* 15, 0b1111 */
152 get_pci_irq_from_of(struct pci_controller *hose, int slot, int pin)
156 struct device_node *hosenode = hose ? hose->arch_data : NULL;
158 if (!hosenode) return -EINVAL;
160 laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(slot, 0) << 8);
161 laddr[1] = laddr[2] = 0;
162 of_irq_map_raw(hosenode, &pin, laddr, &oirq);
163 DBG("mpc86xx_hpcn: pci irq addr %x, slot %d, pin %d, irq %d\n",
164 laddr[0], slot, pin, oirq.specifier[0]);
165 return oirq.specifier[0];
168 static void __devinit quirk_uli1575(struct pci_dev *dev)
171 struct pci_controller *hose = pci_bus_to_host(dev->bus);
172 unsigned char irq2pin[16];
173 unsigned long pirq_map_word = 0;
178 * ULI1575 interrupts route setup
180 memset(irq2pin, 0, 16); /* Initialize default value 0 */
183 * PIRQA -> PIRQD mapping read from OF-tree
185 * interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD
186 * PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA
188 for (i = 0; i < 4; i++){
189 irq = get_pci_irq_from_of(hose, 17, i + 1);
190 if (irq > 0 && irq < 16)
191 irq2pin[irq] = PIRQA + i;
193 printk(KERN_WARNING "ULI1575 device"
194 "(slot %d, pin %d) irq %d is invalid.\n",
199 * PIRQE -> PIRQF mapping set manually
207 for (i = 0; i < 4; i++) irq2pin[i + 9] = PIRQE + i;
209 /* Set IRQ-PIRQ Mapping to ULI1575 */
210 for (i = 0; i < 16; i++)
212 pirq_map_word |= (uli1575_irq_route_table[i] & 0xf)
213 << ((irq2pin[i] - PIRQA) * 4);
215 /* ULI1575 IRQ mapping conf register default value is 0xb9317542 */
216 DBG("Setup ULI1575 IRQ mapping configuration register value = 0x%x\n",
218 pci_write_config_dword(dev, 0x48, pirq_map_word);
220 #define ULI1575_SET_DEV_IRQ(slot, pin, reg) \
223 irq = get_pci_irq_from_of(hose, slot, pin); \
224 if (irq > 0 && irq < 16) \
225 pci_write_config_byte(dev, reg, irq2pin[irq]); \
227 printk(KERN_WARNING "ULI1575 device" \
228 "(slot %d, pin %d) irq %d is invalid.\n", \
232 /* USB 1.1 OHCI controller 1, slot 28, pin 1 */
233 ULI1575_SET_DEV_IRQ(28, 1, 0x86);
235 /* USB 1.1 OHCI controller 2, slot 28, pin 2 */
236 ULI1575_SET_DEV_IRQ(28, 2, 0x87);
238 /* USB 1.1 OHCI controller 3, slot 28, pin 3 */
239 ULI1575_SET_DEV_IRQ(28, 3, 0x88);
241 /* USB 2.0 controller, slot 28, pin 4 */
242 irq = get_pci_irq_from_of(hose, 28, 4);
243 if (irq >= 0 && irq <=15)
244 pci_write_config_dword(dev, 0x74, uli1575_irq_route_table[irq]);
246 /* Audio controller, slot 29, pin 1 */
247 ULI1575_SET_DEV_IRQ(29, 1, 0x8a);
249 /* Modem controller, slot 29, pin 2 */
250 ULI1575_SET_DEV_IRQ(29, 2, 0x8b);
252 /* HD audio controller, slot 29, pin 3 */
253 ULI1575_SET_DEV_IRQ(29, 3, 0x8c);
255 /* SMB interrupt: slot 30, pin 1 */
256 ULI1575_SET_DEV_IRQ(30, 1, 0x8e);
258 /* PMU ACPI SCI interrupt: slot 30, pin 2 */
259 ULI1575_SET_DEV_IRQ(30, 2, 0x8f);
261 /* Serial ATA interrupt: slot 31, pin 1 */
262 ULI1575_SET_DEV_IRQ(31, 1, 0x8d);
264 /* Primary PATA IDE IRQ: 14
265 * Secondary PATA IDE IRQ: 15
267 pci_write_config_byte(dev, 0x44, 0x30 | uli1575_irq_route_table[14]);
268 pci_write_config_byte(dev, 0x75, uli1575_irq_route_table[15]);
270 /* Set IRQ14 and IRQ15 to legacy IRQs */
271 pci_read_config_word(dev, 0x46, &temp);
273 pci_write_config_word(dev, 0x46, temp);
275 /* Set i8259 interrupt trigger
291 #undef ULI1575_SET_DEV_IRQ
294 static void __devinit quirk_uli5288(struct pci_dev *dev)
298 pci_read_config_byte(dev,0x83,&c);
300 pci_write_config_byte(dev, 0x83, c);
302 pci_write_config_byte(dev, 0x09, 0x01);
303 pci_write_config_byte(dev, 0x0a, 0x06);
305 pci_read_config_byte(dev,0x83,&c);
307 pci_write_config_byte(dev, 0x83, c);
309 pci_read_config_byte(dev,0x84,&c);
311 pci_write_config_byte(dev, 0x84, c);
314 static void __devinit quirk_uli5229(struct pci_dev *dev)
317 pci_write_config_word(dev, 0x04, 0x0405);
318 pci_read_config_word(dev, 0x4a, &temp);
320 pci_write_config_word(dev, 0x4a, temp);
323 static void __devinit early_uli5249(struct pci_dev *dev)
326 pci_write_config_word(dev, 0x04, 0x0007);
327 pci_read_config_byte(dev, 0x7c, &temp);
328 pci_write_config_byte(dev, 0x7c, 0x80);
329 pci_write_config_byte(dev, 0x09, 0x01);
330 pci_write_config_byte(dev, 0x7c, temp);
334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
337 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
338 #endif /* CONFIG_PCI */
342 mpc86xx_hpcn_setup_arch(void)
344 struct device_node *np;
347 ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0);
349 np = of_find_node_by_type(NULL, "cpu");
353 fp = (int *)get_property(np, "clock-frequency", NULL);
355 loops_per_jiffy = *fp / HZ;
357 loops_per_jiffy = 50000000 / HZ;
362 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
365 ppc_md.pci_exclude_device = mpc86xx_exclude_device;
368 printk("MPC86xx HPCN board from Freescale Semiconductor\n");
370 #ifdef CONFIG_ROOT_NFS
373 ROOT_DEV = Root_HDA1;
383 mpc86xx_hpcn_show_cpuinfo(struct seq_file *m)
385 struct device_node *root;
386 uint memsize = total_memory;
387 const char *model = "";
388 uint svid = mfspr(SPRN_SVR);
390 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
392 root = of_find_node_by_path("/");
394 model = get_property(root, "model", NULL);
395 seq_printf(m, "Machine\t\t: %s\n", model);
398 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
399 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
403 void __init mpc86xx_hpcn_pcibios_fixup(void)
405 struct pci_dev *dev = NULL;
407 for_each_pci_dev(dev)
408 pci_read_irq_line(dev);
413 * Called very early, device-tree isn't unflattened
415 static int __init mpc86xx_hpcn_probe(void)
417 unsigned long root = of_get_flat_dt_root();
419 if (of_flat_dt_is_compatible(root, "mpc86xx"))
420 return 1; /* Looks good */
427 mpc86xx_restart(char *cmd)
431 rstcr = ioremap(get_immrbase() + MPC86XX_RSTCR_OFFSET, 0x100);
435 /* Assert reset request to Reset Control Register */
436 out_be32(rstcr, 0x2);
443 mpc86xx_time_init(void)
447 /* Set the time base to zero */
451 temp = mfspr(SPRN_HID0);
453 mtspr(SPRN_HID0, temp);
454 asm volatile("isync");
460 define_machine(mpc86xx_hpcn) {
461 .name = "MPC86xx HPCN",
462 .probe = mpc86xx_hpcn_probe,
463 .setup_arch = mpc86xx_hpcn_setup_arch,
464 .init_IRQ = mpc86xx_hpcn_init_irq,
465 .show_cpuinfo = mpc86xx_hpcn_show_cpuinfo,
466 .pcibios_fixup = mpc86xx_hpcn_pcibios_fixup,
467 .get_irq = mpic_get_irq,
468 .restart = mpc86xx_restart,
469 .time_init = mpc86xx_time_init,
470 .calibrate_decr = generic_calibrate_decr,
471 .progress = udbg_progress,