2 * P1022DS board specific routines
4 * Authors: Travis Wheatley <travis.wheatley@freescale.com>
5 * Dave Liu <daveliu@freescale.com>
6 * Timur Tabi <timur@freescale.com>
8 * Copyright 2010 Freescale Semiconductor, Inc.
10 * This file is taken from the Freescale P1022DS BSP, with modifications:
12 * 3) No PCI endpoint support
14 * This file is licensed under the terms of the GNU General Public License
15 * version 2. This program is licensed "as is" without any warranty of any
16 * kind, whether express or implied.
19 #include <linux/pci.h>
20 #include <linux/of_platform.h>
21 #include <linux/lmb.h>
22 #include <linux/memblock.h>
23 #include <asm/div64.h>
25 #include <asm/swiotlb.h>
27 #include <sysdev/fsl_soc.h>
28 #include <sysdev/fsl_pci.h>
29 #include <asm/fsl_guts.h>
31 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
34 * Board-specific initialization of the DIU. This code should probably be
35 * executed when the DIU is opened, rather than in arch code, but the DIU
36 * driver does not have a mechanism for this (yet).
38 * This is especially problematic on the P1022DS because the local bus (eLBC)
39 * and the DIU video signals share the same pins, which means that enabling the
40 * DIU will disable access to NOR flash.
43 /* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
44 #define CLKDVDR_PXCKEN 0x80000000
45 #define CLKDVDR_PXCKINV 0x10000000
46 #define CLKDVDR_PXCKDLY 0x06000000
47 #define CLKDVDR_PXCLK_MASK 0x00FF0000
49 /* Some ngPIXIS register definitions */
50 #define PX_BRDCFG1_DVIEN 0x80
51 #define PX_BRDCFG1_DFPEN 0x40
52 #define PX_BRDCFG1_BACKLIGHT 0x20
53 #define PX_BRDCFG1_DDCEN 0x10
58 * Note that we need to byte-swap the value before it's written to the AD
59 * register. So even though the registers don't look like they're in the same
60 * bit positions as they are on the MPC8610, the same value is written to the
61 * AD register on the MPC8610 and on the P1022.
63 #define AD_BYTE_F 0x10000000
64 #define AD_ALPHA_C_MASK 0x0E000000
65 #define AD_ALPHA_C_SHIFT 25
66 #define AD_BLUE_C_MASK 0x01800000
67 #define AD_BLUE_C_SHIFT 23
68 #define AD_GREEN_C_MASK 0x00600000
69 #define AD_GREEN_C_SHIFT 21
70 #define AD_RED_C_MASK 0x00180000
71 #define AD_RED_C_SHIFT 19
72 #define AD_PALETTE 0x00040000
73 #define AD_PIXEL_S_MASK 0x00030000
74 #define AD_PIXEL_S_SHIFT 16
75 #define AD_COMP_3_MASK 0x0000F000
76 #define AD_COMP_3_SHIFT 12
77 #define AD_COMP_2_MASK 0x00000F00
78 #define AD_COMP_2_SHIFT 8
79 #define AD_COMP_1_MASK 0x000000F0
80 #define AD_COMP_1_SHIFT 4
81 #define AD_COMP_0_MASK 0x0000000F
82 #define AD_COMP_0_SHIFT 0
84 #define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
85 cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
86 (blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
87 (red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
88 (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
89 (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
92 * p1022ds_get_pixel_format: return the Area Descriptor for a given pixel depth
94 * The Area Descriptor is a 32-bit value that determine which bits in each
95 * pixel are to be used for each color.
97 static unsigned int p1022ds_get_pixel_format(unsigned int bits_per_pixel,
100 switch (bits_per_pixel) {
103 return MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8);
106 return MAKE_AD(4, 0, 1, 2, 2, 0, 8, 8, 8);
109 return MAKE_AD(4, 2, 1, 0, 1, 5, 6, 5, 0);
111 pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
117 * p1022ds_set_gamma_table: update the gamma table, if necessary
119 * On some boards, the gamma table for some ports may need to be modified.
120 * This is not the case on the P1022DS, so we do nothing.
122 static void p1022ds_set_gamma_table(int monitor_port, char *gamma_table_base)
127 * p1022ds_set_monitor_port: switch the output to a different monitor port
130 static void p1022ds_set_monitor_port(int monitor_port)
132 struct device_node *pixis_node;
135 pixis_node = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-pixis");
137 pr_err("p1022ds: missing ngPIXIS node\n");
141 brdcfg1 = of_iomap(pixis_node, 0);
143 pr_err("p1022ds: could not map ngPIXIS registers\n");
146 brdcfg1 += 9; /* BRDCFG1 is at offset 9 in the ngPIXIS */
148 switch (monitor_port) {
150 /* Enable the DVI port, disable the DFP and the backlight */
151 clrsetbits_8(brdcfg1, PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT,
154 case 1: /* Single link LVDS */
155 /* Enable the DFP port, disable the DVI and the backlight */
156 clrsetbits_8(brdcfg1, PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT,
160 pr_err("p1022ds: unsupported monitor port %i\n", monitor_port);
165 * p1022ds_set_pixel_clock: program the DIU's clock
167 * @pixclock: the wavelength, in picoseconds, of the clock
169 void p1022ds_set_pixel_clock(unsigned int pixclock)
171 struct device_node *guts_np = NULL;
172 struct ccsr_guts_85xx __iomem *guts;
177 /* Map the global utilities registers. */
178 guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
180 pr_err("p1022ds: missing global utilties device node\n");
184 guts = of_iomap(guts_np, 0);
185 of_node_put(guts_np);
187 pr_err("p1022ds: could not map global utilties device\n");
191 /* Convert pixclock from a wavelength to a frequency */
192 temp = 1000000000000ULL;
193 do_div(temp, pixclock);
196 /* pixclk is the ratio of the platform clock to the pixel clock */
197 pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
199 /* Disable the pixel clock, and set it to non-inverted and no delay */
200 clrbits32(&guts->clkdvdr,
201 CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
203 /* Enable the clock and set the pxclk */
204 setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
208 * p1022ds_show_monitor_port: show the current monitor
210 * This function returns a string indicating whether the current monitor is
211 * set to DVI or LVDS.
213 ssize_t p1022ds_show_monitor_port(int monitor_port, char *buf)
215 return sprintf(buf, "%c0 - DVI\n%c1 - Single link LVDS\n",
216 monitor_port == 0 ? '*' : ' ', monitor_port == 1 ? '*' : ' ');
220 * p1022ds_set_sysfs_monitor_port: set the monitor port for sysfs
222 int p1022ds_set_sysfs_monitor_port(int val)
224 return val < 2 ? val : 0;
229 void __init p1022_ds_pic_init(void)
233 struct device_node *np;
235 np = of_find_node_by_type(NULL, "open-pic");
237 pr_err("Could not find open-pic node\n");
241 if (of_address_to_resource(np, 0, &r)) {
242 pr_err("Failed to map mpic register space\n");
247 mpic = mpic_alloc(np, r.start,
248 MPIC_PRIMARY | MPIC_WANTS_RESET |
249 MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
250 MPIC_SINGLE_DEST_CPU,
251 0, 256, " OpenPIC ");
253 BUG_ON(mpic == NULL);
260 void __init mpc85xx_smp_init(void);
264 * Setup the architecture
266 static void __init p1022_ds_setup_arch(void)
269 struct device_node *np;
271 dma_addr_t max = 0xffffffff;
274 ppc_md.progress("p1022_ds_setup_arch()", 0);
277 for_each_compatible_node(np, "pci", "fsl,p1022-pcie") {
278 struct resource rsrc;
279 struct pci_controller *hose;
281 of_address_to_resource(np, 0, &rsrc);
283 if ((rsrc.start & 0xfffff) == 0x8000)
284 fsl_add_bridge(np, 1);
286 fsl_add_bridge(np, 0);
288 hose = pci_find_hose_for_OF_device(np);
289 max = min(max, hose->dma_window_base_cur +
290 hose->dma_window_size);
294 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
295 diu_ops.get_pixel_format = p1022ds_get_pixel_format;
296 diu_ops.set_gamma_table = p1022ds_set_gamma_table;
297 diu_ops.set_monitor_port = p1022ds_set_monitor_port;
298 diu_ops.set_pixel_clock = p1022ds_set_pixel_clock;
299 diu_ops.show_monitor_port = p1022ds_show_monitor_port;
300 diu_ops.set_sysfs_monitor_port = p1022ds_set_sysfs_monitor_port;
307 #ifdef CONFIG_SWIOTLB
308 if (lmb_end_of_DRAM() > max) {
309 ppc_swiotlb_enable = 1;
310 set_pci_dma_ops(&swiotlb_dma_ops);
311 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
315 pr_info("Freescale P1022 DS reference board\n");
318 static struct of_device_id __initdata p1022_ds_ids[] = {
320 { .compatible = "soc", },
321 { .compatible = "simple-bus", },
322 { .compatible = "gianfar", },
326 static int __init p1022_ds_publish_devices(void)
328 return of_platform_bus_probe(NULL, p1022_ds_ids, NULL);
330 machine_device_initcall(p1022_ds, p1022_ds_publish_devices);
332 machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
335 * Called very early, device-tree isn't unflattened
337 static int __init p1022_ds_probe(void)
339 unsigned long root = of_get_flat_dt_root();
341 return of_flat_dt_is_compatible(root, "fsl,p1022ds");
344 define_machine(p1022_ds) {
346 .probe = p1022_ds_probe,
347 .setup_arch = p1022_ds_setup_arch,
348 .init_IRQ = p1022_ds_pic_init,
350 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
352 .get_irq = mpic_get_irq,
353 .restart = fsl_rstcr_restart,
354 .calibrate_decr = generic_calibrate_decr,
355 .progress = udbg_progress,