2 * Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved.
4 * Author: Andy Fleming <afleming@freescale.com>
6 * Based on 83xx/mpc8360e_pb.c by:
7 * Li Yang <LeoLi@freescale.com>
8 * Yin Olivia <Hong-hua.Yin@freescale.com>
11 * MPC85xx MDS board specific routines.
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/reboot.h>
24 #include <linux/pci.h>
25 #include <linux/kdev_t.h>
26 #include <linux/major.h>
27 #include <linux/console.h>
28 #include <linux/delay.h>
29 #include <linux/seq_file.h>
30 #include <linux/initrd.h>
31 #include <linux/module.h>
32 #include <linux/fsl_devices.h>
33 #include <linux/of_platform.h>
34 #include <linux/of_device.h>
35 #include <linux/phy.h>
37 #include <asm/system.h>
38 #include <asm/atomic.h>
41 #include <asm/machdep.h>
42 #include <asm/pci-bridge.h>
44 #include <mm/mmu_decl.h>
47 #include <sysdev/fsl_soc.h>
48 #include <sysdev/fsl_pci.h>
50 #include <asm/qe_ic.h>
55 #define DBG(fmt...) udbg_printf(fmt)
60 #define MV88E1111_SCR 0x10
61 #define MV88E1111_SCR_125CLK 0x0010
62 static int mpc8568_fixup_125_clock(struct phy_device *phydev)
67 /* Workaround for the 125 CLK Toggle */
68 scr = phy_read(phydev, MV88E1111_SCR);
73 err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
78 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
83 scr = phy_read(phydev, MV88E1111_SCR);
88 err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);
93 static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
99 err = phy_write(phydev,29, 0x0006);
104 temp = phy_read(phydev, 30);
109 temp = (temp & (~0x8000)) | 0x4000;
110 err = phy_write(phydev,30, temp);
115 err = phy_write(phydev,29, 0x000a);
120 temp = phy_read(phydev, 30);
125 temp = phy_read(phydev, 30);
132 err = phy_write(phydev,30,temp);
137 /* Disable automatic MDI/MDIX selection */
138 temp = phy_read(phydev, 16);
144 err = phy_write(phydev,16,temp);
149 /* ************************************************************************
151 * Setup the architecture
154 static void __init mpc85xx_mds_setup_arch(void)
156 struct device_node *np;
157 static u8 __iomem *bcsr_regs = NULL;
160 ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
163 np = of_find_node_by_name(NULL, "bcsr");
167 of_address_to_resource(np, 0, &res);
168 bcsr_regs = ioremap(res.start, res.end - res.start +1);
173 for_each_node_by_type(np, "pci") {
174 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
175 of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
176 struct resource rsrc;
177 of_address_to_resource(np, 0, &rsrc);
178 if ((rsrc.start & 0xfffff) == 0x8000)
179 fsl_add_bridge(np, 1);
181 fsl_add_bridge(np, 0);
186 #ifdef CONFIG_QUICC_ENGINE
187 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
189 np = of_find_node_by_name(NULL, "qe");
197 np = of_find_node_by_name(NULL, "par_io");
199 struct device_node *ucc;
204 for_each_node_by_name(ucc, "ucc")
205 par_io_of_config(ucc);
209 if (machine_is(mpc8568_mds)) {
210 #define BCSR_UCC1_GETH_EN (0x1 << 7)
211 #define BCSR_UCC2_GETH_EN (0x1 << 7)
212 #define BCSR_UCC1_MODE_MSK (0x3 << 4)
213 #define BCSR_UCC2_MODE_MSK (0x3 << 0)
215 /* Turn off UCC1 & UCC2 */
216 clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
217 clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
219 /* Mode is RGMII, all bits clear */
220 clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
223 /* Turn UCC1 & UCC2 on */
224 setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
225 setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
229 #endif /* CONFIG_QUICC_ENGINE */
233 static int __init board_fixups(void)
236 char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
237 struct device_node *mdio;
241 for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
242 mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);
244 of_address_to_resource(mdio, 0, &res);
245 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
246 (unsigned long long)res.start, 1);
248 phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
249 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
251 /* Register a workaround for errata */
252 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
253 (unsigned long long)res.start, 7);
254 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
261 machine_arch_initcall(mpc8568_mds, board_fixups);
262 machine_arch_initcall(mpc8569_mds, board_fixups);
264 static struct of_device_id mpc85xx_ids[] = {
266 { .compatible = "soc", },
267 { .compatible = "simple-bus", },
269 { .compatible = "fsl,qe", },
270 { .compatible = "gianfar", },
274 static int __init mpc85xx_publish_devices(void)
276 /* Publish the QE devices */
277 of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
281 machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
282 machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
284 static void __init mpc85xx_mds_pic_init(void)
288 struct device_node *np = NULL;
290 np = of_find_node_by_type(NULL, "open-pic");
294 if (of_address_to_resource(np, 0, &r)) {
295 printk(KERN_ERR "Failed to map mpic register space\n");
300 mpic = mpic_alloc(np, r.start,
301 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
302 0, 256, " OpenPIC ");
303 BUG_ON(mpic == NULL);
308 #ifdef CONFIG_QUICC_ENGINE
309 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
311 np = of_find_node_by_type(NULL, "qeic");
315 qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
317 #endif /* CONFIG_QUICC_ENGINE */
320 static int __init mpc85xx_mds_probe(void)
322 unsigned long root = of_get_flat_dt_root();
324 return of_flat_dt_is_compatible(root, "MPC85xxMDS");
327 define_machine(mpc8568_mds) {
328 .name = "MPC8568 MDS",
329 .probe = mpc85xx_mds_probe,
330 .setup_arch = mpc85xx_mds_setup_arch,
331 .init_IRQ = mpc85xx_mds_pic_init,
332 .get_irq = mpic_get_irq,
333 .restart = fsl_rstcr_restart,
334 .calibrate_decr = generic_calibrate_decr,
335 .progress = udbg_progress,
337 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
341 static int __init mpc8569_mds_probe(void)
343 unsigned long root = of_get_flat_dt_root();
345 return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS");
348 define_machine(mpc8569_mds) {
349 .name = "MPC8569 MDS",
350 .probe = mpc8569_mds_probe,
351 .setup_arch = mpc85xx_mds_setup_arch,
352 .init_IRQ = mpc85xx_mds_pic_init,
353 .get_irq = mpic_get_irq,
354 .restart = fsl_rstcr_restart,
355 .calibrate_decr = generic_calibrate_decr,
356 .progress = udbg_progress,
358 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,