arch/powerpc/platforms/83xx/mpc836x_mds.c

   1 /*
   2  * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
   3  *
   4  * Author: Li Yang <LeoLi@freescale.com>
   5  *         Yin Olivia <Hong-hua.Yin@freescale.com>
   6  *
   7  * Description:
   8  * MPC8360E MDS board specific routines.
   9  *
  10  * Changelog:
  11  * Jun 21, 2006 Initial version
  12  *
  13  * This program is free software; you can redistribute it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18
  19 #include <linux/stddef.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/reboot.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdev_t.h>
  26 #include <linux/major.h>
  27 #include <linux/console.h>
  28 #include <linux/delay.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/root_dev.h>
  31 #include <linux/initrd.h>
  32 #include <linux/of_platform.h>
  33 #include <linux/of_device.h>
  34
  35 #include <asm/system.h>
  36 #include <asm/atomic.h>
  37 #include <asm/time.h>
  38 #include <asm/io.h>
  39 #include <asm/machdep.h>
  40 #include <asm/ipic.h>
  41 #include <asm/irq.h>
  42 #include <asm/prom.h>
  43 #include <asm/udbg.h>
  44 #include <sysdev/fsl_soc.h>
  45 #include <sysdev/fsl_pci.h>
  46 #include <asm/qe.h>
  47 #include <asm/qe_ic.h>
  48
  49 #include "mpc83xx.h"
  50
  51 #undef DEBUG
  52 #ifdef DEBUG
  53 #define DBG(fmt...) udbg_printf(fmt)
  54 #else
  55 #define DBG(fmt...)
  56 #endif
  57
  58 static u8 *bcsr_regs = NULL;
  59
  60 /* ************************************************************************
  61  *
  62  * Setup the architecture
  63  *
  64  */
  65 static void __init mpc836x_mds_setup_arch(void)
  66 {
  67         struct device_node *np;
  68
  69         if (ppc_md.progress)
  70                 ppc_md.progress("mpc836x_mds_setup_arch()", 0);
  71
  72         /* Map BCSR area */
  73         np = of_find_node_by_name(NULL, "bcsr");
  74         if (np != 0) {
  75                 struct resource res;
  76
  77                 of_address_to_resource(np, 0, &res);
  78                 bcsr_regs = ioremap(res.start, res.end - res.start +1);
  79                 of_node_put(np);
  80         }
  81
  82 #ifdef CONFIG_PCI
  83         for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
  84                 mpc83xx_add_bridge(np);
  85 #endif
  86
  87 #ifdef CONFIG_QUICC_ENGINE
  88         qe_reset();
  89
  90         if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
  91                 par_io_init(np);
  92                 of_node_put(np);
  93
  94                 for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
  95                         par_io_of_config(np);
  96         }
  97
  98         if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
  99                         != NULL){
 100                 uint svid;
 101
 102                 /* Reset the Ethernet PHY */
 103 #define BCSR9_GETHRST 0x20
 104                 clrbits8(&bcsr_regs[9], BCSR9_GETHRST);
 105                 udelay(1000);
 106                 setbits8(&bcsr_regs[9], BCSR9_GETHRST);
 107
 108                 /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
 109                 svid = mfspr(SPRN_SVR);
 110                 if (svid == 0x80480021) {
 111                         void __iomem *immap;
 112
 113                         immap = ioremap(get_immrbase() + 0x14a8, 8);
 114
 115                         /*
 116                          * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
 117                          * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
 118                          */
 119                         setbits32(immap, 0x0c003000);
 120
 121                         /*
 122                          * IMMR + 0x14AC[20:27] = 10101010
 123                          * (data delay for both UCC's)
 124                          */
 125                         clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
 126
 127                         iounmap(immap);
 128                 }
 129
 130                 iounmap(bcsr_regs);
 131                 of_node_put(np);
 132         }
 133 #endif                          /* CONFIG_QUICC_ENGINE */
 134 }
 135
 136 static struct of_device_id mpc836x_ids[] = {
 137         { .type = "soc", },
 138         { .compatible = "soc", },
 139         { .compatible = "simple-bus", },
 140         { .type = "qe", },
 141         { .compatible = "fsl,qe", },
 142         {},
 143 };
 144
 145 static int __init mpc836x_declare_of_platform_devices(void)
 146 {
 147         /* Publish the QE devices */
 148         of_platform_bus_probe(NULL, mpc836x_ids, NULL);
 149
 150         return 0;
 151 }
 152 machine_device_initcall(mpc836x_mds, mpc836x_declare_of_platform_devices);
 153
 154 static void __init mpc836x_mds_init_IRQ(void)
 155 {
 156         struct device_node *np;
 157
 158         np = of_find_node_by_type(NULL, "ipic");
 159         if (!np)
 160                 return;
 161
 162         ipic_init(np, 0);
 163
 164         /* Initialize the default interrupt mapping priorities,
 165          * in case the boot rom changed something on us.
 166          */
 167         ipic_set_default_priority();
 168         of_node_put(np);
 169
 170 #ifdef CONFIG_QUICC_ENGINE
 171         np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
 172         if (!np) {
 173                 np = of_find_node_by_type(NULL, "qeic");
 174                 if (!np)
 175                         return;
 176         }
 177         qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
 178         of_node_put(np);
 179 #endif                          /* CONFIG_QUICC_ENGINE */
 180 }
 181
 182 /*
 183  * Called very early, MMU is off, device-tree isn't unflattened
 184  */
 185 static int __init mpc836x_mds_probe(void)
 186 {
 187         unsigned long root = of_get_flat_dt_root();
 188
 189         return of_flat_dt_is_compatible(root, "MPC836xMDS");
 190 }
 191
 192 define_machine(mpc836x_mds) {
 193         .name           = "MPC836x MDS",
 194         .probe          = mpc836x_mds_probe,
 195         .setup_arch     = mpc836x_mds_setup_arch,
 196         .init_IRQ       = mpc836x_mds_init_IRQ,
 197         .get_irq        = ipic_get_irq,
 198         .restart        = mpc83xx_restart,
 199         .time_init      = mpc83xx_time_init,
 200         .calibrate_decr = generic_calibrate_decr,
 201         .progress       = udbg_progress,
 202 };