arch/powerpc/boot/dts/tqm5200.dts

   1 /*
   2  * TQM5200 board Device Tree Source
   3  *
   4  * Copyright (C) 2007 Semihalf
   5  * Marian Balakowicz <m8@semihalf.com>
   6  *
   7  * This program is free software; you can redistribute  it and/or modify it
   8  * under  the terms of  the GNU General  Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  */
  12
  13 / {
  14         model = "tqc,tqm5200";
  15         compatible = "tqc,tqm5200";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 PowerPC,5200@0 {
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         d-cache-line-size = <20>;
  27                         i-cache-line-size = <20>;
  28                         d-cache-size = <4000>;          // L1, 16K
  29                         i-cache-size = <4000>;          // L1, 16K
  30                         timebase-frequency = <0>;       // from bootloader
  31                         bus-frequency = <0>;            // from bootloader
  32                         clock-frequency = <0>;          // from bootloader
  33                 };
  34         };
  35
  36         memory {
  37                 device_type = "memory";
  38                 reg = <00000000 04000000>;      // 64MB
  39         };
  40
  41         soc5200@f0000000 {
  42                 #address-cells = <1>;
  43                 #size-cells = <1>;
  44                 compatible = "fsl,mpc5200-immr";
  45                 ranges = <0 f0000000 0000c000>;
  46                 reg = <f0000000 00000100>;
  47                 bus-frequency = <0>;            // from bootloader
  48                 system-frequency = <0>;         // from bootloader
  49
  50                 cdm@200 {
  51                         compatible = "fsl,mpc5200-cdm";
  52                         reg = <200 38>;
  53                 };
  54
  55                 mpc5200_pic: interrupt-controller@500 {
  56                         // 5200 interrupts are encoded into two levels;
  57                         interrupt-controller;
  58                         #interrupt-cells = <3>;
  59                         compatible = "fsl,mpc5200-pic";
  60                         reg = <500 80>;
  61                 };
  62
  63                 timer@600 {     // General Purpose Timer
  64                         compatible = "fsl,mpc5200-gpt";
  65                         reg = <600 10>;
  66                         interrupts = <1 9 0>;
  67                         interrupt-parent = <&mpc5200_pic>;
  68                         fsl,has-wdt;
  69                 };
  70
  71                 gpio@b00 {
  72                         compatible = "fsl,mpc5200-gpio";
  73                         reg = <b00 40>;
  74                         interrupts = <1 7 0>;
  75                         interrupt-parent = <&mpc5200_pic>;
  76                 };
  77
  78                 usb@1000 {
  79                         compatible = "fsl,mpc5200-ohci","ohci-be";
  80                         reg = <1000 ff>;
  81                         interrupts = <2 6 0>;
  82                         interrupt-parent = <&mpc5200_pic>;
  83                 };
  84
  85                 dma-controller@1200 {
  86                         compatible = "fsl,mpc5200-bestcomm";
  87                         reg = <1200 80>;
  88                         interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
  89                                       3 4 0  3 5 0  3 6 0  3 7 0
  90                                       3 8 0  3 9 0  3 a 0  3 b 0
  91                                       3 c 0  3 d 0  3 e 0  3 f 0>;
  92                         interrupt-parent = <&mpc5200_pic>;
  93                 };
  94
  95                 xlb@1f00 {
  96                         compatible = "fsl,mpc5200-xlb";
  97                         reg = <1f00 100>;
  98                 };
  99
 100                 serial@2000 {           // PSC1
 101                         device_type = "serial";
 102                         compatible = "fsl,mpc5200-psc-uart";
 103                         port-number = <0>;  // Logical port assignment
 104                         reg = <2000 100>;
 105                         interrupts = <2 1 0>;
 106                         interrupt-parent = <&mpc5200_pic>;
 107                 };
 108
 109                 serial@2200 {           // PSC2
 110                         device_type = "serial";
 111                         compatible = "fsl,mpc5200-psc-uart";
 112                         port-number = <1>;  // Logical port assignment
 113                         reg = <2200 100>;
 114                         interrupts = <2 2 0>;
 115                         interrupt-parent = <&mpc5200_pic>;
 116                 };
 117
 118                 serial@2400 {           // PSC3
 119                         device_type = "serial";
 120                         compatible = "fsl,mpc5200-psc-uart";
 121                         port-number = <2>;  // Logical port assignment
 122                         reg = <2400 100>;
 123                         interrupts = <2 3 0>;
 124                         interrupt-parent = <&mpc5200_pic>;
 125                 };
 126
 127                 ethernet@3000 {
 128                         device_type = "network";
 129                         compatible = "fsl,mpc5200-fec";
 130                         reg = <3000 800>;
 131                         local-mac-address = [ 00 00 00 00 00 00 ];
 132                         interrupts = <2 5 0>;
 133                         interrupt-parent = <&mpc5200_pic>;
 134                 };
 135
 136                 ata@3a00 {
 137                         compatible = "fsl,mpc5200-ata";
 138                         reg = <3a00 100>;
 139                         interrupts = <2 7 0>;
 140                         interrupt-parent = <&mpc5200_pic>;
 141                 };
 142
 143                 i2c@3d40 {
 144                         compatible = "fsl,mpc5200-i2c","fsl-i2c";
 145                         reg = <3d40 40>;
 146                         interrupts = <2 10 0>;
 147                         interrupt-parent = <&mpc5200_pic>;
 148                         fsl5200-clocking;
 149                 };
 150
 151                 sram@8000 {
 152                         compatible = "fsl,mpc5200-sram";
 153                         reg = <8000 4000>;
 154                 };
 155         };
 156
 157         pci@f0000d00 {
 158                 #interrupt-cells = <1>;
 159                 #size-cells = <2>;
 160                 #address-cells = <3>;
 161                 device_type = "pci";
 162                 compatible = "fsl,mpc5200-pci";
 163                 reg = <f0000d00 100>;
 164                 interrupt-map-mask = <f800 0 0 7>;
 165                 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
 166                                  c000 0 0 2 &mpc5200_pic 0 0 3
 167                                  c000 0 0 3 &mpc5200_pic 0 0 3
 168                                  c000 0 0 4 &mpc5200_pic 0 0 3>;
 169                 clock-frequency = <0>; // From boot loader
 170                 interrupts = <2 8 0 2 9 0 2 a 0>;
 171                 interrupt-parent = <&mpc5200_pic>;
 172                 bus-range = <0 0>;
 173                 ranges = <42000000 0 80000000 80000000 0 10000000
 174                           02000000 0 90000000 90000000 0 10000000
 175                           01000000 0 00000000 a0000000 0 01000000>;
 176         };
 177 };