arch/powerpc/boot/dts/p5020si.dtsi

   1 /*
   2  * P5020 Silicon Device Tree Source
   3  *
   4  * Copyright 2010-2011 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 /dts-v1/;
  36
  37 / {
  38         compatible = "fsl,P5020";
  39         #address-cells = <2>;
  40         #size-cells = <2>;
  41         interrupt-parent = <&mpic>;
  42
  43         aliases {
  44                 ccsr = &soc;
  45
  46                 serial0 = &serial0;
  47                 serial1 = &serial1;
  48                 serial2 = &serial2;
  49                 serial3 = &serial3;
  50                 pci0 = &pci0;
  51                 pci1 = &pci1;
  52                 pci2 = &pci2;
  53                 pci3 = &pci3;
  54                 usb0 = &usb0;
  55                 usb1 = &usb1;
  56                 dma0 = &dma0;
  57                 dma1 = &dma1;
  58                 sdhc = &sdhc;
  59                 msi0 = &msi0;
  60                 msi1 = &msi1;
  61                 msi2 = &msi2;
  62
  63                 crypto = &crypto;
  64                 sec_jr0 = &sec_jr0;
  65                 sec_jr1 = &sec_jr1;
  66                 sec_jr2 = &sec_jr2;
  67                 sec_jr3 = &sec_jr3;
  68                 rtic_a = &rtic_a;
  69                 rtic_b = &rtic_b;
  70                 rtic_c = &rtic_c;
  71                 rtic_d = &rtic_d;
  72                 sec_mon = &sec_mon;
  73
  74 /*
  75                 rio0 = &rapidio0;
  76  */
  77         };
  78
  79         cpus {
  80                 #address-cells = <1>;
  81                 #size-cells = <0>;
  82
  83                 cpu0: PowerPC,e5500@0 {
  84                         device_type = "cpu";
  85                         reg = <0>;
  86                         next-level-cache = <&L2_0>;
  87                         L2_0: l2-cache {
  88                                 next-level-cache = <&cpc>;
  89                         };
  90                 };
  91                 cpu1: PowerPC,e5500@1 {
  92                         device_type = "cpu";
  93                         reg = <1>;
  94                         next-level-cache = <&L2_1>;
  95                         L2_1: l2-cache {
  96                                 next-level-cache = <&cpc>;
  97                         };
  98                 };
  99         };
 100
 101         soc: soc@ffe000000 {
 102                 #address-cells = <1>;
 103                 #size-cells = <1>;
 104                 device_type = "soc";
 105                 compatible = "simple-bus";
 106                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
 107                 reg = <0xf 0xfe000000 0 0x00001000>;
 108
 109                 soc-sram-error {
 110                         compatible = "fsl,soc-sram-error";
 111                         interrupts = <16 2 1 29>;
 112                 };
 113
 114                 corenet-law@0 {
 115                         compatible = "fsl,corenet-law";
 116                         reg = <0x0 0x1000>;
 117                         fsl,num-laws = <32>;
 118                 };
 119
 120                 memory-controller@8000 {
 121                         compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
 122                         reg = <0x8000 0x1000>;
 123                         interrupts = <16 2 1 23>;
 124                 };
 125
 126                 memory-controller@9000 {
 127                         compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
 128                         reg = <0x9000 0x1000>;
 129                         interrupts = <16 2 1 22>;
 130                 };
 131
 132                 cpc: l3-cache-controller@10000 {
 133                         compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
 134                         reg = <0x10000 0x1000
 135                                0x11000 0x1000>;
 136                         interrupts = <16 2 1 27
 137                                       16 2 1 26>;
 138                 };
 139
 140                 corenet-cf@18000 {
 141                         compatible = "fsl,corenet-cf";
 142                         reg = <0x18000 0x1000>;
 143                         interrupts = <16 2 1 31>;
 144                         fsl,ccf-num-csdids = <32>;
 145                         fsl,ccf-num-snoopids = <32>;
 146                 };
 147
 148                 iommu@20000 {
 149                         compatible = "fsl,pamu-v1.0", "fsl,pamu";
 150                         reg = <0x20000 0x4000>;
 151                         interrupts = <
 152                                 24 2 0 0
 153                                 16 2 1 30>;
 154                 };
 155
 156                 mpic: pic@40000 {
 157                         clock-frequency = <0>;
 158                         interrupt-controller;
 159                         #address-cells = <0>;
 160                         #interrupt-cells = <4>;
 161                         reg = <0x40000 0x40000>;
 162                         compatible = "fsl,mpic", "chrp,open-pic";
 163                         device_type = "open-pic";
 164                 };
 165
 166                 msi0: msi@41600 {
 167                         compatible = "fsl,mpic-msi";
 168                         reg = <0x41600 0x200>;
 169                         msi-available-ranges = <0 0x100>;
 170                         interrupts = <
 171                                 0xe0 0 0 0
 172                                 0xe1 0 0 0
 173                                 0xe2 0 0 0
 174                                 0xe3 0 0 0
 175                                 0xe4 0 0 0
 176                                 0xe5 0 0 0
 177                                 0xe6 0 0 0
 178                                 0xe7 0 0 0>;
 179                 };
 180
 181                 msi1: msi@41800 {
 182                         compatible = "fsl,mpic-msi";
 183                         reg = <0x41800 0x200>;
 184                         msi-available-ranges = <0 0x100>;
 185                         interrupts = <
 186                                 0xe8 0 0 0
 187                                 0xe9 0 0 0
 188                                 0xea 0 0 0
 189                                 0xeb 0 0 0
 190                                 0xec 0 0 0
 191                                 0xed 0 0 0
 192                                 0xee 0 0 0
 193                                 0xef 0 0 0>;
 194                 };
 195
 196                 msi2: msi@41a00 {
 197                         compatible = "fsl,mpic-msi";
 198                         reg = <0x41a00 0x200>;
 199                         msi-available-ranges = <0 0x100>;
 200                         interrupts = <
 201                                 0xf0 0 0 0
 202                                 0xf1 0 0 0
 203                                 0xf2 0 0 0
 204                                 0xf3 0 0 0
 205                                 0xf4 0 0 0
 206                                 0xf5 0 0 0
 207                                 0xf6 0 0 0
 208                                 0xf7 0 0 0>;
 209                 };
 210
 211                 guts: global-utilities@e0000 {
 212                         compatible = "fsl,qoriq-device-config-1.0";
 213                         reg = <0xe0000 0xe00>;
 214                         fsl,has-rstcr;
 215                         #sleep-cells = <1>;
 216                         fsl,liodn-bits = <12>;
 217                 };
 218
 219                 pins: global-utilities@e0e00 {
 220                         compatible = "fsl,qoriq-pin-control-1.0";
 221                         reg = <0xe0e00 0x200>;
 222                         #sleep-cells = <2>;
 223                 };
 224
 225                 clockgen: global-utilities@e1000 {
 226                         compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
 227                         reg = <0xe1000 0x1000>;
 228                         clock-frequency = <0>;
 229                 };
 230
 231                 rcpm: global-utilities@e2000 {
 232                         compatible = "fsl,qoriq-rcpm-1.0";
 233                         reg = <0xe2000 0x1000>;
 234                         #sleep-cells = <1>;
 235                 };
 236
 237                 sfp: sfp@e8000 {
 238                         compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
 239                         reg        = <0xe8000 0x1000>;
 240                 };
 241
 242                 serdes: serdes@ea000 {
 243                         compatible = "fsl,p5020-serdes";
 244                         reg        = <0xea000 0x1000>;
 245                 };
 246
 247                 dma0: dma@100300 {
 248                         #address-cells = <1>;
 249                         #size-cells = <1>;
 250                         compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
 251                         reg = <0x100300 0x4>;
 252                         ranges = <0x0 0x100100 0x200>;
 253                         cell-index = <0>;
 254                         dma-channel@0 {
 255                                 compatible = "fsl,p5020-dma-channel",
 256                                                 "fsl,eloplus-dma-channel";
 257                                 reg = <0x0 0x80>;
 258                                 cell-index = <0>;
 259                                 interrupts = <28 2 0 0>;
 260                         };
 261                         dma-channel@80 {
 262                                 compatible = "fsl,p5020-dma-channel",
 263                                                 "fsl,eloplus-dma-channel";
 264                                 reg = <0x80 0x80>;
 265                                 cell-index = <1>;
 266                                 interrupts = <29 2 0 0>;
 267                         };
 268                         dma-channel@100 {
 269                                 compatible = "fsl,p5020-dma-channel",
 270                                                 "fsl,eloplus-dma-channel";
 271                                 reg = <0x100 0x80>;
 272                                 cell-index = <2>;
 273                                 interrupts = <30 2 0 0>;
 274                         };
 275                         dma-channel@180 {
 276                                 compatible = "fsl,p5020-dma-channel",
 277                                                 "fsl,eloplus-dma-channel";
 278                                 reg = <0x180 0x80>;
 279                                 cell-index = <3>;
 280                                 interrupts = <31 2 0 0>;
 281                         };
 282                 };
 283
 284                 dma1: dma@101300 {
 285                         #address-cells = <1>;
 286                         #size-cells = <1>;
 287                         compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
 288                         reg = <0x101300 0x4>;
 289                         ranges = <0x0 0x101100 0x200>;
 290                         cell-index = <1>;
 291                         dma-channel@0 {
 292                                 compatible = "fsl,p5020-dma-channel",
 293                                                 "fsl,eloplus-dma-channel";
 294                                 reg = <0x0 0x80>;
 295                                 cell-index = <0>;
 296                                 interrupts = <32 2 0 0>;
 297                         };
 298                         dma-channel@80 {
 299                                 compatible = "fsl,p5020-dma-channel",
 300                                                 "fsl,eloplus-dma-channel";
 301                                 reg = <0x80 0x80>;
 302                                 cell-index = <1>;
 303                                 interrupts = <33 2 0 0>;
 304                         };
 305                         dma-channel@100 {
 306                                 compatible = "fsl,p5020-dma-channel",
 307                                                 "fsl,eloplus-dma-channel";
 308                                 reg = <0x100 0x80>;
 309                                 cell-index = <2>;
 310                                 interrupts = <34 2 0 0>;
 311                         };
 312                         dma-channel@180 {
 313                                 compatible = "fsl,p5020-dma-channel",
 314                                                 "fsl,eloplus-dma-channel";
 315                                 reg = <0x180 0x80>;
 316                                 cell-index = <3>;
 317                                 interrupts = <35 2 0 0>;
 318                         };
 319                 };
 320
 321                 spi@110000 {
 322                         #address-cells = <1>;
 323                         #size-cells = <0>;
 324                         compatible = "fsl,p5020-espi", "fsl,mpc8536-espi";
 325                         reg = <0x110000 0x1000>;
 326                         interrupts = <53 0x2 0 0>;
 327                         fsl,espi-num-chipselects = <4>;
 328                 };
 329
 330                 sdhc: sdhc@114000 {
 331                         compatible = "fsl,p5020-esdhc", "fsl,esdhc";
 332                         reg = <0x114000 0x1000>;
 333                         interrupts = <48 2 0 0>;
 334                         sdhci,auto-cmd12;
 335                         clock-frequency = <0>;
 336                 };
 337
 338                 i2c@118000 {
 339                         #address-cells = <1>;
 340                         #size-cells = <0>;
 341                         cell-index = <0>;
 342                         compatible = "fsl-i2c";
 343                         reg = <0x118000 0x100>;
 344                         interrupts = <38 2 0 0>;
 345                         dfsrr;
 346                 };
 347
 348                 i2c@118100 {
 349                         #address-cells = <1>;
 350                         #size-cells = <0>;
 351                         cell-index = <1>;
 352                         compatible = "fsl-i2c";
 353                         reg = <0x118100 0x100>;
 354                         interrupts = <38 2 0 0>;
 355                         dfsrr;
 356                 };
 357
 358                 i2c@119000 {
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361                         cell-index = <2>;
 362                         compatible = "fsl-i2c";
 363                         reg = <0x119000 0x100>;
 364                         interrupts = <39 2 0 0>;
 365                         dfsrr;
 366                 };
 367
 368                 i2c@119100 {
 369                         #address-cells = <1>;
 370                         #size-cells = <0>;
 371                         cell-index = <3>;
 372                         compatible = "fsl-i2c";
 373                         reg = <0x119100 0x100>;
 374                         interrupts = <39 2 0 0>;
 375                         dfsrr;
 376                 };
 377
 378                 serial0: serial@11c500 {
 379                         cell-index = <0>;
 380                         device_type = "serial";
 381                         compatible = "ns16550";
 382                         reg = <0x11c500 0x100>;
 383                         clock-frequency = <0>;
 384                         interrupts = <36 2 0 0>;
 385                 };
 386
 387                 serial1: serial@11c600 {
 388                         cell-index = <1>;
 389                         device_type = "serial";
 390                         compatible = "ns16550";
 391                         reg = <0x11c600 0x100>;
 392                         clock-frequency = <0>;
 393                         interrupts = <36 2 0 0>;
 394                 };
 395
 396                 serial2: serial@11d500 {
 397                         cell-index = <2>;
 398                         device_type = "serial";
 399                         compatible = "ns16550";
 400                         reg = <0x11d500 0x100>;
 401                         clock-frequency = <0>;
 402                         interrupts = <37 2 0 0>;
 403                 };
 404
 405                 serial3: serial@11d600 {
 406                         cell-index = <3>;
 407                         device_type = "serial";
 408                         compatible = "ns16550";
 409                         reg = <0x11d600 0x100>;
 410                         clock-frequency = <0>;
 411                         interrupts = <37 2 0 0>;
 412                 };
 413
 414                 gpio0: gpio@130000 {
 415                         compatible = "fsl,p5020-gpio", "fsl,qoriq-gpio";
 416                         reg = <0x130000 0x1000>;
 417                         interrupts = <55 2 0 0>;
 418                         #gpio-cells = <2>;
 419                         gpio-controller;
 420                 };
 421
 422                 usb0: usb@210000 {
 423                         compatible = "fsl,p5020-usb2-mph",
 424                                         "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
 425                         reg = <0x210000 0x1000>;
 426                         #address-cells = <1>;
 427                         #size-cells = <0>;
 428                         interrupts = <44 0x2 0 0>;
 429                         phy_type = "utmi";
 430                         port0;
 431                 };
 432
 433                 usb1: usb@211000 {
 434                         compatible = "fsl,p5020-usb2-dr",
 435                                         "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
 436                         reg = <0x211000 0x1000>;
 437                         #address-cells = <1>;
 438                         #size-cells = <0>;
 439                         interrupts = <45 0x2 0 0>;
 440                         dr_mode = "host";
 441                         phy_type = "utmi";
 442                 };
 443
 444                 sata@220000 {
 445                         compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
 446                         reg = <0x220000 0x1000>;
 447                         interrupts = <68 0x2 0 0>;
 448                 };
 449
 450                 sata@221000 {
 451                         compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
 452                         reg = <0x221000 0x1000>;
 453                         interrupts = <69 0x2 0 0>;
 454                 };
 455
 456                 crypto: crypto@300000 {
 457                         compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
 458                         #address-cells = <1>;
 459                         #size-cells = <1>;
 460                         reg              = <0x300000 0x10000>;
 461                         ranges           = <0 0x300000 0x10000>;
 462                         interrupts       = <92 2 0 0>;
 463
 464                         sec_jr0: jr@1000 {
 465                                 compatible = "fsl,sec-v4.2-job-ring",
 466                                              "fsl,sec-v4.0-job-ring";
 467                                 reg = <0x1000 0x1000>;
 468                                 interrupts = <88 2 0 0>;
 469                         };
 470
 471                         sec_jr1: jr@2000 {
 472                                 compatible = "fsl,sec-v4.2-job-ring",
 473                                              "fsl,sec-v4.0-job-ring";
 474                                 reg = <0x2000 0x1000>;
 475                                 interrupts = <89 2 0 0>;
 476                         };
 477
 478                         sec_jr2: jr@3000 {
 479                                 compatible = "fsl,sec-v4.2-job-ring",
 480                                              "fsl,sec-v4.0-job-ring";
 481                                 reg = <0x3000 0x1000>;
 482                                 interrupts = <90 2 0 0>;
 483                         };
 484
 485                         sec_jr3: jr@4000 {
 486                                 compatible = "fsl,sec-v4.2-job-ring",
 487                                              "fsl,sec-v4.0-job-ring";
 488                                 reg = <0x4000 0x1000>;
 489                                 interrupts = <91 2 0 0>;
 490                         };
 491
 492                         rtic@6000 {
 493                                 compatible = "fsl,sec-v4.2-rtic",
 494                                              "fsl,sec-v4.0-rtic";
 495                                 #address-cells = <1>;
 496                                 #size-cells = <1>;
 497                                 reg = <0x6000 0x100>;
 498                                 ranges = <0x0 0x6100 0xe00>;
 499
 500                                 rtic_a: rtic-a@0 {
 501                                         compatible = "fsl,sec-v4.2-rtic-memory",
 502                                                      "fsl,sec-v4.0-rtic-memory";
 503                                         reg = <0x00 0x20 0x100 0x80>;
 504                                 };
 505
 506                                 rtic_b: rtic-b@20 {
 507                                         compatible = "fsl,sec-v4.2-rtic-memory",
 508                                                      "fsl,sec-v4.0-rtic-memory";
 509                                         reg = <0x20 0x20 0x200 0x80>;
 510                                 };
 511
 512                                 rtic_c: rtic-c@40 {
 513                                         compatible = "fsl,sec-v4.2-rtic-memory",
 514                                                      "fsl,sec-v4.0-rtic-memory";
 515                                         reg = <0x40 0x20 0x300 0x80>;
 516                                 };
 517
 518                                 rtic_d: rtic-d@60 {
 519                                         compatible = "fsl,sec-v4.2-rtic-memory",
 520                                                      "fsl,sec-v4.0-rtic-memory";
 521                                         reg = <0x60 0x20 0x500 0x80>;
 522                                 };
 523                         };
 524                 };
 525
 526                 sec_mon: sec_mon@314000 {
 527                         compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
 528                         reg = <0x314000 0x1000>;
 529                         interrupts = <93 2 0 0>;
 530                 };
 531         };
 532
 533 /*
 534         rapidio0: rapidio@ffe0c0000
 535 */
 536
 537         localbus@ffe124000 {
 538                 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
 539                 interrupts = <25 2 0 0>;
 540                 #address-cells = <2>;
 541                 #size-cells = <1>;
 542         };
 543
 544         pci0: pcie@ffe200000 {
 545                 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
 546                 device_type = "pci";
 547                 #size-cells = <2>;
 548                 #address-cells = <3>;
 549                 bus-range = <0x0 0xff>;
 550                 clock-frequency = <0x1fca055>;
 551                 fsl,msi = <&msi0>;
 552                 interrupts = <16 2 1 15>;
 553
 554                 pcie@0 {
 555                         reg = <0 0 0 0 0>;
 556                         #interrupt-cells = <1>;
 557                         #size-cells = <2>;
 558                         #address-cells = <3>;
 559                         device_type = "pci";
 560                         interrupts = <16 2 1 15>;
 561                         interrupt-map-mask = <0xf800 0 0 7>;
 562                         interrupt-map = <
 563                                 /* IDSEL 0x0 */
 564                                 0000 0 0 1 &mpic 40 1 0 0
 565                                 0000 0 0 2 &mpic 1 1 0 0
 566                                 0000 0 0 3 &mpic 2 1 0 0
 567                                 0000 0 0 4 &mpic 3 1 0 0
 568                                 >;
 569                 };
 570         };
 571
 572         pci1: pcie@ffe201000 {
 573                 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
 574                 device_type = "pci";
 575                 #size-cells = <2>;
 576                 #address-cells = <3>;
 577                 bus-range = <0 0xff>;
 578                 clock-frequency = <0x1fca055>;
 579                 fsl,msi = <&msi1>;
 580                 interrupts = <16 2 1 14>;
 581                 pcie@0 {
 582                         reg = <0 0 0 0 0>;
 583                         #interrupt-cells = <1>;
 584                         #size-cells = <2>;
 585                         #address-cells = <3>;
 586                         device_type = "pci";
 587                         interrupts = <16 2 1 14>;
 588                         interrupt-map-mask = <0xf800 0 0 7>;
 589                         interrupt-map = <
 590                                 /* IDSEL 0x0 */
 591                                 0000 0 0 1 &mpic 41 1 0 0
 592                                 0000 0 0 2 &mpic 5 1 0 0
 593                                 0000 0 0 3 &mpic 6 1 0 0
 594                                 0000 0 0 4 &mpic 7 1 0 0
 595                                 >;
 596                 };
 597         };
 598
 599         pci2: pcie@ffe202000 {
 600                 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
 601                 device_type = "pci";
 602                 #size-cells = <2>;
 603                 #address-cells = <3>;
 604                 bus-range = <0x0 0xff>;
 605                 clock-frequency = <0x1fca055>;
 606                 fsl,msi = <&msi2>;
 607                 interrupts = <16 2 1 13>;
 608                 pcie@0 {
 609                         reg = <0 0 0 0 0>;
 610                         #interrupt-cells = <1>;
 611                         #size-cells = <2>;
 612                         #address-cells = <3>;
 613                         device_type = "pci";
 614                         interrupts = <16 2 1 13>;
 615                         interrupt-map-mask = <0xf800 0 0 7>;
 616                         interrupt-map = <
 617                                 /* IDSEL 0x0 */
 618                                 0000 0 0 1 &mpic 42 1 0 0
 619                                 0000 0 0 2 &mpic 9 1 0 0
 620                                 0000 0 0 3 &mpic 10 1 0 0
 621                                 0000 0 0 4 &mpic 11 1 0 0
 622                                 >;
 623                 };
 624         };
 625
 626         pci3: pcie@ffe203000 {
 627                 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
 628                 device_type = "pci";
 629                 #size-cells = <2>;
 630                 #address-cells = <3>;
 631                 bus-range = <0x0 0xff>;
 632                 clock-frequency = <0x1fca055>;
 633                 fsl,msi = <&msi2>;
 634                 interrupts = <16 2 1 12>;
 635                 pcie@0 {
 636                         reg = <0 0 0 0 0>;
 637                         #interrupt-cells = <1>;
 638                         #size-cells = <2>;
 639                         #address-cells = <3>;
 640                         device_type = "pci";
 641                         interrupts = <16 2 1 12>;
 642                         interrupt-map-mask = <0xf800 0 0 7>;
 643                         interrupt-map = <
 644                                 /* IDSEL 0x0 */
 645                                 0000 0 0 1 &mpic 43 1 0 0
 646                                 0000 0 0 2 &mpic 0 1 0 0
 647                                 0000 0 0 3 &mpic 4 1 0 0
 648                                 0000 0 0 4 &mpic 8 1 0 0
 649                                 >;
 650                 };
 651         };
 652 };