2 * P4080DS Device Tree Source
4 * Copyright 2009 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 model = "fsl,P4080DS";
16 compatible = "fsl,P4080DS";
43 cpu0: PowerPC,4080@0 {
46 next-level-cache = <&L2_0>;
50 cpu1: PowerPC,4080@1 {
53 next-level-cache = <&L2_1>;
57 cpu2: PowerPC,4080@2 {
60 next-level-cache = <&L2_2>;
64 cpu3: PowerPC,4080@3 {
67 next-level-cache = <&L2_3>;
71 cpu4: PowerPC,4080@4 {
74 next-level-cache = <&L2_4>;
78 cpu5: PowerPC,4080@5 {
81 next-level-cache = <&L2_5>;
85 cpu6: PowerPC,4080@6 {
88 next-level-cache = <&L2_6>;
92 cpu7: PowerPC,4080@7 {
95 next-level-cache = <&L2_7>;
102 device_type = "memory";
106 #address-cells = <1>;
109 compatible = "simple-bus";
110 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
111 reg = <0xf 0xfe000000 0 0x00001000>;
114 compatible = "fsl,corenet-law";
119 memory-controller@8000 {
120 compatible = "fsl,p4080-memory-controller";
121 reg = <0x8000 0x1000>;
122 interrupt-parent = <&mpic>;
123 interrupts = <0x12 2>;
126 memory-controller@9000 {
127 compatible = "fsl,p4080-memory-controller";
128 reg = <0x9000 0x1000>;
129 interrupt-parent = <&mpic>;
130 interrupts = <0x12 2>;
134 compatible = "fsl,corenet-cf";
135 reg = <0x18000 0x1000>;
136 fsl,ccf-num-csdids = <32>;
137 fsl,ccf-num-snoopids = <32>;
141 compatible = "fsl,p4080-pamu";
142 reg = <0x20000 0x10000>;
144 interrupt-parent = <&mpic>;
148 interrupt-controller;
149 #address-cells = <0>;
150 #interrupt-cells = <2>;
151 reg = <0x40000 0x40000>;
152 compatible = "chrp,open-pic";
153 device_type = "open-pic";
157 #address-cells = <1>;
159 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
160 reg = <0x100300 0x4>;
161 ranges = <0x0 0x100100 0x200>;
164 compatible = "fsl,p4080-dma-channel",
165 "fsl,eloplus-dma-channel";
168 interrupt-parent = <&mpic>;
172 compatible = "fsl,p4080-dma-channel",
173 "fsl,eloplus-dma-channel";
176 interrupt-parent = <&mpic>;
180 compatible = "fsl,p4080-dma-channel",
181 "fsl,eloplus-dma-channel";
184 interrupt-parent = <&mpic>;
188 compatible = "fsl,p4080-dma-channel",
189 "fsl,eloplus-dma-channel";
192 interrupt-parent = <&mpic>;
198 #address-cells = <1>;
200 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
201 reg = <0x101300 0x4>;
202 ranges = <0x0 0x101100 0x200>;
205 compatible = "fsl,p4080-dma-channel",
206 "fsl,eloplus-dma-channel";
209 interrupt-parent = <&mpic>;
213 compatible = "fsl,p4080-dma-channel",
214 "fsl,eloplus-dma-channel";
217 interrupt-parent = <&mpic>;
221 compatible = "fsl,p4080-dma-channel",
222 "fsl,eloplus-dma-channel";
225 interrupt-parent = <&mpic>;
229 compatible = "fsl,p4080-dma-channel",
230 "fsl,eloplus-dma-channel";
233 interrupt-parent = <&mpic>;
240 #address-cells = <1>;
242 compatible = "fsl,espi";
243 reg = <0x110000 0x1000>;
244 interrupts = <53 0x2>;
245 interrupt-parent = <&mpic>;
246 espi,num-ss-bits = <4>;
250 #address-cells = <1>;
252 compatible = "fsl,espi-flash";
254 linux,modalias = "fsl_m25p80";
255 spi-max-frequency = <40000000>; /* input clock */
258 reg = <0x00000000 0x00100000>;
263 reg = <0x00100000 0x00500000>;
268 reg = <0x00600000 0x00100000>;
272 label = "file system";
273 reg = <0x00700000 0x00900000>;
279 compatible = "fsl,p4080-esdhc", "fsl,esdhc";
280 reg = <0x114000 0x1000>;
282 interrupt-parent = <&mpic>;
283 voltage-ranges = <3300 3300>;
288 #address-cells = <1>;
291 compatible = "fsl-i2c";
292 reg = <0x118000 0x100>;
294 interrupt-parent = <&mpic>;
299 #address-cells = <1>;
302 compatible = "fsl-i2c";
303 reg = <0x118100 0x100>;
305 interrupt-parent = <&mpic>;
308 compatible = "at24,24c256";
312 compatible = "at24,24c256";
316 compatible = "dallas,ds3232";
318 interrupts = <0 0x1>;
319 interrupt-parent = <&mpic>;
324 #address-cells = <1>;
327 compatible = "fsl-i2c";
328 reg = <0x119000 0x100>;
330 interrupt-parent = <&mpic>;
335 #address-cells = <1>;
338 compatible = "fsl-i2c";
339 reg = <0x119100 0x100>;
341 interrupt-parent = <&mpic>;
345 serial0: serial@11c500 {
347 device_type = "serial";
348 compatible = "ns16550";
349 reg = <0x11c500 0x100>;
350 clock-frequency = <0>;
352 interrupt-parent = <&mpic>;
355 serial1: serial@11c600 {
357 device_type = "serial";
358 compatible = "ns16550";
359 reg = <0x11c600 0x100>;
360 clock-frequency = <0>;
362 interrupt-parent = <&mpic>;
365 serial2: serial@11d500 {
367 device_type = "serial";
368 compatible = "ns16550";
369 reg = <0x11d500 0x100>;
370 clock-frequency = <0>;
372 interrupt-parent = <&mpic>;
375 serial3: serial@11d600 {
377 device_type = "serial";
378 compatible = "ns16550";
379 reg = <0x11d600 0x100>;
380 clock-frequency = <0>;
382 interrupt-parent = <&mpic>;
386 compatible = "fsl,p4080-gpio";
387 reg = <0x130000 0x1000>;
389 interrupt-parent = <&mpic>;
395 compatible = "fsl,p4080-usb2-mph",
396 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
397 reg = <0x210000 0x1000>;
398 #address-cells = <1>;
400 interrupt-parent = <&mpic>;
401 interrupts = <44 0x2>;
406 compatible = "fsl,p4080-usb2-dr",
407 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
408 reg = <0x211000 0x1000>;
409 #address-cells = <1>;
411 interrupt-parent = <&mpic>;
412 interrupts = <45 0x2>;
418 rapidio0: rapidio@ffe0c0000 {
419 #address-cells = <2>;
421 compatible = "fsl,rapidio-delta";
422 reg = <0xf 0xfe0c0000 0 0x20000>;
423 ranges = <0 0 0xf 0xf5000000 0 0x01000000>;
424 interrupt-parent = <&mpic>;
425 /* err_irq bell_outb_irq bell_inb_irq
426 msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */
427 interrupts = <16 2 56 2 57 2 60 2 61 2 62 2 63 2>;
431 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
432 reg = <0xf 0xfe124000 0 0x1000>;
434 #address-cells = <2>;
437 ranges = <0 0 0xf 0xe8000000 0x08000000>;
440 compatible = "cfi-flash";
441 reg = <0 0 0x08000000>;
447 pci0: pcie@ffe200000 {
448 compatible = "fsl,p4080-pcie";
450 #interrupt-cells = <1>;
452 #address-cells = <3>;
453 reg = <0xf 0xfe200000 0 0x1000>;
454 bus-range = <0x0 0xff>;
455 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
456 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
457 clock-frequency = <0x1fca055>;
458 interrupt-parent = <&mpic>;
461 interrupt-map-mask = <0xf800 0 0 7>;
464 0000 0 0 1 &mpic 40 1
472 #address-cells = <3>;
474 ranges = <0x02000000 0 0xe0000000
475 0x02000000 0 0xe0000000
478 0x01000000 0 0x00000000
479 0x01000000 0 0x00000000
484 pci1: pcie@ffe201000 {
485 compatible = "fsl,p4080-pcie";
487 #interrupt-cells = <1>;
489 #address-cells = <3>;
490 reg = <0xf 0xfe201000 0 0x1000>;
491 bus-range = <0 0xff>;
492 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
493 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
494 clock-frequency = <0x1fca055>;
495 interrupt-parent = <&mpic>;
497 interrupt-map-mask = <0xf800 0 0 7>;
500 0000 0 0 1 &mpic 41 1
508 #address-cells = <3>;
510 ranges = <0x02000000 0 0xe0000000
511 0x02000000 0 0xe0000000
514 0x01000000 0 0x00000000
515 0x01000000 0 0x00000000
520 pci2: pcie@ffe202000 {
521 compatible = "fsl,p4080-pcie";
523 #interrupt-cells = <1>;
525 #address-cells = <3>;
526 reg = <0xf 0xfe202000 0 0x1000>;
527 bus-range = <0x0 0xff>;
528 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
529 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
530 clock-frequency = <0x1fca055>;
531 interrupt-parent = <&mpic>;
533 interrupt-map-mask = <0xf800 0 0 7>;
536 0000 0 0 1 &mpic 42 1
538 0000 0 0 3 &mpic 10 1
539 0000 0 0 4 &mpic 11 1
544 #address-cells = <3>;
546 ranges = <0x02000000 0 0xe0000000
547 0x02000000 0 0xe0000000
550 0x01000000 0 0x00000000
551 0x01000000 0 0x00000000