arch/powerpc/boot/dts/p4080ds.dts

   1 /*
   2  * P4080DS Device Tree Source
   3  *
   4  * Copyright 2009-2011 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 /include/ "p4080si.dtsi"
  36
  37 / {
  38         model = "fsl,P4080DS";
  39         compatible = "fsl,P4080DS";
  40         #address-cells = <2>;
  41         #size-cells = <2>;
  42         interrupt-parent = <&mpic>;
  43
  44         memory {
  45                 device_type = "memory";
  46         };
  47
  48         dcsr: dcsr@f00000000 {
  49                 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
  50         };
  51
  52         soc: soc@ffe000000 {
  53                 spi@110000 {
  54                         flash@0 {
  55                                 #address-cells = <1>;
  56                                 #size-cells = <1>;
  57                                 compatible = "spansion,s25sl12801";
  58                                 reg = <0>;
  59                                 spi-max-frequency = <40000000>; /* input clock */
  60                                 partition@u-boot {
  61                                         label = "u-boot";
  62                                         reg = <0x00000000 0x00100000>;
  63                                         read-only;
  64                                 };
  65                                 partition@kernel {
  66                                         label = "kernel";
  67                                         reg = <0x00100000 0x00500000>;
  68                                         read-only;
  69                                 };
  70                                 partition@dtb {
  71                                         label = "dtb";
  72                                         reg = <0x00600000 0x00100000>;
  73                                         read-only;
  74                                 };
  75                                 partition@fs {
  76                                         label = "file system";
  77                                         reg = <0x00700000 0x00900000>;
  78                                 };
  79                         };
  80                 };
  81
  82                 i2c@118100 {
  83                         eeprom@51 {
  84                                 compatible = "at24,24c256";
  85                                 reg = <0x51>;
  86                         };
  87                         eeprom@52 {
  88                                 compatible = "at24,24c256";
  89                                 reg = <0x52>;
  90                         };
  91                         rtc@68 {
  92                                 compatible = "dallas,ds3232";
  93                                 reg = <0x68>;
  94                                 interrupts = <0x1 0x1 0 0>;
  95                         };
  96                 };
  97
  98                 usb0: usb@210000 {
  99                         phy_type = "ulpi";
 100                 };
 101
 102                 usb1: usb@211000 {
 103                         dr_mode = "host";
 104                         phy_type = "ulpi";
 105                 };
 106         };
 107
 108         rapidio0: rapidio@ffe0c0000 {
 109                 reg = <0xf 0xfe0c0000 0 0x20000>;
 110                 ranges = <0 0 0xc 0x20000000 0 0x01000000>;
 111         };
 112
 113         localbus@ffe124000 {
 114                 reg = <0xf 0xfe124000 0 0x1000>;
 115                 ranges = <0 0 0xf 0xe8000000 0x08000000
 116                           3 0 0xf 0xffdf0000 0x00008000>;
 117
 118                 flash@0,0 {
 119                         compatible = "cfi-flash";
 120                         reg = <0 0 0x08000000>;
 121                         bank-width = <2>;
 122                         device-width = <2>;
 123                 };
 124
 125                 board-control@3,0 {
 126                         compatible = "fsl,p4080ds-fpga", "fsl,fpga-ngpixis";
 127                         reg = <3 0 0x30>;
 128                 };
 129         };
 130
 131         pci0: pcie@ffe200000 {
 132                 reg = <0xf 0xfe200000 0 0x1000>;
 133                 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
 134                           0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
 135                 pcie@0 {
 136                         ranges = <0x02000000 0 0xe0000000
 137                                   0x02000000 0 0xe0000000
 138                                   0 0x20000000
 139
 140                                   0x01000000 0 0x00000000
 141                                   0x01000000 0 0x00000000
 142                                   0 0x00010000>;
 143                 };
 144         };
 145
 146         pci1: pcie@ffe201000 {
 147                 reg = <0xf 0xfe201000 0 0x1000>;
 148                 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
 149                           0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
 150                 pcie@0 {
 151                         ranges = <0x02000000 0 0xe0000000
 152                                   0x02000000 0 0xe0000000
 153                                   0 0x20000000
 154
 155                                   0x01000000 0 0x00000000
 156                                   0x01000000 0 0x00000000
 157                                   0 0x00010000>;
 158                 };
 159         };
 160
 161         pci2: pcie@ffe202000 {
 162                 reg = <0xf 0xfe202000 0 0x1000>;
 163                 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
 164                           0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
 165                 pcie@0 {
 166                         ranges = <0x02000000 0 0xe0000000
 167                                   0x02000000 0 0xe0000000
 168                                   0 0x20000000
 169
 170                                   0x01000000 0 0x00000000
 171                                   0x01000000 0 0x00000000
 172                                   0 0x00010000>;
 173                 };
 174         };
 175
 176 };