arch/powerpc/boot/dts/p3041ds.dts

   1 /*
   2  * P3041DS Device Tree Source
   3  *
   4  * Copyright 2010-2011 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 /include/ "p3041si.dtsi"
  36
  37 / {
  38         model = "fsl,P3041DS";
  39         compatible = "fsl,P3041DS";
  40         #address-cells = <2>;
  41         #size-cells = <2>;
  42         interrupt-parent = <&mpic>;
  43
  44         memory {
  45                 device_type = "memory";
  46         };
  47
  48         dcsr: dcsr@f00000000 {
  49                 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
  50         };
  51
  52         soc: soc@ffe000000 {
  53                 spi@110000 {
  54                         flash@0 {
  55                                 #address-cells = <1>;
  56                                 #size-cells = <1>;
  57                                 compatible = "spansion,s25sl12801";
  58                                 reg = <0>;
  59                                 spi-max-frequency = <40000000>; /* input clock */
  60                                 partition@u-boot {
  61                                         label = "u-boot";
  62                                         reg = <0x00000000 0x00100000>;
  63                                         read-only;
  64                                 };
  65                                 partition@kernel {
  66                                         label = "kernel";
  67                                         reg = <0x00100000 0x00500000>;
  68                                         read-only;
  69                                 };
  70                                 partition@dtb {
  71                                         label = "dtb";
  72                                         reg = <0x00600000 0x00100000>;
  73                                         read-only;
  74                                 };
  75                                 partition@fs {
  76                                         label = "file system";
  77                                         reg = <0x00700000 0x00900000>;
  78                                 };
  79                         };
  80                 };
  81
  82                 i2c@118100 {
  83                         eeprom@51 {
  84                                 compatible = "at24,24c256";
  85                                 reg = <0x51>;
  86                         };
  87                         eeprom@52 {
  88                                 compatible = "at24,24c256";
  89                                 reg = <0x52>;
  90                         };
  91                 };
  92
  93                 i2c@119100 {
  94                         rtc@68 {
  95                                 compatible = "dallas,ds3232";
  96                                 reg = <0x68>;
  97                                 interrupts = <0x1 0x1 0 0>;
  98                         };
  99                 };
 100         };
 101
 102         localbus@ffe124000 {
 103                 reg = <0xf 0xfe124000 0 0x1000>;
 104                 ranges = <0 0 0xf 0xe8000000 0x08000000
 105                           2 0 0xf 0xffa00000 0x00040000
 106                           3 0 0xf 0xffdf0000 0x00008000>;
 107
 108                 flash@0,0 {
 109                         compatible = "cfi-flash";
 110                         reg = <0 0 0x08000000>;
 111                         bank-width = <2>;
 112                         device-width = <2>;
 113                 };
 114
 115                 nand@2,0 {
 116                         #address-cells = <1>;
 117                         #size-cells = <1>;
 118                         compatible = "fsl,elbc-fcm-nand";
 119                         reg = <0x2 0x0 0x40000>;
 120
 121                         partition@0 {
 122                                 label = "NAND U-Boot Image";
 123                                 reg = <0x0 0x02000000>;
 124                                 read-only;
 125                         };
 126
 127                         partition@2000000 {
 128                                 label = "NAND Root File System";
 129                                 reg = <0x02000000 0x10000000>;
 130                         };
 131
 132                         partition@12000000 {
 133                                 label = "NAND Compressed RFS Image";
 134                                 reg = <0x12000000 0x08000000>;
 135                         };
 136
 137                         partition@1a000000 {
 138                                 label = "NAND Linux Kernel Image";
 139                                 reg = <0x1a000000 0x04000000>;
 140                         };
 141
 142                         partition@1e000000 {
 143                                 label = "NAND DTB Image";
 144                                 reg = <0x1e000000 0x01000000>;
 145                         };
 146
 147                         partition@1f000000 {
 148                                 label = "NAND Writable User area";
 149                                 reg = <0x1f000000 0x21000000>;
 150                         };
 151                 };
 152
 153                 board-control@3,0 {
 154                         compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis";
 155                         reg = <3 0 0x30>;
 156                 };
 157         };
 158
 159         pci0: pcie@ffe200000 {
 160                 reg = <0xf 0xfe200000 0 0x1000>;
 161                 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
 162                           0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
 163                 pcie@0 {
 164                         ranges = <0x02000000 0 0xe0000000
 165                                   0x02000000 0 0xe0000000
 166                                   0 0x20000000
 167
 168                                   0x01000000 0 0x00000000
 169                                   0x01000000 0 0x00000000
 170                                   0 0x00010000>;
 171                 };
 172         };
 173
 174         pci1: pcie@ffe201000 {
 175                 reg = <0xf 0xfe201000 0 0x1000>;
 176                 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
 177                           0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
 178                 pcie@0 {
 179                         ranges = <0x02000000 0 0xe0000000
 180                                   0x02000000 0 0xe0000000
 181                                   0 0x20000000
 182
 183                                   0x01000000 0 0x00000000
 184                                   0x01000000 0 0x00000000
 185                                   0 0x00010000>;
 186                 };
 187         };
 188
 189         pci2: pcie@ffe202000 {
 190                 reg = <0xf 0xfe202000 0 0x1000>;
 191                 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
 192                           0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
 193                 pcie@0 {
 194                         ranges = <0x02000000 0 0xe0000000
 195                                   0x02000000 0 0xe0000000
 196                                   0 0x20000000
 197
 198                                   0x01000000 0 0x00000000
 199                                   0x01000000 0 0x00000000
 200                                   0 0x00010000>;
 201                 };
 202         };
 203
 204         pci3: pcie@ffe203000 {
 205                 reg = <0xf 0xfe203000 0 0x1000>;
 206                 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
 207                           0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
 208                 pcie@0 {
 209                         ranges = <0x02000000 0 0xe0000000
 210                                   0x02000000 0 0xe0000000
 211                                   0 0x20000000
 212
 213                                   0x01000000 0 0x00000000
 214                                   0x01000000 0 0x00000000
 215                                   0 0x00010000>;
 216                 };
 217         };
 218 };