arch/powerpc/boot/dts/p1020rdb.dts

   1 /*
   2  * P1020 RDB Device Tree Source
   3  *
   4  * Copyright 2009 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13 / {
  14         model = "fsl,P1020";
  15         compatible = "fsl,P1020RDB";
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 serial0 = &serial0;
  21                 serial1 = &serial1;
  22                 pci0 = &pci0;
  23                 pci1 = &pci1;
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 PowerPC,P1020@0 {
  31                         device_type = "cpu";
  32                         reg = <0x0>;
  33                         next-level-cache = <&L2>;
  34                 };
  35
  36                 PowerPC,P1020@1 {
  37                         device_type = "cpu";
  38                         reg = <0x1>;
  39                         next-level-cache = <&L2>;
  40                 };
  41         };
  42
  43         memory {
  44                 device_type = "memory";
  45         };
  46
  47         localbus@ffe05000 {
  48                 #address-cells = <2>;
  49                 #size-cells = <1>;
  50                 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
  51                 reg = <0 0xffe05000 0 0x1000>;
  52                 interrupts = <19 2>;
  53                 interrupt-parent = <&mpic>;
  54
  55                 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
  56                 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
  57                           0x1 0x0 0x0 0xffa00000 0x00040000
  58                           0x2 0x0 0x0 0xffb00000 0x00020000>;
  59
  60                 nor@0,0 {
  61                         #address-cells = <1>;
  62                         #size-cells = <1>;
  63                         compatible = "cfi-flash";
  64                         reg = <0x0 0x0 0x1000000>;
  65                         bank-width = <2>;
  66                         device-width = <1>;
  67
  68                         partition@0 {
  69                                 /* This location must not be altered  */
  70                                 /* 256KB for Vitesse 7385 Switch firmware */
  71                                 reg = <0x0 0x00040000>;
  72                                 label = "NOR (RO) Vitesse-7385 Firmware";
  73                                 read-only;
  74                         };
  75
  76                         partition@40000 {
  77                                 /* 256KB for DTB Image */
  78                                 reg = <0x00040000 0x00040000>;
  79                                 label = "NOR (RO) DTB Image";
  80                                 read-only;
  81                         };
  82
  83                         partition@80000 {
  84                                 /* 3.5 MB for Linux Kernel Image */
  85                                 reg = <0x00080000 0x00380000>;
  86                                 label = "NOR (RO) Linux Kernel Image";
  87                                 read-only;
  88                         };
  89
  90                         partition@400000 {
  91                                 /* 11MB for JFFS2 based Root file System */
  92                                 reg = <0x00400000 0x00b00000>;
  93                                 label = "NOR (RW) JFFS2 Root File System";
  94                         };
  95
  96                         partition@f00000 {
  97                                 /* This location must not be altered  */
  98                                 /* 512KB for u-boot Bootloader Image */
  99                                 /* 512KB for u-boot Environment Variables */
 100                                 reg = <0x00f00000 0x00100000>;
 101                                 label = "NOR (RO) U-Boot Image";
 102                                 read-only;
 103                         };
 104                 };
 105
 106                 nand@1,0 {
 107                         #address-cells = <1>;
 108                         #size-cells = <1>;
 109                         compatible = "fsl,p1020-fcm-nand",
 110                                      "fsl,elbc-fcm-nand";
 111                         reg = <0x1 0x0 0x40000>;
 112
 113                         partition@0 {
 114                                 /* This location must not be altered  */
 115                                 /* 1MB for u-boot Bootloader Image */
 116                                 reg = <0x0 0x00100000>;
 117                                 label = "NAND (RO) U-Boot Image";
 118                                 read-only;
 119                         };
 120
 121                         partition@100000 {
 122                                 /* 1MB for DTB Image */
 123                                 reg = <0x00100000 0x00100000>;
 124                                 label = "NAND (RO) DTB Image";
 125                                 read-only;
 126                         };
 127
 128                         partition@200000 {
 129                                 /* 4MB for Linux Kernel Image */
 130                                 reg = <0x00200000 0x00400000>;
 131                                 label = "NAND (RO) Linux Kernel Image";
 132                                 read-only;
 133                         };
 134
 135                         partition@600000 {
 136                                 /* 4MB for Compressed Root file System Image */
 137                                 reg = <0x00600000 0x00400000>;
 138                                 label = "NAND (RO) Compressed RFS Image";
 139                                 read-only;
 140                         };
 141
 142                         partition@a00000 {
 143                                 /* 7MB for JFFS2 based Root file System */
 144                                 reg = <0x00a00000 0x00700000>;
 145                                 label = "NAND (RW) JFFS2 Root File System";
 146                         };
 147
 148                         partition@1100000 {
 149                                 /* 15MB for JFFS2 based Root file System */
 150                                 reg = <0x01100000 0x00f00000>;
 151                                 label = "NAND (RW) Writable User area";
 152                         };
 153                 };
 154
 155                 L2switch@2,0 {
 156                         #address-cells = <1>;
 157                         #size-cells = <1>;
 158                         compatible = "vitesse-7385";
 159                         reg = <0x2 0x0 0x20000>;
 160                 };
 161
 162         };
 163
 164         soc@ffe00000 {
 165                 #address-cells = <1>;
 166                 #size-cells = <1>;
 167                 device_type = "soc";
 168                 compatible = "fsl,p1020-immr", "simple-bus";
 169                 ranges = <0x0  0x0 0xffe00000 0x100000>;
 170                 bus-frequency = <0>;            // Filled out by uboot.
 171
 172                 ecm-law@0 {
 173                         compatible = "fsl,ecm-law";
 174                         reg = <0x0 0x1000>;
 175                         fsl,num-laws = <12>;
 176                 };
 177
 178                 ecm@1000 {
 179                         compatible = "fsl,p1020-ecm", "fsl,ecm";
 180                         reg = <0x1000 0x1000>;
 181                         interrupts = <16 2>;
 182                         interrupt-parent = <&mpic>;
 183                 };
 184
 185                 memory-controller@2000 {
 186                         compatible = "fsl,p1020-memory-controller";
 187                         reg = <0x2000 0x1000>;
 188                         interrupt-parent = <&mpic>;
 189                         interrupts = <16 2>;
 190                 };
 191
 192                 i2c@3000 {
 193                         #address-cells = <1>;
 194                         #size-cells = <0>;
 195                         cell-index = <0>;
 196                         compatible = "fsl-i2c";
 197                         reg = <0x3000 0x100>;
 198                         interrupts = <43 2>;
 199                         interrupt-parent = <&mpic>;
 200                         dfsrr;
 201                         rtc@68 {
 202                                 compatible = "dallas,ds1339";
 203                                 reg = <0x68>;
 204                         };
 205                 };
 206
 207                 i2c@3100 {
 208                         #address-cells = <1>;
 209                         #size-cells = <0>;
 210                         cell-index = <1>;
 211                         compatible = "fsl-i2c";
 212                         reg = <0x3100 0x100>;
 213                         interrupts = <43 2>;
 214                         interrupt-parent = <&mpic>;
 215                         dfsrr;
 216                 };
 217
 218                 serial0: serial@4500 {
 219                         cell-index = <0>;
 220                         device_type = "serial";
 221                         compatible = "ns16550";
 222                         reg = <0x4500 0x100>;
 223                         clock-frequency = <0>;
 224                         interrupts = <42 2>;
 225                         interrupt-parent = <&mpic>;
 226                 };
 227
 228                 serial1: serial@4600 {
 229                         cell-index = <1>;
 230                         device_type = "serial";
 231                         compatible = "ns16550";
 232                         reg = <0x4600 0x100>;
 233                         clock-frequency = <0>;
 234                         interrupts = <42 2>;
 235                         interrupt-parent = <&mpic>;
 236                 };
 237
 238                 spi@7000 {
 239                         cell-index = <0>;
 240                         #address-cells = <1>;
 241                         #size-cells = <0>;
 242                         compatible = "fsl,espi";
 243                         reg = <0x7000 0x1000>;
 244                         interrupts = <59 0x2>;
 245                         interrupt-parent = <&mpic>;
 246                         mode = "cpu";
 247
 248                         fsl_m25p80@0 {
 249                                 #address-cells = <1>;
 250                                 #size-cells = <1>;
 251                                 compatible = "fsl,espi-flash";
 252                                 reg = <0>;
 253                                 linux,modalias = "fsl_m25p80";
 254                                 modal = "s25sl128b";
 255                                 spi-max-frequency = <50000000>;
 256                                 mode = <0>;
 257
 258                                 partition@0 {
 259                                         /* 512KB for u-boot Bootloader Image */
 260                                         reg = <0x0 0x00080000>;
 261                                         label = "SPI (RO) U-Boot Image";
 262                                         read-only;
 263                                 };
 264
 265                                 partition@80000 {
 266                                         /* 512KB for DTB Image */
 267                                         reg = <0x00080000 0x00080000>;
 268                                         label = "SPI (RO) DTB Image";
 269                                         read-only;
 270                                 };
 271
 272                                 partition@100000 {
 273                                         /* 4MB for Linux Kernel Image */
 274                                         reg = <0x00100000 0x00400000>;
 275                                         label = "SPI (RO) Linux Kernel Image";
 276                                         read-only;
 277                                 };
 278
 279                                 partition@500000 {
 280                                         /* 4MB for Compressed RFS Image */
 281                                         reg = <0x00500000 0x00400000>;
 282                                         label = "SPI (RO) Compressed RFS Image";
 283                                         read-only;
 284                                 };
 285
 286                                 partition@900000 {
 287                                         /* 7MB for JFFS2 based RFS */
 288                                         reg = <0x00900000 0x00700000>;
 289                                         label = "SPI (RW) JFFS2 RFS";
 290                                 };
 291                         };
 292                 };
 293
 294                 gpio: gpio-controller@f000 {
 295                         #gpio-cells = <2>;
 296                         compatible = "fsl,mpc8572-gpio";
 297                         reg = <0xf000 0x100>;
 298                         interrupts = <47 0x2>;
 299                         interrupt-parent = <&mpic>;
 300                         gpio-controller;
 301                 };
 302
 303                 L2: l2-cache-controller@20000 {
 304                         compatible = "fsl,p1020-l2-cache-controller";
 305                         reg = <0x20000 0x1000>;
 306                         cache-line-size = <32>; // 32 bytes
 307                         cache-size = <0x40000>; // L2,256K
 308                         interrupt-parent = <&mpic>;
 309                         interrupts = <16 2>;
 310                 };
 311
 312                 dma@21300 {
 313                         #address-cells = <1>;
 314                         #size-cells = <1>;
 315                         compatible = "fsl,eloplus-dma";
 316                         reg = <0x21300 0x4>;
 317                         ranges = <0x0 0x21100 0x200>;
 318                         cell-index = <0>;
 319                         dma-channel@0 {
 320                                 compatible = "fsl,eloplus-dma-channel";
 321                                 reg = <0x0 0x80>;
 322                                 cell-index = <0>;
 323                                 interrupt-parent = <&mpic>;
 324                                 interrupts = <20 2>;
 325                         };
 326                         dma-channel@80 {
 327                                 compatible = "fsl,eloplus-dma-channel";
 328                                 reg = <0x80 0x80>;
 329                                 cell-index = <1>;
 330                                 interrupt-parent = <&mpic>;
 331                                 interrupts = <21 2>;
 332                         };
 333                         dma-channel@100 {
 334                                 compatible = "fsl,eloplus-dma-channel";
 335                                 reg = <0x100 0x80>;
 336                                 cell-index = <2>;
 337                                 interrupt-parent = <&mpic>;
 338                                 interrupts = <22 2>;
 339                         };
 340                         dma-channel@180 {
 341                                 compatible = "fsl,eloplus-dma-channel";
 342                                 reg = <0x180 0x80>;
 343                                 cell-index = <3>;
 344                                 interrupt-parent = <&mpic>;
 345                                 interrupts = <23 2>;
 346                         };
 347                 };
 348
 349                 usb@22000 {
 350                         #address-cells = <1>;
 351                         #size-cells = <0>;
 352                         compatible = "fsl-usb2-dr";
 353                         reg = <0x22000 0x1000>;
 354                         interrupt-parent = <&mpic>;
 355                         interrupts = <28 0x2>;
 356                         phy_type = "ulpi";
 357                 };
 358
 359                 usb@23000 {
 360                         #address-cells = <1>;
 361                         #size-cells = <0>;
 362                         compatible = "fsl-usb2-dr";
 363                         reg = <0x23000 0x1000>;
 364                         interrupt-parent = <&mpic>;
 365                         interrupts = <46 0x2>;
 366                         phy_type = "ulpi";
 367                 };
 368
 369                 sdhci@2e000 {
 370                         compatible = "fsl,p1020-esdhc", "fsl,esdhc";
 371                         reg = <0x2e000 0x1000>;
 372                         interrupts = <72 0x2>;
 373                         interrupt-parent = <&mpic>;
 374                         /* Filled in by U-Boot */
 375                         clock-frequency = <0>;
 376                 };
 377
 378                 crypto@30000 {
 379                         compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
 380                                      "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
 381                         reg = <0x30000 0x10000>;
 382                         interrupts = <45 2 58 2>;
 383                         interrupt-parent = <&mpic>;
 384                         fsl,num-channels = <4>;
 385                         fsl,channel-fifo-len = <24>;
 386                         fsl,exec-units-mask = <0xbfe>;
 387                         fsl,descriptor-types-mask = <0x3ab0ebf>;
 388                 };
 389
 390                 mpic: pic@40000 {
 391                         interrupt-controller;
 392                         #address-cells = <0>;
 393                         #interrupt-cells = <2>;
 394                         reg = <0x40000 0x40000>;
 395                         compatible = "chrp,open-pic";
 396                         device_type = "open-pic";
 397                 };
 398
 399                 msi@41600 {
 400                         compatible = "fsl,p1020-msi", "fsl,mpic-msi";
 401                         reg = <0x41600 0x80>;
 402                         msi-available-ranges = <0 0x100>;
 403                         interrupts = <
 404                                 0xe0 0
 405                                 0xe1 0
 406                                 0xe2 0
 407                                 0xe3 0
 408                                 0xe4 0
 409                                 0xe5 0
 410                                 0xe6 0
 411                                 0xe7 0>;
 412                         interrupt-parent = <&mpic>;
 413                 };
 414
 415                 global-utilities@e0000 {        //global utilities block
 416                         compatible = "fsl,p1020-guts";
 417                         reg = <0xe0000 0x1000>;
 418                         fsl,has-rstcr;
 419                 };
 420         };
 421
 422         pci0: pcie@ffe09000 {
 423                 compatible = "fsl,mpc8548-pcie";
 424                 device_type = "pci";
 425                 #interrupt-cells = <1>;
 426                 #size-cells = <2>;
 427                 #address-cells = <3>;
 428                 reg = <0 0xffe09000 0 0x1000>;
 429                 bus-range = <0 255>;
 430                 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
 431                           0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
 432                 clock-frequency = <33333333>;
 433                 interrupt-parent = <&mpic>;
 434                 interrupts = <16 2>;
 435                 pcie@0 {
 436                         reg = <0x0 0x0 0x0 0x0 0x0>;
 437                         #size-cells = <2>;
 438                         #address-cells = <3>;
 439                         device_type = "pci";
 440                         ranges = <0x2000000 0x0 0xa0000000
 441                                   0x2000000 0x0 0xa0000000
 442                                   0x0 0x20000000
 443
 444                                   0x1000000 0x0 0x0
 445                                   0x1000000 0x0 0x0
 446                                   0x0 0x100000>;
 447                 };
 448         };
 449
 450         pci1: pcie@ffe0a000 {
 451                 compatible = "fsl,mpc8548-pcie";
 452                 device_type = "pci";
 453                 #interrupt-cells = <1>;
 454                 #size-cells = <2>;
 455                 #address-cells = <3>;
 456                 reg = <0 0xffe0a000 0 0x1000>;
 457                 bus-range = <0 255>;
 458                 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
 459                           0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
 460                 clock-frequency = <33333333>;
 461                 interrupt-parent = <&mpic>;
 462                 interrupts = <16 2>;
 463                 pcie@0 {
 464                         reg = <0x0 0x0 0x0 0x0 0x0>;
 465                         #size-cells = <2>;
 466                         #address-cells = <3>;
 467                         device_type = "pci";
 468                         ranges = <0x2000000 0x0 0xc0000000
 469                                   0x2000000 0x0 0xc0000000
 470                                   0x0 0x20000000
 471
 472                                   0x1000000 0x0 0x0
 473                                   0x1000000 0x0 0x0
 474                                   0x0 0x100000>;
 475                 };
 476         };
 477 };