arch/powerpc/boot/dts/mpc8572ds.dts

   1 /*
   2  * MPC8572 DS Device Tree Source
   3  *
   4  * Copyright 2007-2009 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13 / {
  14         model = "fsl,MPC8572DS";
  15         compatible = "fsl,MPC8572DS";
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 ethernet0 = &enet0;
  21                 ethernet1 = &enet1;
  22                 ethernet2 = &enet2;
  23                 ethernet3 = &enet3;
  24                 serial0 = &serial0;
  25                 serial1 = &serial1;
  26                 pci0 = &pci0;
  27                 pci1 = &pci1;
  28                 pci2 = &pci2;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 PowerPC,8572@0 {
  36                         device_type = "cpu";
  37                         reg = <0x0>;
  38                         d-cache-line-size = <32>;       // 32 bytes
  39                         i-cache-line-size = <32>;       // 32 bytes
  40                         d-cache-size = <0x8000>;                // L1, 32K
  41                         i-cache-size = <0x8000>;                // L1, 32K
  42                         timebase-frequency = <0>;
  43                         bus-frequency = <0>;
  44                         clock-frequency = <0>;
  45                         next-level-cache = <&L2>;
  46                 };
  47
  48                 PowerPC,8572@1 {
  49                         device_type = "cpu";
  50                         reg = <0x1>;
  51                         d-cache-line-size = <32>;       // 32 bytes
  52                         i-cache-line-size = <32>;       // 32 bytes
  53                         d-cache-size = <0x8000>;                // L1, 32K
  54                         i-cache-size = <0x8000>;                // L1, 32K
  55                         timebase-frequency = <0>;
  56                         bus-frequency = <0>;
  57                         clock-frequency = <0>;
  58                         next-level-cache = <&L2>;
  59                 };
  60         };
  61
  62         memory {
  63                 device_type = "memory";
  64         };
  65
  66         localbus@ffe05000 {
  67                 #address-cells = <2>;
  68                 #size-cells = <1>;
  69                 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
  70                 reg = <0 0xffe05000 0 0x1000>;
  71                 interrupts = <19 2>;
  72                 interrupt-parent = <&mpic>;
  73
  74                 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
  75                           0x1 0x0 0x0 0xe0000000 0x08000000
  76                           0x2 0x0 0x0 0xffa00000 0x00040000
  77                           0x3 0x0 0x0 0xffdf0000 0x00008000
  78                           0x4 0x0 0x0 0xffa40000 0x00040000
  79                           0x5 0x0 0x0 0xffa80000 0x00040000
  80                           0x6 0x0 0x0 0xffac0000 0x00040000>;
  81
  82                 nor@0,0 {
  83                         #address-cells = <1>;
  84                         #size-cells = <1>;
  85                         compatible = "cfi-flash";
  86                         reg = <0x0 0x0 0x8000000>;
  87                         bank-width = <2>;
  88                         device-width = <1>;
  89
  90                         ramdisk@0 {
  91                                 reg = <0x0 0x03000000>;
  92                                 read-only;
  93                         };
  94
  95                         diagnostic@3000000 {
  96                                 reg = <0x03000000 0x00e00000>;
  97                                 read-only;
  98                         };
  99
 100                         dink@3e00000 {
 101                                 reg = <0x03e00000 0x00200000>;
 102                                 read-only;
 103                         };
 104
 105                         kernel@4000000 {
 106                                 reg = <0x04000000 0x00400000>;
 107                                 read-only;
 108                         };
 109
 110                         jffs2@4400000 {
 111                                 reg = <0x04400000 0x03b00000>;
 112                         };
 113
 114                         dtb@7f00000 {
 115                                 reg = <0x07f00000 0x00080000>;
 116                                 read-only;
 117                         };
 118
 119                         u-boot@7f80000 {
 120                                 reg = <0x07f80000 0x00080000>;
 121                                 read-only;
 122                         };
 123                 };
 124
 125                 nand@2,0 {
 126                         #address-cells = <1>;
 127                         #size-cells = <1>;
 128                         compatible = "fsl,mpc8572-fcm-nand",
 129                                      "fsl,elbc-fcm-nand";
 130                         reg = <0x2 0x0 0x40000>;
 131
 132                         u-boot@0 {
 133                                 reg = <0x0 0x02000000>;
 134                                 read-only;
 135                         };
 136
 137                         jffs2@2000000 {
 138                                 reg = <0x02000000 0x10000000>;
 139                         };
 140
 141                         ramdisk@12000000 {
 142                                 reg = <0x12000000 0x08000000>;
 143                                 read-only;
 144                         };
 145
 146                         kernel@1a000000 {
 147                                 reg = <0x1a000000 0x04000000>;
 148                         };
 149
 150                         dtb@1e000000 {
 151                                 reg = <0x1e000000 0x01000000>;
 152                                 read-only;
 153                         };
 154
 155                         empty@1f000000 {
 156                                 reg = <0x1f000000 0x21000000>;
 157                         };
 158                 };
 159
 160                 nand@4,0 {
 161                         compatible = "fsl,mpc8572-fcm-nand",
 162                                      "fsl,elbc-fcm-nand";
 163                         reg = <0x4 0x0 0x40000>;
 164                 };
 165
 166                 nand@5,0 {
 167                         compatible = "fsl,mpc8572-fcm-nand",
 168                                      "fsl,elbc-fcm-nand";
 169                         reg = <0x5 0x0 0x40000>;
 170                 };
 171
 172                 nand@6,0 {
 173                         compatible = "fsl,mpc8572-fcm-nand",
 174                                      "fsl,elbc-fcm-nand";
 175                         reg = <0x6 0x0 0x40000>;
 176                 };
 177         };
 178
 179         soc8572@ffe00000 {
 180                 #address-cells = <1>;
 181                 #size-cells = <1>;
 182                 device_type = "soc";
 183                 compatible = "simple-bus";
 184                 ranges = <0x0 0 0xffe00000 0x100000>;
 185                 bus-frequency = <0>;            // Filled out by uboot.
 186
 187                 ecm-law@0 {
 188                         compatible = "fsl,ecm-law";
 189                         reg = <0x0 0x1000>;
 190                         fsl,num-laws = <12>;
 191                 };
 192
 193                 ecm@1000 {
 194                         compatible = "fsl,mpc8572-ecm", "fsl,ecm";
 195                         reg = <0x1000 0x1000>;
 196                         interrupts = <17 2>;
 197                         interrupt-parent = <&mpic>;
 198                 };
 199
 200                 memory-controller@2000 {
 201                         compatible = "fsl,mpc8572-memory-controller";
 202                         reg = <0x2000 0x1000>;
 203                         interrupt-parent = <&mpic>;
 204                         interrupts = <18 2>;
 205                 };
 206
 207                 memory-controller@6000 {
 208                         compatible = "fsl,mpc8572-memory-controller";
 209                         reg = <0x6000 0x1000>;
 210                         interrupt-parent = <&mpic>;
 211                         interrupts = <18 2>;
 212                 };
 213
 214                 L2: l2-cache-controller@20000 {
 215                         compatible = "fsl,mpc8572-l2-cache-controller";
 216                         reg = <0x20000 0x1000>;
 217                         cache-line-size = <32>; // 32 bytes
 218                         cache-size = <0x100000>; // L2, 1M
 219                         interrupt-parent = <&mpic>;
 220                         interrupts = <16 2>;
 221                 };
 222
 223                 i2c@3000 {
 224                         #address-cells = <1>;
 225                         #size-cells = <0>;
 226                         cell-index = <0>;
 227                         compatible = "fsl-i2c";
 228                         reg = <0x3000 0x100>;
 229                         interrupts = <43 2>;
 230                         interrupt-parent = <&mpic>;
 231                         dfsrr;
 232                 };
 233
 234                 i2c@3100 {
 235                         #address-cells = <1>;
 236                         #size-cells = <0>;
 237                         cell-index = <1>;
 238                         compatible = "fsl-i2c";
 239                         reg = <0x3100 0x100>;
 240                         interrupts = <43 2>;
 241                         interrupt-parent = <&mpic>;
 242                         dfsrr;
 243                 };
 244
 245                 dma@c300 {
 246                         #address-cells = <1>;
 247                         #size-cells = <1>;
 248                         compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
 249                         reg = <0xc300 0x4>;
 250                         ranges = <0x0 0xc100 0x200>;
 251                         cell-index = <1>;
 252                         dma-channel@0 {
 253                                 compatible = "fsl,mpc8572-dma-channel",
 254                                                 "fsl,eloplus-dma-channel";
 255                                 reg = <0x0 0x80>;
 256                                 cell-index = <0>;
 257                                 interrupt-parent = <&mpic>;
 258                                 interrupts = <76 2>;
 259                         };
 260                         dma-channel@80 {
 261                                 compatible = "fsl,mpc8572-dma-channel",
 262                                                 "fsl,eloplus-dma-channel";
 263                                 reg = <0x80 0x80>;
 264                                 cell-index = <1>;
 265                                 interrupt-parent = <&mpic>;
 266                                 interrupts = <77 2>;
 267                         };
 268                         dma-channel@100 {
 269                                 compatible = "fsl,mpc8572-dma-channel",
 270                                                 "fsl,eloplus-dma-channel";
 271                                 reg = <0x100 0x80>;
 272                                 cell-index = <2>;
 273                                 interrupt-parent = <&mpic>;
 274                                 interrupts = <78 2>;
 275                         };
 276                         dma-channel@180 {
 277                                 compatible = "fsl,mpc8572-dma-channel",
 278                                                 "fsl,eloplus-dma-channel";
 279                                 reg = <0x180 0x80>;
 280                                 cell-index = <3>;
 281                                 interrupt-parent = <&mpic>;
 282                                 interrupts = <79 2>;
 283                         };
 284                 };
 285
 286                 dma@21300 {
 287                         #address-cells = <1>;
 288                         #size-cells = <1>;
 289                         compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
 290                         reg = <0x21300 0x4>;
 291                         ranges = <0x0 0x21100 0x200>;
 292                         cell-index = <0>;
 293                         dma-channel@0 {
 294                                 compatible = "fsl,mpc8572-dma-channel",
 295                                                 "fsl,eloplus-dma-channel";
 296                                 reg = <0x0 0x80>;
 297                                 cell-index = <0>;
 298                                 interrupt-parent = <&mpic>;
 299                                 interrupts = <20 2>;
 300                         };
 301                         dma-channel@80 {
 302                                 compatible = "fsl,mpc8572-dma-channel",
 303                                                 "fsl,eloplus-dma-channel";
 304                                 reg = <0x80 0x80>;
 305                                 cell-index = <1>;
 306                                 interrupt-parent = <&mpic>;
 307                                 interrupts = <21 2>;
 308                         };
 309                         dma-channel@100 {
 310                                 compatible = "fsl,mpc8572-dma-channel",
 311                                                 "fsl,eloplus-dma-channel";
 312                                 reg = <0x100 0x80>;
 313                                 cell-index = <2>;
 314                                 interrupt-parent = <&mpic>;
 315                                 interrupts = <22 2>;
 316                         };
 317                         dma-channel@180 {
 318                                 compatible = "fsl,mpc8572-dma-channel",
 319                                                 "fsl,eloplus-dma-channel";
 320                                 reg = <0x180 0x80>;
 321                                 cell-index = <3>;
 322                                 interrupt-parent = <&mpic>;
 323                                 interrupts = <23 2>;
 324                         };
 325                 };
 326
 327                 ptp_clock@24E00 {
 328                         compatible = "fsl,etsec-ptp";
 329                         reg = <0x24E00 0xB0>;
 330                         interrupts = <68 2 69 2 70 2 71 2>;
 331                         interrupt-parent = < &mpic >;
 332                         fsl,tclk-period = <5>;
 333                         fsl,tmr-prsc = <200>;
 334                         fsl,tmr-add = <0xAAAAAAAB>;
 335                         fsl,tmr-fiper1 = <0x3B9AC9FB>;
 336                         fsl,tmr-fiper2 = <0x3B9AC9FB>;
 337                         fsl,max-adj = <499999999>;
 338                 };
 339
 340                 enet0: ethernet@24000 {
 341                         #address-cells = <1>;
 342                         #size-cells = <1>;
 343                         cell-index = <0>;
 344                         device_type = "network";
 345                         model = "eTSEC";
 346                         compatible = "gianfar";
 347                         reg = <0x24000 0x1000>;
 348                         ranges = <0x0 0x24000 0x1000>;
 349                         local-mac-address = [ 00 00 00 00 00 00 ];
 350                         interrupts = <29 2 30 2 34 2>;
 351                         interrupt-parent = <&mpic>;
 352                         tbi-handle = <&tbi0>;
 353                         phy-handle = <&phy0>;
 354                         phy-connection-type = "rgmii-id";
 355
 356                         mdio@520 {
 357                                 #address-cells = <1>;
 358                                 #size-cells = <0>;
 359                                 compatible = "fsl,gianfar-mdio";
 360                                 reg = <0x520 0x20>;
 361
 362                                 phy0: ethernet-phy@0 {
 363                                         interrupt-parent = <&mpic>;
 364                                         interrupts = <10 1>;
 365                                         reg = <0x0>;
 366                                 };
 367                                 phy1: ethernet-phy@1 {
 368                                         interrupt-parent = <&mpic>;
 369                                         interrupts = <10 1>;
 370                                         reg = <0x1>;
 371                                 };
 372                                 phy2: ethernet-phy@2 {
 373                                         interrupt-parent = <&mpic>;
 374                                         interrupts = <10 1>;
 375                                         reg = <0x2>;
 376                                 };
 377                                 phy3: ethernet-phy@3 {
 378                                         interrupt-parent = <&mpic>;
 379                                         interrupts = <10 1>;
 380                                         reg = <0x3>;
 381                                 };
 382
 383                                 tbi0: tbi-phy@11 {
 384                                         reg = <0x11>;
 385                                         device_type = "tbi-phy";
 386                                 };
 387                         };
 388                 };
 389
 390                 enet1: ethernet@25000 {
 391                         #address-cells = <1>;
 392                         #size-cells = <1>;
 393                         cell-index = <1>;
 394                         device_type = "network";
 395                         model = "eTSEC";
 396                         compatible = "gianfar";
 397                         reg = <0x25000 0x1000>;
 398                         ranges = <0x0 0x25000 0x1000>;
 399                         local-mac-address = [ 00 00 00 00 00 00 ];
 400                         interrupts = <35 2 36 2 40 2>;
 401                         interrupt-parent = <&mpic>;
 402                         tbi-handle = <&tbi1>;
 403                         phy-handle = <&phy1>;
 404                         phy-connection-type = "rgmii-id";
 405
 406                         mdio@520 {
 407                                 #address-cells = <1>;
 408                                 #size-cells = <0>;
 409                                 compatible = "fsl,gianfar-tbi";
 410                                 reg = <0x520 0x20>;
 411
 412                                 tbi1: tbi-phy@11 {
 413                                         reg = <0x11>;
 414                                         device_type = "tbi-phy";
 415                                 };
 416                         };
 417                 };
 418
 419                 enet2: ethernet@26000 {
 420                         #address-cells = <1>;
 421                         #size-cells = <1>;
 422                         cell-index = <2>;
 423                         device_type = "network";
 424                         model = "eTSEC";
 425                         compatible = "gianfar";
 426                         reg = <0x26000 0x1000>;
 427                         ranges = <0x0 0x26000 0x1000>;
 428                         local-mac-address = [ 00 00 00 00 00 00 ];
 429                         interrupts = <31 2 32 2 33 2>;
 430                         interrupt-parent = <&mpic>;
 431                         tbi-handle = <&tbi2>;
 432                         phy-handle = <&phy2>;
 433                         phy-connection-type = "rgmii-id";
 434
 435                         mdio@520 {
 436                                 #address-cells = <1>;
 437                                 #size-cells = <0>;
 438                                 compatible = "fsl,gianfar-tbi";
 439                                 reg = <0x520 0x20>;
 440
 441                                 tbi2: tbi-phy@11 {
 442                                         reg = <0x11>;
 443                                         device_type = "tbi-phy";
 444                                 };
 445                         };
 446                 };
 447
 448                 enet3: ethernet@27000 {
 449                         #address-cells = <1>;
 450                         #size-cells = <1>;
 451                         cell-index = <3>;
 452                         device_type = "network";
 453                         model = "eTSEC";
 454                         compatible = "gianfar";
 455                         reg = <0x27000 0x1000>;
 456                         ranges = <0x0 0x27000 0x1000>;
 457                         local-mac-address = [ 00 00 00 00 00 00 ];
 458                         interrupts = <37 2 38 2 39 2>;
 459                         interrupt-parent = <&mpic>;
 460                         tbi-handle = <&tbi3>;
 461                         phy-handle = <&phy3>;
 462                         phy-connection-type = "rgmii-id";
 463
 464                         mdio@520 {
 465                                 #address-cells = <1>;
 466                                 #size-cells = <0>;
 467                                 compatible = "fsl,gianfar-tbi";
 468                                 reg = <0x520 0x20>;
 469
 470                                 tbi3: tbi-phy@11 {
 471                                         reg = <0x11>;
 472                                         device_type = "tbi-phy";
 473                                 };
 474                         };
 475                 };
 476
 477                 serial0: serial@4500 {
 478                         cell-index = <0>;
 479                         device_type = "serial";
 480                         compatible = "ns16550";
 481                         reg = <0x4500 0x100>;
 482                         clock-frequency = <0>;
 483                         interrupts = <42 2>;
 484                         interrupt-parent = <&mpic>;
 485                 };
 486
 487                 serial1: serial@4600 {
 488                         cell-index = <1>;
 489                         device_type = "serial";
 490                         compatible = "ns16550";
 491                         reg = <0x4600 0x100>;
 492                         clock-frequency = <0>;
 493                         interrupts = <42 2>;
 494                         interrupt-parent = <&mpic>;
 495                 };
 496
 497                 global-utilities@e0000 {        //global utilities block
 498                         compatible = "fsl,mpc8572-guts";
 499                         reg = <0xe0000 0x1000>;
 500                         fsl,has-rstcr;
 501                 };
 502
 503                 msi@41600 {
 504                         compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
 505                         reg = <0x41600 0x80>;
 506                         msi-available-ranges = <0 0x100>;
 507                         interrupts = <
 508                                 0xe0 0
 509                                 0xe1 0
 510                                 0xe2 0
 511                                 0xe3 0
 512                                 0xe4 0
 513                                 0xe5 0
 514                                 0xe6 0
 515                                 0xe7 0>;
 516                         interrupt-parent = <&mpic>;
 517                 };
 518
 519                 crypto@30000 {
 520                         compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
 521                                      "fsl,sec2.1", "fsl,sec2.0";
 522                         reg = <0x30000 0x10000>;
 523                         interrupts = <45 2 58 2>;
 524                         interrupt-parent = <&mpic>;
 525                         fsl,num-channels = <4>;
 526                         fsl,channel-fifo-len = <24>;
 527                         fsl,exec-units-mask = <0x9fe>;
 528                         fsl,descriptor-types-mask = <0x3ab0ebf>;
 529                 };
 530
 531                 mpic: pic@40000 {
 532                         interrupt-controller;
 533                         #address-cells = <0>;
 534                         #interrupt-cells = <2>;
 535                         reg = <0x40000 0x40000>;
 536                         compatible = "chrp,open-pic";
 537                         device_type = "open-pic";
 538                 };
 539         };
 540
 541         pci0: pcie@ffe08000 {
 542                 compatible = "fsl,mpc8548-pcie";
 543                 device_type = "pci";
 544                 #interrupt-cells = <1>;
 545                 #size-cells = <2>;
 546                 #address-cells = <3>;
 547                 reg = <0 0xffe08000 0 0x1000>;
 548                 bus-range = <0 255>;
 549                 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
 550                           0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>;
 551                 clock-frequency = <33333333>;
 552                 interrupt-parent = <&mpic>;
 553                 interrupts = <24 2>;
 554                 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
 555                 interrupt-map = <
 556                         /* IDSEL 0x11 func 0 - PCI slot 1 */
 557                         0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
 558                         0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
 559                         0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
 560                         0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
 561
 562                         /* IDSEL 0x11 func 1 - PCI slot 1 */
 563                         0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
 564                         0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
 565                         0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
 566                         0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
 567
 568                         /* IDSEL 0x11 func 2 - PCI slot 1 */
 569                         0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
 570                         0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
 571                         0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
 572                         0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
 573
 574                         /* IDSEL 0x11 func 3 - PCI slot 1 */
 575                         0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
 576                         0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
 577                         0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
 578                         0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
 579
 580                         /* IDSEL 0x11 func 4 - PCI slot 1 */
 581                         0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
 582                         0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
 583                         0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
 584                         0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
 585
 586                         /* IDSEL 0x11 func 5 - PCI slot 1 */
 587                         0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
 588                         0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
 589                         0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
 590                         0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
 591
 592                         /* IDSEL 0x11 func 6 - PCI slot 1 */
 593                         0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
 594                         0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
 595                         0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
 596                         0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
 597
 598                         /* IDSEL 0x11 func 7 - PCI slot 1 */
 599                         0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
 600                         0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
 601                         0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
 602                         0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
 603
 604                         /* IDSEL 0x12 func 0 - PCI slot 2 */
 605                         0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
 606                         0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
 607                         0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
 608                         0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
 609
 610                         /* IDSEL 0x12 func 1 - PCI slot 2 */
 611                         0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
 612                         0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
 613                         0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
 614                         0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
 615
 616                         /* IDSEL 0x12 func 2 - PCI slot 2 */
 617                         0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
 618                         0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
 619                         0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
 620                         0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
 621
 622                         /* IDSEL 0x12 func 3 - PCI slot 2 */
 623                         0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
 624                         0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
 625                         0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
 626                         0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
 627
 628                         /* IDSEL 0x12 func 4 - PCI slot 2 */
 629                         0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
 630                         0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
 631                         0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
 632                         0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
 633
 634                         /* IDSEL 0x12 func 5 - PCI slot 2 */
 635                         0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
 636                         0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
 637                         0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
 638                         0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
 639
 640                         /* IDSEL 0x12 func 6 - PCI slot 2 */
 641                         0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
 642                         0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
 643                         0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
 644                         0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
 645
 646                         /* IDSEL 0x12 func 7 - PCI slot 2 */
 647                         0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
 648                         0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
 649                         0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
 650                         0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
 651
 652                         // IDSEL 0x1c  USB
 653                         0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
 654                         0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
 655                         0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
 656                         0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
 657
 658                         // IDSEL 0x1d  Audio
 659                         0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
 660
 661                         // IDSEL 0x1e Legacy
 662                         0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
 663                         0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
 664
 665                         // IDSEL 0x1f IDE/SATA
 666                         0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
 667                         0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
 668
 669                         >;
 670
 671                 pcie@0 {
 672                         reg = <0x0 0x0 0x0 0x0 0x0>;
 673                         #size-cells = <2>;
 674                         #address-cells = <3>;
 675                         device_type = "pci";
 676                         ranges = <0x2000000 0x0 0x80000000
 677                                   0x2000000 0x0 0x80000000
 678                                   0x0 0x20000000
 679
 680                                   0x1000000 0x0 0x0
 681                                   0x1000000 0x0 0x0
 682                                   0x0 0x10000>;
 683                         uli1575@0 {
 684                                 reg = <0x0 0x0 0x0 0x0 0x0>;
 685                                 #size-cells = <2>;
 686                                 #address-cells = <3>;
 687                                 ranges = <0x2000000 0x0 0x80000000
 688                                           0x2000000 0x0 0x80000000
 689                                           0x0 0x20000000
 690
 691                                           0x1000000 0x0 0x0
 692                                           0x1000000 0x0 0x0
 693                                           0x0 0x10000>;
 694                                 isa@1e {
 695                                         device_type = "isa";
 696                                         #interrupt-cells = <2>;
 697                                         #size-cells = <1>;
 698                                         #address-cells = <2>;
 699                                         reg = <0xf000 0x0 0x0 0x0 0x0>;
 700                                         ranges = <0x1 0x0 0x1000000 0x0 0x0
 701                                                   0x1000>;
 702                                         interrupt-parent = <&i8259>;
 703
 704                                         i8259: interrupt-controller@20 {
 705                                                 reg = <0x1 0x20 0x2
 706                                                        0x1 0xa0 0x2
 707                                                        0x1 0x4d0 0x2>;
 708                                                 interrupt-controller;
 709                                                 device_type = "interrupt-controller";
 710                                                 #address-cells = <0>;
 711                                                 #interrupt-cells = <2>;
 712                                                 compatible = "chrp,iic";
 713                                                 interrupts = <9 2>;
 714                                                 interrupt-parent = <&mpic>;
 715                                         };
 716
 717                                         i8042@60 {
 718                                                 #size-cells = <0>;
 719                                                 #address-cells = <1>;
 720                                                 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
 721                                                 interrupts = <1 3 12 3>;
 722                                                 interrupt-parent =
 723                                                         <&i8259>;
 724
 725                                                 keyboard@0 {
 726                                                         reg = <0x0>;
 727                                                         compatible = "pnpPNP,303";
 728                                                 };
 729
 730                                                 mouse@1 {
 731                                                         reg = <0x1>;
 732                                                         compatible = "pnpPNP,f03";
 733                                                 };
 734                                         };
 735
 736                                         rtc@70 {
 737                                                 compatible = "pnpPNP,b00";
 738                                                 reg = <0x1 0x70 0x2>;
 739                                         };
 740
 741                                         gpio@400 {
 742                                                 reg = <0x1 0x400 0x80>;
 743                                         };
 744                                 };
 745                         };
 746                 };
 747
 748         };
 749
 750         pci1: pcie@ffe09000 {
 751                 compatible = "fsl,mpc8548-pcie";
 752                 device_type = "pci";
 753                 #interrupt-cells = <1>;
 754                 #size-cells = <2>;
 755                 #address-cells = <3>;
 756                 reg = <0 0xffe09000 0 0x1000>;
 757                 bus-range = <0 255>;
 758                 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
 759                           0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>;
 760                 clock-frequency = <33333333>;
 761                 interrupt-parent = <&mpic>;
 762                 interrupts = <25 2>;
 763                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 764                 interrupt-map = <
 765                         /* IDSEL 0x0 */
 766                         0000 0x0 0x0 0x1 &mpic 0x4 0x1
 767                         0000 0x0 0x0 0x2 &mpic 0x5 0x1
 768                         0000 0x0 0x0 0x3 &mpic 0x6 0x1
 769                         0000 0x0 0x0 0x4 &mpic 0x7 0x1
 770                         >;
 771                 pcie@0 {
 772                         reg = <0x0 0x0 0x0 0x0 0x0>;
 773                         #size-cells = <2>;
 774                         #address-cells = <3>;
 775                         device_type = "pci";
 776                         ranges = <0x2000000 0x0 0xa0000000
 777                                   0x2000000 0x0 0xa0000000
 778                                   0x0 0x20000000
 779
 780                                   0x1000000 0x0 0x0
 781                                   0x1000000 0x0 0x0
 782                                   0x0 0x10000>;
 783                 };
 784         };
 785
 786         pci2: pcie@ffe0a000 {
 787                 compatible = "fsl,mpc8548-pcie";
 788                 device_type = "pci";
 789                 #interrupt-cells = <1>;
 790                 #size-cells = <2>;
 791                 #address-cells = <3>;
 792                 reg = <0 0xffe0a000 0 0x1000>;
 793                 bus-range = <0 255>;
 794                 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
 795                           0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>;
 796                 clock-frequency = <33333333>;
 797                 interrupt-parent = <&mpic>;
 798                 interrupts = <26 2>;
 799                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 800                 interrupt-map = <
 801                         /* IDSEL 0x0 */
 802                         0000 0x0 0x0 0x1 &mpic 0x0 0x1
 803                         0000 0x0 0x0 0x2 &mpic 0x1 0x1
 804                         0000 0x0 0x0 0x3 &mpic 0x2 0x1
 805                         0000 0x0 0x0 0x4 &mpic 0x3 0x1
 806                         >;
 807                 pcie@0 {
 808                         reg = <0x0 0x0 0x0 0x0 0x0>;
 809                         #size-cells = <2>;
 810                         #address-cells = <3>;
 811                         device_type = "pci";
 812                         ranges = <0x2000000 0x0 0xc0000000
 813                                   0x2000000 0x0 0xc0000000
 814                                   0x0 0x20000000
 815
 816                                   0x1000000 0x0 0x0
 817                                   0x1000000 0x0 0x0
 818                                   0x0 0x10000>;
 819                 };
 820         };
 821 };