arch/powerpc/boot/dts/mpc8572ds.dts

   1 /*
   2  * MPC8572 DS Device Tree Source
   3  *
   4  * Copyright 2007, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13 / {
  14         model = "fsl,MPC8572DS";
  15         compatible = "fsl,MPC8572DS";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         aliases {
  20                 ethernet0 = &enet0;
  21                 ethernet1 = &enet1;
  22                 ethernet2 = &enet2;
  23                 ethernet3 = &enet3;
  24                 serial0 = &serial0;
  25                 serial1 = &serial1;
  26                 pci0 = &pci0;
  27                 pci1 = &pci1;
  28                 pci2 = &pci2;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 PowerPC,8572@0 {
  36                         device_type = "cpu";
  37                         reg = <0x0>;
  38                         d-cache-line-size = <32>;       // 32 bytes
  39                         i-cache-line-size = <32>;       // 32 bytes
  40                         d-cache-size = <0x8000>;                // L1, 32K
  41                         i-cache-size = <0x8000>;                // L1, 32K
  42                         timebase-frequency = <0>;
  43                         bus-frequency = <0>;
  44                         clock-frequency = <0>;
  45                         next-level-cache = <&L2>;
  46                 };
  47
  48                 PowerPC,8572@1 {
  49                         device_type = "cpu";
  50                         reg = <0x1>;
  51                         d-cache-line-size = <32>;       // 32 bytes
  52                         i-cache-line-size = <32>;       // 32 bytes
  53                         d-cache-size = <0x8000>;                // L1, 32K
  54                         i-cache-size = <0x8000>;                // L1, 32K
  55                         timebase-frequency = <0>;
  56                         bus-frequency = <0>;
  57                         clock-frequency = <0>;
  58                         next-level-cache = <&L2>;
  59                 };
  60         };
  61
  62         memory {
  63                 device_type = "memory";
  64                 reg = <0x0 0x0>;        // Filled by U-Boot
  65         };
  66
  67         soc8572@ffe00000 {
  68                 #address-cells = <1>;
  69                 #size-cells = <1>;
  70                 device_type = "soc";
  71                 compatible = "simple-bus";
  72                 ranges = <0x0 0xffe00000 0x100000>;
  73                 reg = <0xffe00000 0x1000>;      // CCSRBAR & soc regs, remove once parse code for immrbase fixed
  74                 bus-frequency = <0>;            // Filled out by uboot.
  75
  76                 memory-controller@2000 {
  77                         compatible = "fsl,mpc8572-memory-controller";
  78                         reg = <0x2000 0x1000>;
  79                         interrupt-parent = <&mpic>;
  80                         interrupts = <18 2>;
  81                 };
  82
  83                 memory-controller@6000 {
  84                         compatible = "fsl,mpc8572-memory-controller";
  85                         reg = <0x6000 0x1000>;
  86                         interrupt-parent = <&mpic>;
  87                         interrupts = <18 2>;
  88                 };
  89
  90                 L2: l2-cache-controller@20000 {
  91                         compatible = "fsl,mpc8572-l2-cache-controller";
  92                         reg = <0x20000 0x1000>;
  93                         cache-line-size = <32>; // 32 bytes
  94                         cache-size = <0x80000>; // L2, 512K
  95                         interrupt-parent = <&mpic>;
  96                         interrupts = <16 2>;
  97                 };
  98
  99                 i2c@3000 {
 100                         #address-cells = <1>;
 101                         #size-cells = <0>;
 102                         cell-index = <0>;
 103                         compatible = "fsl-i2c";
 104                         reg = <0x3000 0x100>;
 105                         interrupts = <43 2>;
 106                         interrupt-parent = <&mpic>;
 107                         dfsrr;
 108                 };
 109
 110                 i2c@3100 {
 111                         #address-cells = <1>;
 112                         #size-cells = <0>;
 113                         cell-index = <1>;
 114                         compatible = "fsl-i2c";
 115                         reg = <0x3100 0x100>;
 116                         interrupts = <43 2>;
 117                         interrupt-parent = <&mpic>;
 118                         dfsrr;
 119                 };
 120
 121                 dma@c300 {
 122                         #address-cells = <1>;
 123                         #size-cells = <1>;
 124                         compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
 125                         reg = <0xc300 0x4>;
 126                         ranges = <0x0 0xc100 0x200>;
 127                         cell-index = <1>;
 128                         dma-channel@0 {
 129                                 compatible = "fsl,mpc8572-dma-channel",
 130                                                 "fsl,eloplus-dma-channel";
 131                                 reg = <0x0 0x80>;
 132                                 cell-index = <0>;
 133                                 interrupt-parent = <&mpic>;
 134                                 interrupts = <76 2>;
 135                         };
 136                         dma-channel@80 {
 137                                 compatible = "fsl,mpc8572-dma-channel",
 138                                                 "fsl,eloplus-dma-channel";
 139                                 reg = <0x80 0x80>;
 140                                 cell-index = <1>;
 141                                 interrupt-parent = <&mpic>;
 142                                 interrupts = <77 2>;
 143                         };
 144                         dma-channel@100 {
 145                                 compatible = "fsl,mpc8572-dma-channel",
 146                                                 "fsl,eloplus-dma-channel";
 147                                 reg = <0x100 0x80>;
 148                                 cell-index = <2>;
 149                                 interrupt-parent = <&mpic>;
 150                                 interrupts = <78 2>;
 151                         };
 152                         dma-channel@180 {
 153                                 compatible = "fsl,mpc8572-dma-channel",
 154                                                 "fsl,eloplus-dma-channel";
 155                                 reg = <0x180 0x80>;
 156                                 cell-index = <3>;
 157                                 interrupt-parent = <&mpic>;
 158                                 interrupts = <79 2>;
 159                         };
 160                 };
 161
 162                 dma@21300 {
 163                         #address-cells = <1>;
 164                         #size-cells = <1>;
 165                         compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
 166                         reg = <0x21300 0x4>;
 167                         ranges = <0x0 0x21100 0x200>;
 168                         cell-index = <0>;
 169                         dma-channel@0 {
 170                                 compatible = "fsl,mpc8572-dma-channel",
 171                                                 "fsl,eloplus-dma-channel";
 172                                 reg = <0x0 0x80>;
 173                                 cell-index = <0>;
 174                                 interrupt-parent = <&mpic>;
 175                                 interrupts = <20 2>;
 176                         };
 177                         dma-channel@80 {
 178                                 compatible = "fsl,mpc8572-dma-channel",
 179                                                 "fsl,eloplus-dma-channel";
 180                                 reg = <0x80 0x80>;
 181                                 cell-index = <1>;
 182                                 interrupt-parent = <&mpic>;
 183                                 interrupts = <21 2>;
 184                         };
 185                         dma-channel@100 {
 186                                 compatible = "fsl,mpc8572-dma-channel",
 187                                                 "fsl,eloplus-dma-channel";
 188                                 reg = <0x100 0x80>;
 189                                 cell-index = <2>;
 190                                 interrupt-parent = <&mpic>;
 191                                 interrupts = <22 2>;
 192                         };
 193                         dma-channel@180 {
 194                                 compatible = "fsl,mpc8572-dma-channel",
 195                                                 "fsl,eloplus-dma-channel";
 196                                 reg = <0x180 0x80>;
 197                                 cell-index = <3>;
 198                                 interrupt-parent = <&mpic>;
 199                                 interrupts = <23 2>;
 200                         };
 201                 };
 202
 203                 mdio@24520 {
 204                         #address-cells = <1>;
 205                         #size-cells = <0>;
 206                         compatible = "fsl,gianfar-mdio";
 207                         reg = <0x24520 0x20>;
 208
 209                         phy0: ethernet-phy@0 {
 210                                 interrupt-parent = <&mpic>;
 211                                 interrupts = <10 1>;
 212                                 reg = <0x0>;
 213                         };
 214                         phy1: ethernet-phy@1 {
 215                                 interrupt-parent = <&mpic>;
 216                                 interrupts = <10 1>;
 217                                 reg = <0x1>;
 218                         };
 219                         phy2: ethernet-phy@2 {
 220                                 interrupt-parent = <&mpic>;
 221                                 interrupts = <10 1>;
 222                                 reg = <0x2>;
 223                         };
 224                         phy3: ethernet-phy@3 {
 225                                 interrupt-parent = <&mpic>;
 226                                 interrupts = <10 1>;
 227                                 reg = <0x3>;
 228                         };
 229                 };
 230
 231                 enet0: ethernet@24000 {
 232                         cell-index = <0>;
 233                         device_type = "network";
 234                         model = "eTSEC";
 235                         compatible = "gianfar";
 236                         reg = <0x24000 0x1000>;
 237                         local-mac-address = [ 00 00 00 00 00 00 ];
 238                         interrupts = <29 2 30 2 34 2>;
 239                         interrupt-parent = <&mpic>;
 240                         phy-handle = <&phy0>;
 241                         phy-connection-type = "rgmii-id";
 242                 };
 243
 244                 enet1: ethernet@25000 {
 245                         cell-index = <1>;
 246                         device_type = "network";
 247                         model = "eTSEC";
 248                         compatible = "gianfar";
 249                         reg = <0x25000 0x1000>;
 250                         local-mac-address = [ 00 00 00 00 00 00 ];
 251                         interrupts = <35 2 36 2 40 2>;
 252                         interrupt-parent = <&mpic>;
 253                         phy-handle = <&phy1>;
 254                         phy-connection-type = "rgmii-id";
 255                 };
 256
 257                 enet2: ethernet@26000 {
 258                         cell-index = <2>;
 259                         device_type = "network";
 260                         model = "eTSEC";
 261                         compatible = "gianfar";
 262                         reg = <0x26000 0x1000>;
 263                         local-mac-address = [ 00 00 00 00 00 00 ];
 264                         interrupts = <31 2 32 2 33 2>;
 265                         interrupt-parent = <&mpic>;
 266                         phy-handle = <&phy2>;
 267                         phy-connection-type = "rgmii-id";
 268                 };
 269
 270                 enet3: ethernet@27000 {
 271                         cell-index = <3>;
 272                         device_type = "network";
 273                         model = "eTSEC";
 274                         compatible = "gianfar";
 275                         reg = <0x27000 0x1000>;
 276                         local-mac-address = [ 00 00 00 00 00 00 ];
 277                         interrupts = <37 2 38 2 39 2>;
 278                         interrupt-parent = <&mpic>;
 279                         phy-handle = <&phy3>;
 280                         phy-connection-type = "rgmii-id";
 281                 };
 282
 283                 serial0: serial@4500 {
 284                         cell-index = <0>;
 285                         device_type = "serial";
 286                         compatible = "ns16550";
 287                         reg = <0x4500 0x100>;
 288                         clock-frequency = <0>;
 289                         interrupts = <42 2>;
 290                         interrupt-parent = <&mpic>;
 291                 };
 292
 293                 serial1: serial@4600 {
 294                         cell-index = <1>;
 295                         device_type = "serial";
 296                         compatible = "ns16550";
 297                         reg = <0x4600 0x100>;
 298                         clock-frequency = <0>;
 299                         interrupts = <42 2>;
 300                         interrupt-parent = <&mpic>;
 301                 };
 302
 303                 global-utilities@e0000 {        //global utilities block
 304                         compatible = "fsl,mpc8572-guts";
 305                         reg = <0xe0000 0x1000>;
 306                         fsl,has-rstcr;
 307                 };
 308
 309                 msi@41600 {
 310                         compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
 311                         reg = <0x41600 0x80>;
 312                         msi-available-ranges = <0 0x100>;
 313                         interrupts = <
 314                                 0xe0 0
 315                                 0xe1 0
 316                                 0xe2 0
 317                                 0xe3 0
 318                                 0xe4 0
 319                                 0xe5 0
 320                                 0xe6 0
 321                                 0xe7 0>;
 322                         interrupt-parent = <&mpic>;
 323                 };
 324
 325                 crypto@30000 {
 326                         compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
 327                                      "fsl,sec2.1", "fsl,sec2.0";
 328                         reg = <0x30000 0x10000>;
 329                         interrupts = <45 2 58 2>;
 330                         interrupt-parent = <&mpic>;
 331                         fsl,num-channels = <4>;
 332                         fsl,channel-fifo-len = <24>;
 333                         fsl,exec-units-mask = <0x9fe>;
 334                         fsl,descriptor-types-mask = <0x3ab0ebf>;
 335                 };
 336
 337                 mpic: pic@40000 {
 338                         interrupt-controller;
 339                         #address-cells = <0>;
 340                         #interrupt-cells = <2>;
 341                         reg = <0x40000 0x40000>;
 342                         compatible = "chrp,open-pic";
 343                         device_type = "open-pic";
 344                 };
 345         };
 346
 347         pci0: pcie@ffe08000 {
 348                 cell-index = <0>;
 349                 compatible = "fsl,mpc8548-pcie";
 350                 device_type = "pci";
 351                 #interrupt-cells = <1>;
 352                 #size-cells = <2>;
 353                 #address-cells = <3>;
 354                 reg = <0xffe08000 0x1000>;
 355                 bus-range = <0 255>;
 356                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 357                           0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
 358                 clock-frequency = <33333333>;
 359                 interrupt-parent = <&mpic>;
 360                 interrupts = <24 2>;
 361                 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
 362                 interrupt-map = <
 363                         /* IDSEL 0x11 func 0 - PCI slot 1 */
 364                         0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
 365                         0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
 366                         0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
 367                         0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
 368
 369                         /* IDSEL 0x11 func 1 - PCI slot 1 */
 370                         0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
 371                         0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
 372                         0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
 373                         0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
 374
 375                         /* IDSEL 0x11 func 2 - PCI slot 1 */
 376                         0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
 377                         0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
 378                         0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
 379                         0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
 380
 381                         /* IDSEL 0x11 func 3 - PCI slot 1 */
 382                         0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
 383                         0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
 384                         0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
 385                         0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
 386
 387                         /* IDSEL 0x11 func 4 - PCI slot 1 */
 388                         0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
 389                         0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
 390                         0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
 391                         0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
 392
 393                         /* IDSEL 0x11 func 5 - PCI slot 1 */
 394                         0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
 395                         0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
 396                         0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
 397                         0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
 398
 399                         /* IDSEL 0x11 func 6 - PCI slot 1 */
 400                         0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
 401                         0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
 402                         0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
 403                         0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
 404
 405                         /* IDSEL 0x11 func 7 - PCI slot 1 */
 406                         0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
 407                         0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
 408                         0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
 409                         0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
 410
 411                         /* IDSEL 0x12 func 0 - PCI slot 2 */
 412                         0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
 413                         0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
 414                         0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
 415                         0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
 416
 417                         /* IDSEL 0x12 func 1 - PCI slot 2 */
 418                         0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
 419                         0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
 420                         0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
 421                         0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
 422
 423                         /* IDSEL 0x12 func 2 - PCI slot 2 */
 424                         0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
 425                         0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
 426                         0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
 427                         0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
 428
 429                         /* IDSEL 0x12 func 3 - PCI slot 2 */
 430                         0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
 431                         0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
 432                         0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
 433                         0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
 434
 435                         /* IDSEL 0x12 func 4 - PCI slot 2 */
 436                         0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
 437                         0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
 438                         0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
 439                         0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
 440
 441                         /* IDSEL 0x12 func 5 - PCI slot 2 */
 442                         0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
 443                         0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
 444                         0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
 445                         0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
 446
 447                         /* IDSEL 0x12 func 6 - PCI slot 2 */
 448                         0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
 449                         0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
 450                         0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
 451                         0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
 452
 453                         /* IDSEL 0x12 func 7 - PCI slot 2 */
 454                         0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
 455                         0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
 456                         0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
 457                         0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
 458
 459                         // IDSEL 0x1c  USB
 460                         0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
 461                         0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
 462                         0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
 463                         0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
 464
 465                         // IDSEL 0x1d  Audio
 466                         0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
 467
 468                         // IDSEL 0x1e Legacy
 469                         0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
 470                         0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
 471
 472                         // IDSEL 0x1f IDE/SATA
 473                         0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
 474                         0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
 475
 476                         >;
 477
 478                 pcie@0 {
 479                         reg = <0x0 0x0 0x0 0x0 0x0>;
 480                         #size-cells = <2>;
 481                         #address-cells = <3>;
 482                         device_type = "pci";
 483                         ranges = <0x2000000 0x0 0x80000000
 484                                   0x2000000 0x0 0x80000000
 485                                   0x0 0x20000000
 486
 487                                   0x1000000 0x0 0x0
 488                                   0x1000000 0x0 0x0
 489                                   0x0 0x100000>;
 490                         uli1575@0 {
 491                                 reg = <0x0 0x0 0x0 0x0 0x0>;
 492                                 #size-cells = <2>;
 493                                 #address-cells = <3>;
 494                                 ranges = <0x2000000 0x0 0x80000000
 495                                           0x2000000 0x0 0x80000000
 496                                           0x0 0x20000000
 497
 498                                           0x1000000 0x0 0x0
 499                                           0x1000000 0x0 0x0
 500                                           0x0 0x100000>;
 501                                 isa@1e {
 502                                         device_type = "isa";
 503                                         #interrupt-cells = <2>;
 504                                         #size-cells = <1>;
 505                                         #address-cells = <2>;
 506                                         reg = <0xf000 0x0 0x0 0x0 0x0>;
 507                                         ranges = <0x1 0x0 0x1000000 0x0 0x0
 508                                                   0x1000>;
 509                                         interrupt-parent = <&i8259>;
 510
 511                                         i8259: interrupt-controller@20 {
 512                                                 reg = <0x1 0x20 0x2
 513                                                        0x1 0xa0 0x2
 514                                                        0x1 0x4d0 0x2>;
 515                                                 interrupt-controller;
 516                                                 device_type = "interrupt-controller";
 517                                                 #address-cells = <0>;
 518                                                 #interrupt-cells = <2>;
 519                                                 compatible = "chrp,iic";
 520                                                 interrupts = <9 2>;
 521                                                 interrupt-parent = <&mpic>;
 522                                         };
 523
 524                                         i8042@60 {
 525                                                 #size-cells = <0>;
 526                                                 #address-cells = <1>;
 527                                                 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
 528                                                 interrupts = <1 3 12 3>;
 529                                                 interrupt-parent =
 530                                                         <&i8259>;
 531
 532                                                 keyboard@0 {
 533                                                         reg = <0x0>;
 534                                                         compatible = "pnpPNP,303";
 535                                                 };
 536
 537                                                 mouse@1 {
 538                                                         reg = <0x1>;
 539                                                         compatible = "pnpPNP,f03";
 540                                                 };
 541                                         };
 542
 543                                         rtc@70 {
 544                                                 compatible = "pnpPNP,b00";
 545                                                 reg = <0x1 0x70 0x2>;
 546                                         };
 547
 548                                         gpio@400 {
 549                                                 reg = <0x1 0x400 0x80>;
 550                                         };
 551                                 };
 552                         };
 553                 };
 554
 555         };
 556
 557         pci1: pcie@ffe09000 {
 558                 cell-index = <1>;
 559                 compatible = "fsl,mpc8548-pcie";
 560                 device_type = "pci";
 561                 #interrupt-cells = <1>;
 562                 #size-cells = <2>;
 563                 #address-cells = <3>;
 564                 reg = <0xffe09000 0x1000>;
 565                 bus-range = <0 255>;
 566                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
 567                           0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
 568                 clock-frequency = <33333333>;
 569                 interrupt-parent = <&mpic>;
 570                 interrupts = <26 2>;
 571                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 572                 interrupt-map = <
 573                         /* IDSEL 0x0 */
 574                         0000 0x0 0x0 0x1 &mpic 0x4 0x1
 575                         0000 0x0 0x0 0x2 &mpic 0x5 0x1
 576                         0000 0x0 0x0 0x3 &mpic 0x6 0x1
 577                         0000 0x0 0x0 0x4 &mpic 0x7 0x1
 578                         >;
 579                 pcie@0 {
 580                         reg = <0x0 0x0 0x0 0x0 0x0>;
 581                         #size-cells = <2>;
 582                         #address-cells = <3>;
 583                         device_type = "pci";
 584                         ranges = <0x2000000 0x0 0xa0000000
 585                                   0x2000000 0x0 0xa0000000
 586                                   0x0 0x20000000
 587
 588                                   0x1000000 0x0 0x0
 589                                   0x1000000 0x0 0x0
 590                                   0x0 0x100000>;
 591                 };
 592         };
 593
 594         pci2: pcie@ffe0a000 {
 595                 cell-index = <2>;
 596                 compatible = "fsl,mpc8548-pcie";
 597                 device_type = "pci";
 598                 #interrupt-cells = <1>;
 599                 #size-cells = <2>;
 600                 #address-cells = <3>;
 601                 reg = <0xffe0a000 0x1000>;
 602                 bus-range = <0 255>;
 603                 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
 604                           0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
 605                 clock-frequency = <33333333>;
 606                 interrupt-parent = <&mpic>;
 607                 interrupts = <27 2>;
 608                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 609                 interrupt-map = <
 610                         /* IDSEL 0x0 */
 611                         0000 0x0 0x0 0x1 &mpic 0x0 0x1
 612                         0000 0x0 0x0 0x2 &mpic 0x1 0x1
 613                         0000 0x0 0x0 0x3 &mpic 0x2 0x1
 614                         0000 0x0 0x0 0x4 &mpic 0x3 0x1
 615                         >;
 616                 pcie@0 {
 617                         reg = <0x0 0x0 0x0 0x0 0x0>;
 618                         #size-cells = <2>;
 619                         #address-cells = <3>;
 620                         device_type = "pci";
 621                         ranges = <0x2000000 0x0 0xc0000000
 622                                   0x2000000 0x0 0xc0000000
 623                                   0x0 0x20000000
 624
 625                                   0x1000000 0x0 0x0
 626                                   0x1000000 0x0 0x0
 627                                   0x0 0x100000>;
 628                 };
 629         };
 630 };