arch/powerpc/boot/dts/mpc8572ds.dts

   1 /*
   2  * MPC8572 DS Device Tree Source
   3  *
   4  * Copyright 2007 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 / {
  13         model = "fsl,MPC8572DS";
  14         compatible = "fsl,MPC8572DS";
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         aliases {
  19                 ethernet0 = &enet0;
  20                 ethernet1 = &enet1;
  21                 ethernet2 = &enet2;
  22                 ethernet3 = &enet3;
  23                 serial0 = &serial0;
  24                 serial1 = &serial1;
  25                 pci0 = &pci0;
  26                 pci1 = &pci1;
  27                 pci2 = &pci2;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 PowerPC,8572@0 {
  35                         device_type = "cpu";
  36                         reg = <0>;
  37                         d-cache-line-size = <20>;       // 32 bytes
  38                         i-cache-line-size = <20>;       // 32 bytes
  39                         d-cache-size = <8000>;          // L1, 32K
  40                         i-cache-size = <8000>;          // L1, 32K
  41                         timebase-frequency = <0>;
  42                         bus-frequency = <0>;
  43                         clock-frequency = <0>;
  44                 };
  45         };
  46
  47         memory {
  48                 device_type = "memory";
  49                 reg = <00000000 00000000>;      // Filled by U-Boot
  50         };
  51
  52         soc8572@ffe00000 {
  53                 #address-cells = <1>;
  54                 #size-cells = <1>;
  55                 device_type = "soc";
  56                 ranges = <00000000 ffe00000 00100000>;
  57                 reg = <ffe00000 00001000>;      // CCSRBAR & soc regs, remove once parse code for immrbase fixed
  58                 bus-frequency = <0>;            // Filled out by uboot.
  59
  60                 memory-controller@2000 {
  61                         compatible = "fsl,mpc8572-memory-controller";
  62                         reg = <2000 1000>;
  63                         interrupt-parent = <&mpic>;
  64                         interrupts = <12 2>;
  65                 };
  66
  67                 memory-controller@6000 {
  68                         compatible = "fsl,mpc8572-memory-controller";
  69                         reg = <6000 1000>;
  70                         interrupt-parent = <&mpic>;
  71                         interrupts = <12 2>;
  72                 };
  73
  74                 l2-cache-controller@20000 {
  75                         compatible = "fsl,mpc8572-l2-cache-controller";
  76                         reg = <20000 1000>;
  77                         cache-line-size = <20>; // 32 bytes
  78                         cache-size = <80000>;   // L2, 512K
  79                         interrupt-parent = <&mpic>;
  80                         interrupts = <10 2>;
  81                 };
  82
  83                 i2c@3000 {
  84                         #address-cells = <1>;
  85                         #size-cells = <0>;
  86                         cell-index = <0>;
  87                         compatible = "fsl-i2c";
  88                         reg = <3000 100>;
  89                         interrupts = <2b 2>;
  90                         interrupt-parent = <&mpic>;
  91                         dfsrr;
  92                 };
  93
  94                 i2c@3100 {
  95                         #address-cells = <1>;
  96                         #size-cells = <0>;
  97                         cell-index = <1>;
  98                         compatible = "fsl-i2c";
  99                         reg = <3100 100>;
 100                         interrupts = <2b 2>;
 101                         interrupt-parent = <&mpic>;
 102                         dfsrr;
 103                 };
 104
 105                 mdio@24520 {
 106                         #address-cells = <1>;
 107                         #size-cells = <0>;
 108                         compatible = "fsl,gianfar-mdio";
 109                         reg = <24520 20>;
 110
 111                         phy0: ethernet-phy@0 {
 112                                 interrupt-parent = <&mpic>;
 113                                 interrupts = <a 1>;
 114                                 reg = <0>;
 115                         };
 116                         phy1: ethernet-phy@1 {
 117                                 interrupt-parent = <&mpic>;
 118                                 interrupts = <a 1>;
 119                                 reg = <1>;
 120                         };
 121                         phy2: ethernet-phy@2 {
 122                                 interrupt-parent = <&mpic>;
 123                                 interrupts = <a 1>;
 124                                 reg = <2>;
 125                         };
 126                         phy3: ethernet-phy@3 {
 127                                 interrupt-parent = <&mpic>;
 128                                 interrupts = <a 1>;
 129                                 reg = <3>;
 130                         };
 131                 };
 132
 133                 enet0: ethernet@24000 {
 134                         cell-index = <0>;
 135                         device_type = "network";
 136                         model = "eTSEC";
 137                         compatible = "gianfar";
 138                         reg = <24000 1000>;
 139                         local-mac-address = [ 00 00 00 00 00 00 ];
 140                         interrupts = <1d 2 1e 2 22 2>;
 141                         interrupt-parent = <&mpic>;
 142                         phy-handle = <&phy0>;
 143                         phy-connection-type = "rgmii-id";
 144                 };
 145
 146                 enet1: ethernet@25000 {
 147                         cell-index = <1>;
 148                         device_type = "network";
 149                         model = "eTSEC";
 150                         compatible = "gianfar";
 151                         reg = <25000 1000>;
 152                         local-mac-address = [ 00 00 00 00 00 00 ];
 153                         interrupts = <23 2 24 2 28 2>;
 154                         interrupt-parent = <&mpic>;
 155                         phy-handle = <&phy1>;
 156                         phy-connection-type = "rgmii-id";
 157                 };
 158
 159                 enet2: ethernet@26000 {
 160                         cell-index = <2>;
 161                         device_type = "network";
 162                         model = "eTSEC";
 163                         compatible = "gianfar";
 164                         reg = <26000 1000>;
 165                         local-mac-address = [ 00 00 00 00 00 00 ];
 166                         interrupts = <1f 2 20 2 21 2>;
 167                         interrupt-parent = <&mpic>;
 168                         phy-handle = <&phy2>;
 169                         phy-connection-type = "rgmii-id";
 170                 };
 171
 172                 enet3: ethernet@27000 {
 173                         cell-index = <3>;
 174                         device_type = "network";
 175                         model = "eTSEC";
 176                         compatible = "gianfar";
 177                         reg = <27000 1000>;
 178                         local-mac-address = [ 00 00 00 00 00 00 ];
 179                         interrupts = <25 2 26 2 27 2>;
 180                         interrupt-parent = <&mpic>;
 181                         phy-handle = <&phy3>;
 182                         phy-connection-type = "rgmii-id";
 183                 };
 184
 185                 serial0: serial@4500 {
 186                         cell-index = <0>;
 187                         device_type = "serial";
 188                         compatible = "ns16550";
 189                         reg = <4500 100>;
 190                         clock-frequency = <0>;
 191                         interrupts = <2a 2>;
 192                         interrupt-parent = <&mpic>;
 193                 };
 194
 195                 serial1: serial@4600 {
 196                         cell-index = <1>;
 197                         device_type = "serial";
 198                         compatible = "ns16550";
 199                         reg = <4600 100>;
 200                         clock-frequency = <0>;
 201                         interrupts = <2a 2>;
 202                         interrupt-parent = <&mpic>;
 203                 };
 204
 205                 global-utilities@e0000 {        //global utilities block
 206                         compatible = "fsl,mpc8572-guts";
 207                         reg = <e0000 1000>;
 208                         fsl,has-rstcr;
 209                 };
 210
 211                 mpic: pic@40000 {
 212                         clock-frequency = <0>;
 213                         interrupt-controller;
 214                         #address-cells = <0>;
 215                         #interrupt-cells = <2>;
 216                         reg = <40000 40000>;
 217                         compatible = "chrp,open-pic";
 218                         device_type = "open-pic";
 219                         big-endian;
 220                 };
 221         };
 222
 223         pci0: pcie@ffe08000 {
 224                 cell-index = <0>;
 225                 compatible = "fsl,mpc8548-pcie";
 226                 device_type = "pci";
 227                 #interrupt-cells = <1>;
 228                 #size-cells = <2>;
 229                 #address-cells = <3>;
 230                 reg = <ffe08000 1000>;
 231                 bus-range = <0 ff>;
 232                 ranges = <02000000 0 80000000 80000000 0 20000000
 233                           01000000 0 00000000 ffc00000 0 00010000>;
 234                 clock-frequency = <1fca055>;
 235                 interrupt-parent = <&mpic>;
 236                 interrupts = <18 2>;
 237                 interrupt-map-mask = <ff00 0 0 7>;
 238                 interrupt-map = <
 239                         /* IDSEL 0x11 func 0 - PCI slot 1 */
 240                         8800 0 0 1 &mpic 2 1
 241                         8800 0 0 2 &mpic 3 1
 242                         8800 0 0 3 &mpic 4 1
 243                         8800 0 0 4 &mpic 1 1
 244
 245                         /* IDSEL 0x11 func 1 - PCI slot 1 */
 246                         8900 0 0 1 &mpic 2 1
 247                         8900 0 0 2 &mpic 3 1
 248                         8900 0 0 3 &mpic 4 1
 249                         8900 0 0 4 &mpic 1 1
 250
 251                         /* IDSEL 0x11 func 2 - PCI slot 1 */
 252                         8a00 0 0 1 &mpic 2 1
 253                         8a00 0 0 2 &mpic 3 1
 254                         8a00 0 0 3 &mpic 4 1
 255                         8a00 0 0 4 &mpic 1 1
 256
 257                         /* IDSEL 0x11 func 3 - PCI slot 1 */
 258                         8b00 0 0 1 &mpic 2 1
 259                         8b00 0 0 2 &mpic 3 1
 260                         8b00 0 0 3 &mpic 4 1
 261                         8b00 0 0 4 &mpic 1 1
 262
 263                         /* IDSEL 0x11 func 4 - PCI slot 1 */
 264                         8c00 0 0 1 &mpic 2 1
 265                         8c00 0 0 2 &mpic 3 1
 266                         8c00 0 0 3 &mpic 4 1
 267                         8c00 0 0 4 &mpic 1 1
 268
 269                         /* IDSEL 0x11 func 5 - PCI slot 1 */
 270                         8d00 0 0 1 &mpic 2 1
 271                         8d00 0 0 2 &mpic 3 1
 272                         8d00 0 0 3 &mpic 4 1
 273                         8d00 0 0 4 &mpic 1 1
 274
 275                         /* IDSEL 0x11 func 6 - PCI slot 1 */
 276                         8e00 0 0 1 &mpic 2 1
 277                         8e00 0 0 2 &mpic 3 1
 278                         8e00 0 0 3 &mpic 4 1
 279                         8e00 0 0 4 &mpic 1 1
 280
 281                         /* IDSEL 0x11 func 7 - PCI slot 1 */
 282                         8f00 0 0 1 &mpic 2 1
 283                         8f00 0 0 2 &mpic 3 1
 284                         8f00 0 0 3 &mpic 4 1
 285                         8f00 0 0 4 &mpic 1 1
 286
 287                         /* IDSEL 0x12 func 0 - PCI slot 2 */
 288                         9000 0 0 1 &mpic 3 1
 289                         9000 0 0 2 &mpic 4 1
 290                         9000 0 0 3 &mpic 1 1
 291                         9000 0 0 4 &mpic 2 1
 292
 293                         /* IDSEL 0x12 func 1 - PCI slot 2 */
 294                         9100 0 0 1 &mpic 3 1
 295                         9100 0 0 2 &mpic 4 1
 296                         9100 0 0 3 &mpic 1 1
 297                         9100 0 0 4 &mpic 2 1
 298
 299                         /* IDSEL 0x12 func 2 - PCI slot 2 */
 300                         9200 0 0 1 &mpic 3 1
 301                         9200 0 0 2 &mpic 4 1
 302                         9200 0 0 3 &mpic 1 1
 303                         9200 0 0 4 &mpic 2 1
 304
 305                         /* IDSEL 0x12 func 3 - PCI slot 2 */
 306                         9300 0 0 1 &mpic 3 1
 307                         9300 0 0 2 &mpic 4 1
 308                         9300 0 0 3 &mpic 1 1
 309                         9300 0 0 4 &mpic 2 1
 310
 311                         /* IDSEL 0x12 func 4 - PCI slot 2 */
 312                         9400 0 0 1 &mpic 3 1
 313                         9400 0 0 2 &mpic 4 1
 314                         9400 0 0 3 &mpic 1 1
 315                         9400 0 0 4 &mpic 2 1
 316
 317                         /* IDSEL 0x12 func 5 - PCI slot 2 */
 318                         9500 0 0 1 &mpic 3 1
 319                         9500 0 0 2 &mpic 4 1
 320                         9500 0 0 3 &mpic 1 1
 321                         9500 0 0 4 &mpic 2 1
 322
 323                         /* IDSEL 0x12 func 6 - PCI slot 2 */
 324                         9600 0 0 1 &mpic 3 1
 325                         9600 0 0 2 &mpic 4 1
 326                         9600 0 0 3 &mpic 1 1
 327                         9600 0 0 4 &mpic 2 1
 328
 329                         /* IDSEL 0x12 func 7 - PCI slot 2 */
 330                         9700 0 0 1 &mpic 3 1
 331                         9700 0 0 2 &mpic 4 1
 332                         9700 0 0 3 &mpic 1 1
 333                         9700 0 0 4 &mpic 2 1
 334
 335                         // IDSEL 0x1c  USB
 336                         e000 0 0 1 &i8259 c 2
 337                         e100 0 0 2 &i8259 9 2
 338                         e200 0 0 3 &i8259 a 2
 339                         e300 0 0 4 &i8259 b 2
 340
 341                         // IDSEL 0x1d  Audio
 342                         e800 0 0 1 &i8259 6 2
 343
 344                         // IDSEL 0x1e Legacy
 345                         f000 0 0 1 &i8259 7 2
 346                         f100 0 0 1 &i8259 7 2
 347
 348                         // IDSEL 0x1f IDE/SATA
 349                         f800 0 0 1 &i8259 e 2
 350                         f900 0 0 1 &i8259 5 2
 351
 352                         >;
 353
 354                 pcie@0 {
 355                         reg = <0 0 0 0 0>;
 356                         #size-cells = <2>;
 357                         #address-cells = <3>;
 358                         device_type = "pci";
 359                         ranges = <02000000 0 80000000
 360                                   02000000 0 80000000
 361                                   0 20000000
 362
 363                                   01000000 0 00000000
 364                                   01000000 0 00000000
 365                                   0 00100000>;
 366                         uli1575@0 {
 367                                 reg = <0 0 0 0 0>;
 368                                 #size-cells = <2>;
 369                                 #address-cells = <3>;
 370                                 ranges = <02000000 0 80000000
 371                                           02000000 0 80000000
 372                                           0 20000000
 373
 374                                           01000000 0 00000000
 375                                           01000000 0 00000000
 376                                           0 00100000>;
 377                                 isa@1e {
 378                                         device_type = "isa";
 379                                         #interrupt-cells = <2>;
 380                                         #size-cells = <1>;
 381                                         #address-cells = <2>;
 382                                         reg = <f000 0 0 0 0>;
 383                                         ranges = <1 0 01000000 0 0
 384                                                   00001000>;
 385                                         interrupt-parent = <&i8259>;
 386
 387                                         i8259: interrupt-controller@20 {
 388                                                 reg = <1 20 2
 389                                                        1 a0 2
 390                                                        1 4d0 2>;
 391                                                 interrupt-controller;
 392                                                 device_type = "interrupt-controller";
 393                                                 #address-cells = <0>;
 394                                                 #interrupt-cells = <2>;
 395                                                 compatible = "chrp,iic";
 396                                                 interrupts = <9 2>;
 397                                                 interrupt-parent = <&mpic>;
 398                                         };
 399
 400                                         i8042@60 {
 401                                                 #size-cells = <0>;
 402                                                 #address-cells = <1>;
 403                                                 reg = <1 60 1 1 64 1>;
 404                                                 interrupts = <1 3 c 3>;
 405                                                 interrupt-parent =
 406                                                         <&i8259>;
 407
 408                                                 keyboard@0 {
 409                                                         reg = <0>;
 410                                                         compatible = "pnpPNP,303";
 411                                                 };
 412
 413                                                 mouse@1 {
 414                                                         reg = <1>;
 415                                                         compatible = "pnpPNP,f03";
 416                                                 };
 417                                         };
 418
 419                                         rtc@70 {
 420                                                 compatible = "pnpPNP,b00";
 421                                                 reg = <1 70 2>;
 422                                         };
 423
 424                                         gpio@400 {
 425                                                 reg = <1 400 80>;
 426                                         };
 427                                 };
 428                         };
 429                 };
 430
 431         };
 432
 433         pci1: pcie@ffe09000 {
 434                 cell-index = <1>;
 435                 compatible = "fsl,mpc8548-pcie";
 436                 device_type = "pci";
 437                 #interrupt-cells = <1>;
 438                 #size-cells = <2>;
 439                 #address-cells = <3>;
 440                 reg = <ffe09000 1000>;
 441                 bus-range = <0 ff>;
 442                 ranges = <02000000 0 a0000000 a0000000 0 20000000
 443                           01000000 0 00000000 ffc10000 0 00010000>;
 444                 clock-frequency = <1fca055>;
 445                 interrupt-parent = <&mpic>;
 446                 interrupts = <1a 2>;
 447                 interrupt-map-mask = <f800 0 0 7>;
 448                 interrupt-map = <
 449                         /* IDSEL 0x0 */
 450                         0000 0 0 1 &mpic 4 1
 451                         0000 0 0 2 &mpic 5 1
 452                         0000 0 0 3 &mpic 6 1
 453                         0000 0 0 4 &mpic 7 1
 454                         >;
 455                 pcie@0 {
 456                         reg = <0 0 0 0 0>;
 457                         #size-cells = <2>;
 458                         #address-cells = <3>;
 459                         device_type = "pci";
 460                         ranges = <02000000 0 a0000000
 461                                   02000000 0 a0000000
 462                                   0 20000000
 463
 464                                   01000000 0 00000000
 465                                   01000000 0 00000000
 466                                   0 00100000>;
 467                 };
 468         };
 469
 470         pci2: pcie@ffe0a000 {
 471                 cell-index = <2>;
 472                 compatible = "fsl,mpc8548-pcie";
 473                 device_type = "pci";
 474                 #interrupt-cells = <1>;
 475                 #size-cells = <2>;
 476                 #address-cells = <3>;
 477                 reg = <ffe0a000 1000>;
 478                 bus-range = <0 ff>;
 479                 ranges = <02000000 0 c0000000 c0000000 0 20000000
 480                           01000000 0 00000000 ffc20000 0 00010000>;
 481                 clock-frequency = <1fca055>;
 482                 interrupt-parent = <&mpic>;
 483                 interrupts = <1b 2>;
 484                 interrupt-map-mask = <f800 0 0 7>;
 485                 interrupt-map = <
 486                         /* IDSEL 0x0 */
 487                         0000 0 0 1 &mpic 0 1
 488                         0000 0 0 2 &mpic 1 1
 489                         0000 0 0 3 &mpic 2 1
 490                         0000 0 0 4 &mpic 3 1
 491                         >;
 492                 pcie@0 {
 493                         reg = <0 0 0 0 0>;
 494                         #size-cells = <2>;
 495                         #address-cells = <3>;
 496                         device_type = "pci";
 497                         ranges = <02000000 0 c0000000
 498                                   02000000 0 c0000000
 499                                   0 20000000
 500
 501                                   01000000 0 00000000
 502                                   01000000 0 00000000
 503                                   0 00100000>;
 504                 };
 505         };
 506 };