arch/powerpc/boot/dts/mpc8548cds.dts

   1 /*
   2  * MPC8548 CDS Device Tree Source
   3  *
   4  * Copyright 2006, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8548CDS";
  16         compatible = "MPC8548CDS", "MPC85xxCDS";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23 /*
  24                 ethernet2 = &enet2;
  25                 ethernet3 = &enet3;
  26 */
  27                 serial0 = &serial0;
  28                 serial1 = &serial1;
  29                 pci0 = &pci0;
  30                 pci1 = &pci1;
  31                 pci2 = &pci2;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 PowerPC,8548@0 {
  39                         device_type = "cpu";
  40                         reg = <0x0>;
  41                         d-cache-line-size = <32>;       // 32 bytes
  42                         i-cache-line-size = <32>;       // 32 bytes
  43                         d-cache-size = <0x8000>;                // L1, 32K
  44                         i-cache-size = <0x8000>;                // L1, 32K
  45                         timebase-frequency = <0>;       //  33 MHz, from uboot
  46                         bus-frequency = <0>;    // 166 MHz
  47                         clock-frequency = <0>;  // 825 MHz, from uboot
  48                         next-level-cache = <&L2>;
  49                 };
  50         };
  51
  52         memory {
  53                 device_type = "memory";
  54                 reg = <0x0 0x8000000>;  // 128M at 0x0
  55         };
  56
  57         soc8548@e0000000 {
  58                 #address-cells = <1>;
  59                 #size-cells = <1>;
  60                 device_type = "soc";
  61                 compatible = "simple-bus";
  62                 ranges = <0x0 0xe0000000 0x100000>;
  63                 reg = <0xe0000000 0x1000>;      // CCSRBAR
  64                 bus-frequency = <0>;
  65
  66                 memory-controller@2000 {
  67                         compatible = "fsl,8548-memory-controller";
  68                         reg = <0x2000 0x1000>;
  69                         interrupt-parent = <&mpic>;
  70                         interrupts = <18 2>;
  71                 };
  72
  73                 L2: l2-cache-controller@20000 {
  74                         compatible = "fsl,8548-l2-cache-controller";
  75                         reg = <0x20000 0x1000>;
  76                         cache-line-size = <32>; // 32 bytes
  77                         cache-size = <0x80000>; // L2, 512K
  78                         interrupt-parent = <&mpic>;
  79                         interrupts = <16 2>;
  80                 };
  81
  82                 i2c@3000 {
  83                         #address-cells = <1>;
  84                         #size-cells = <0>;
  85                         cell-index = <0>;
  86                         compatible = "fsl-i2c";
  87                         reg = <0x3000 0x100>;
  88                         interrupts = <43 2>;
  89                         interrupt-parent = <&mpic>;
  90                         dfsrr;
  91                 };
  92
  93                 i2c@3100 {
  94                         #address-cells = <1>;
  95                         #size-cells = <0>;
  96                         cell-index = <1>;
  97                         compatible = "fsl-i2c";
  98                         reg = <0x3100 0x100>;
  99                         interrupts = <43 2>;
 100                         interrupt-parent = <&mpic>;
 101                         dfsrr;
 102                 };
 103
 104                 dma@21300 {
 105                         #address-cells = <1>;
 106                         #size-cells = <1>;
 107                         compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
 108                         reg = <0x21300 0x4>;
 109                         ranges = <0x0 0x21100 0x200>;
 110                         cell-index = <0>;
 111                         dma-channel@0 {
 112                                 compatible = "fsl,mpc8548-dma-channel",
 113                                                 "fsl,eloplus-dma-channel";
 114                                 reg = <0x0 0x80>;
 115                                 cell-index = <0>;
 116                                 interrupt-parent = <&mpic>;
 117                                 interrupts = <20 2>;
 118                         };
 119                         dma-channel@80 {
 120                                 compatible = "fsl,mpc8548-dma-channel",
 121                                                 "fsl,eloplus-dma-channel";
 122                                 reg = <0x80 0x80>;
 123                                 cell-index = <1>;
 124                                 interrupt-parent = <&mpic>;
 125                                 interrupts = <21 2>;
 126                         };
 127                         dma-channel@100 {
 128                                 compatible = "fsl,mpc8548-dma-channel",
 129                                                 "fsl,eloplus-dma-channel";
 130                                 reg = <0x100 0x80>;
 131                                 cell-index = <2>;
 132                                 interrupt-parent = <&mpic>;
 133                                 interrupts = <22 2>;
 134                         };
 135                         dma-channel@180 {
 136                                 compatible = "fsl,mpc8548-dma-channel",
 137                                                 "fsl,eloplus-dma-channel";
 138                                 reg = <0x180 0x80>;
 139                                 cell-index = <3>;
 140                                 interrupt-parent = <&mpic>;
 141                                 interrupts = <23 2>;
 142                         };
 143                 };
 144
 145                 mdio@24520 {
 146                         #address-cells = <1>;
 147                         #size-cells = <0>;
 148                         compatible = "fsl,gianfar-mdio";
 149                         reg = <0x24520 0x20>;
 150
 151                         phy0: ethernet-phy@0 {
 152                                 interrupt-parent = <&mpic>;
 153                                 interrupts = <5 1>;
 154                                 reg = <0x0>;
 155                                 device_type = "ethernet-phy";
 156                         };
 157                         phy1: ethernet-phy@1 {
 158                                 interrupt-parent = <&mpic>;
 159                                 interrupts = <5 1>;
 160                                 reg = <0x1>;
 161                                 device_type = "ethernet-phy";
 162                         };
 163                         phy2: ethernet-phy@2 {
 164                                 interrupt-parent = <&mpic>;
 165                                 interrupts = <5 1>;
 166                                 reg = <0x2>;
 167                                 device_type = "ethernet-phy";
 168                         };
 169                         phy3: ethernet-phy@3 {
 170                                 interrupt-parent = <&mpic>;
 171                                 interrupts = <5 1>;
 172                                 reg = <0x3>;
 173                                 device_type = "ethernet-phy";
 174                         };
 175                         tbi0: tbi-phy@11 {
 176                                 reg = <0x11>;
 177                                 device_type = "tbi-phy";
 178                         };
 179                 };
 180
 181                 mdio@25520 {
 182                         #address-cells = <1>;
 183                         #size-cells = <0>;
 184                         compatible = "fsl,gianfar-tbi";
 185                         reg = <0x25520 0x20>;
 186
 187                         tbi1: tbi-phy@11 {
 188                                 reg = <0x11>;
 189                                 device_type = "tbi-phy";
 190                         };
 191                 };
 192
 193                 mdio@26520 {
 194                         #address-cells = <1>;
 195                         #size-cells = <0>;
 196                         compatible = "fsl,gianfar-tbi";
 197                         reg = <0x26520 0x20>;
 198
 199                         tbi2: tbi-phy@11 {
 200                                 reg = <0x11>;
 201                                 device_type = "tbi-phy";
 202                         };
 203                 };
 204
 205                 mdio@27520 {
 206                         #address-cells = <1>;
 207                         #size-cells = <0>;
 208                         compatible = "fsl,gianfar-tbi";
 209                         reg = <0x27520 0x20>;
 210
 211                         tbi3: tbi-phy@11 {
 212                                 reg = <0x11>;
 213                                 device_type = "tbi-phy";
 214                         };
 215                 };
 216
 217                 enet0: ethernet@24000 {
 218                         cell-index = <0>;
 219                         device_type = "network";
 220                         model = "eTSEC";
 221                         compatible = "gianfar";
 222                         reg = <0x24000 0x1000>;
 223                         local-mac-address = [ 00 00 00 00 00 00 ];
 224                         interrupts = <29 2 30 2 34 2>;
 225                         interrupt-parent = <&mpic>;
 226                         tbi-handle = <&tbi0>;
 227                         phy-handle = <&phy0>;
 228                 };
 229
 230                 enet1: ethernet@25000 {
 231                         cell-index = <1>;
 232                         device_type = "network";
 233                         model = "eTSEC";
 234                         compatible = "gianfar";
 235                         reg = <0x25000 0x1000>;
 236                         local-mac-address = [ 00 00 00 00 00 00 ];
 237                         interrupts = <35 2 36 2 40 2>;
 238                         interrupt-parent = <&mpic>;
 239                         tbi-handle = <&tbi1>;
 240                         phy-handle = <&phy1>;
 241                 };
 242
 243 /* eTSEC 3/4 are currently broken
 244                 enet2: ethernet@26000 {
 245                         cell-index = <2>;
 246                         device_type = "network";
 247                         model = "eTSEC";
 248                         compatible = "gianfar";
 249                         reg = <0x26000 0x1000>;
 250                         local-mac-address = [ 00 00 00 00 00 00 ];
 251                         interrupts = <31 2 32 2 33 2>;
 252                         interrupt-parent = <&mpic>;
 253                         tbi-handle = <&tbi2>;
 254                         phy-handle = <&phy2>;
 255                 };
 256
 257                 enet3: ethernet@27000 {
 258                         cell-index = <3>;
 259                         device_type = "network";
 260                         model = "eTSEC";
 261                         compatible = "gianfar";
 262                         reg = <0x27000 0x1000>;
 263                         local-mac-address = [ 00 00 00 00 00 00 ];
 264                         interrupts = <37 2 38 2 39 2>;
 265                         interrupt-parent = <&mpic>;
 266                         tbi-handle = <&tbi3>;
 267                         phy-handle = <&phy3>;
 268                 };
 269  */
 270
 271                 serial0: serial@4500 {
 272                         cell-index = <0>;
 273                         device_type = "serial";
 274                         compatible = "ns16550";
 275                         reg = <0x4500 0x100>;   // reg base, size
 276                         clock-frequency = <0>;  // should we fill in in uboot?
 277                         interrupts = <42 2>;
 278                         interrupt-parent = <&mpic>;
 279                 };
 280
 281                 serial1: serial@4600 {
 282                         cell-index = <1>;
 283                         device_type = "serial";
 284                         compatible = "ns16550";
 285                         reg = <0x4600 0x100>;   // reg base, size
 286                         clock-frequency = <0>;  // should we fill in in uboot?
 287                         interrupts = <42 2>;
 288                         interrupt-parent = <&mpic>;
 289                 };
 290
 291                 global-utilities@e0000 {        //global utilities reg
 292                         compatible = "fsl,mpc8548-guts";
 293                         reg = <0xe0000 0x1000>;
 294                         fsl,has-rstcr;
 295                 };
 296
 297                 crypto@30000 {
 298                         compatible = "fsl,sec2.1", "fsl,sec2.0";
 299                         reg = <0x30000 0x10000>;
 300                         interrupts = <45 2>;
 301                         interrupt-parent = <&mpic>;
 302                         fsl,num-channels = <4>;
 303                         fsl,channel-fifo-len = <24>;
 304                         fsl,exec-units-mask = <0xfe>;
 305                         fsl,descriptor-types-mask = <0x12b0ebf>;
 306                 };
 307
 308                 mpic: pic@40000 {
 309                         interrupt-controller;
 310                         #address-cells = <0>;
 311                         #interrupt-cells = <2>;
 312                         reg = <0x40000 0x40000>;
 313                         compatible = "chrp,open-pic";
 314                         device_type = "open-pic";
 315                 };
 316         };
 317
 318         pci0: pci@e0008000 {
 319                 cell-index = <0>;
 320                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 321                 interrupt-map = <
 322                         /* IDSEL 0x4 (PCIX Slot 2) */
 323                         0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
 324                         0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
 325                         0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
 326                         0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
 327
 328                         /* IDSEL 0x5 (PCIX Slot 3) */
 329                         0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
 330                         0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
 331                         0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
 332                         0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
 333
 334                         /* IDSEL 0x6 (PCIX Slot 4) */
 335                         0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
 336                         0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
 337                         0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
 338                         0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
 339
 340                         /* IDSEL 0x8 (PCIX Slot 5) */
 341                         0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
 342                         0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
 343                         0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
 344                         0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
 345
 346                         /* IDSEL 0xC (Tsi310 bridge) */
 347                         0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
 348                         0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
 349                         0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
 350                         0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
 351
 352                         /* IDSEL 0x14 (Slot 2) */
 353                         0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
 354                         0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
 355                         0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
 356                         0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
 357
 358                         /* IDSEL 0x15 (Slot 3) */
 359                         0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
 360                         0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
 361                         0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
 362                         0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
 363
 364                         /* IDSEL 0x16 (Slot 4) */
 365                         0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
 366                         0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
 367                         0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
 368                         0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
 369
 370                         /* IDSEL 0x18 (Slot 5) */
 371                         0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
 372                         0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
 373                         0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
 374                         0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
 375
 376                         /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
 377                         0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
 378                         0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
 379                         0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
 380                         0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 381
 382                 interrupt-parent = <&mpic>;
 383                 interrupts = <24 2>;
 384                 bus-range = <0 0>;
 385                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 386                           0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
 387                 clock-frequency = <66666666>;
 388                 #interrupt-cells = <1>;
 389                 #size-cells = <2>;
 390                 #address-cells = <3>;
 391                 reg = <0xe0008000 0x1000>;
 392                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
 393                 device_type = "pci";
 394
 395                 pci_bridge@1c {
 396                         interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 397                         interrupt-map = <
 398
 399                                 /* IDSEL 0x00 (PrPMC Site) */
 400                                 0000 0x0 0x0 0x1 &mpic 0x0 0x1
 401                                 0000 0x0 0x0 0x2 &mpic 0x1 0x1
 402                                 0000 0x0 0x0 0x3 &mpic 0x2 0x1
 403                                 0000 0x0 0x0 0x4 &mpic 0x3 0x1
 404
 405                                 /* IDSEL 0x04 (VIA chip) */
 406                                 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
 407                                 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
 408                                 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
 409                                 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
 410
 411                                 /* IDSEL 0x05 (8139) */
 412                                 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
 413
 414                                 /* IDSEL 0x06 (Slot 6) */
 415                                 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
 416                                 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
 417                                 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
 418                                 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
 419
 420                                 /* IDESL 0x07 (Slot 7) */
 421                                 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
 422                                 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
 423                                 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
 424                                 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
 425
 426                         reg = <0xe000 0x0 0x0 0x0 0x0>;
 427                         #interrupt-cells = <1>;
 428                         #size-cells = <2>;
 429                         #address-cells = <3>;
 430                         ranges = <0x2000000 0x0 0x80000000
 431                                   0x2000000 0x0 0x80000000
 432                                   0x0 0x20000000
 433                                   0x1000000 0x0 0x0
 434                                   0x1000000 0x0 0x0
 435                                   0x0 0x80000>;
 436                         clock-frequency = <33333333>;
 437
 438                         isa@4 {
 439                                 device_type = "isa";
 440                                 #interrupt-cells = <2>;
 441                                 #size-cells = <1>;
 442                                 #address-cells = <2>;
 443                                 reg = <0x2000 0x0 0x0 0x0 0x0>;
 444                                 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
 445                                 interrupt-parent = <&i8259>;
 446
 447                                 i8259: interrupt-controller@20 {
 448                                         interrupt-controller;
 449                                         device_type = "interrupt-controller";
 450                                         reg = <0x1 0x20 0x2
 451                                                0x1 0xa0 0x2
 452                                                0x1 0x4d0 0x2>;
 453                                         #address-cells = <0>;
 454                                         #interrupt-cells = <2>;
 455                                         compatible = "chrp,iic";
 456                                         interrupts = <0 1>;
 457                                         interrupt-parent = <&mpic>;
 458                                 };
 459
 460                                 rtc@70 {
 461                                         compatible = "pnpPNP,b00";
 462                                         reg = <0x1 0x70 0x2>;
 463                                 };
 464                         };
 465                 };
 466         };
 467
 468         pci1: pci@e0009000 {
 469                 cell-index = <1>;
 470                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 471                 interrupt-map = <
 472
 473                         /* IDSEL 0x15 */
 474                         0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
 475                         0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
 476                         0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
 477                         0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
 478
 479                 interrupt-parent = <&mpic>;
 480                 interrupts = <25 2>;
 481                 bus-range = <0 0>;
 482                 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
 483                           0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
 484                 clock-frequency = <66666666>;
 485                 #interrupt-cells = <1>;
 486                 #size-cells = <2>;
 487                 #address-cells = <3>;
 488                 reg = <0xe0009000 0x1000>;
 489                 compatible = "fsl,mpc8540-pci";
 490                 device_type = "pci";
 491         };
 492
 493         pci2: pcie@e000a000 {
 494                 cell-index = <2>;
 495                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 496                 interrupt-map = <
 497
 498                         /* IDSEL 0x0 (PEX) */
 499                         00000 0x0 0x0 0x1 &mpic 0x0 0x1
 500                         00000 0x0 0x0 0x2 &mpic 0x1 0x1
 501                         00000 0x0 0x0 0x3 &mpic 0x2 0x1
 502                         00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 503
 504                 interrupt-parent = <&mpic>;
 505                 interrupts = <26 2>;
 506                 bus-range = <0 255>;
 507                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
 508                           0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
 509                 clock-frequency = <33333333>;
 510                 #interrupt-cells = <1>;
 511                 #size-cells = <2>;
 512                 #address-cells = <3>;
 513                 reg = <0xe000a000 0x1000>;
 514                 compatible = "fsl,mpc8548-pcie";
 515                 device_type = "pci";
 516                 pcie@0 {
 517                         reg = <0x0 0x0 0x0 0x0 0x0>;
 518                         #size-cells = <2>;
 519                         #address-cells = <3>;
 520                         device_type = "pci";
 521                         ranges = <0x2000000 0x0 0xa0000000
 522                                   0x2000000 0x0 0xa0000000
 523                                   0x0 0x20000000
 524
 525                                   0x1000000 0x0 0x0
 526                                   0x1000000 0x0 0x0
 527                                   0x0 0x100000>;
 528                 };
 529         };
 530 };