arch/powerpc/boot/dts/mpc8548cds.dts

   1 /*
   2  * MPC8548 CDS Device Tree Source
   3  *
   4  * Copyright 2006, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8548CDS";
  16         compatible = "MPC8548CDS", "MPC85xxCDS";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23 /*
  24                 ethernet2 = &enet2;
  25                 ethernet3 = &enet3;
  26 */
  27                 serial0 = &serial0;
  28                 serial1 = &serial1;
  29                 pci0 = &pci0;
  30                 pci1 = &pci1;
  31                 pci2 = &pci2;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 PowerPC,8548@0 {
  39                         device_type = "cpu";
  40                         reg = <0x0>;
  41                         d-cache-line-size = <32>;       // 32 bytes
  42                         i-cache-line-size = <32>;       // 32 bytes
  43                         d-cache-size = <0x8000>;                // L1, 32K
  44                         i-cache-size = <0x8000>;                // L1, 32K
  45                         timebase-frequency = <0>;       //  33 MHz, from uboot
  46                         bus-frequency = <0>;    // 166 MHz
  47                         clock-frequency = <0>;  // 825 MHz, from uboot
  48                         next-level-cache = <&L2>;
  49                 };
  50         };
  51
  52         memory {
  53                 device_type = "memory";
  54                 reg = <0x0 0x8000000>;  // 128M at 0x0
  55         };
  56
  57         soc8548@e0000000 {
  58                 #address-cells = <1>;
  59                 #size-cells = <1>;
  60                 device_type = "soc";
  61                 compatible = "simple-bus";
  62                 ranges = <0x0 0xe0000000 0x100000>;
  63                 bus-frequency = <0>;
  64
  65                 ecm-law@0 {
  66                         compatible = "fsl,ecm-law";
  67                         reg = <0x0 0x1000>;
  68                         fsl,num-laws = <10>;
  69                 };
  70
  71                 ecm@1000 {
  72                         compatible = "fsl,mpc8548-ecm", "fsl,ecm";
  73                         reg = <0x1000 0x1000>;
  74                         interrupts = <17 2>;
  75                         interrupt-parent = <&mpic>;
  76                 };
  77
  78                 memory-controller@2000 {
  79                         compatible = "fsl,8548-memory-controller";
  80                         reg = <0x2000 0x1000>;
  81                         interrupt-parent = <&mpic>;
  82                         interrupts = <18 2>;
  83                 };
  84
  85                 L2: l2-cache-controller@20000 {
  86                         compatible = "fsl,8548-l2-cache-controller";
  87                         reg = <0x20000 0x1000>;
  88                         cache-line-size = <32>; // 32 bytes
  89                         cache-size = <0x80000>; // L2, 512K
  90                         interrupt-parent = <&mpic>;
  91                         interrupts = <16 2>;
  92                 };
  93
  94                 i2c@3000 {
  95                         #address-cells = <1>;
  96                         #size-cells = <0>;
  97                         cell-index = <0>;
  98                         compatible = "fsl-i2c";
  99                         reg = <0x3000 0x100>;
 100                         interrupts = <43 2>;
 101                         interrupt-parent = <&mpic>;
 102                         dfsrr;
 103                 };
 104
 105                 i2c@3100 {
 106                         #address-cells = <1>;
 107                         #size-cells = <0>;
 108                         cell-index = <1>;
 109                         compatible = "fsl-i2c";
 110                         reg = <0x3100 0x100>;
 111                         interrupts = <43 2>;
 112                         interrupt-parent = <&mpic>;
 113                         dfsrr;
 114                 };
 115
 116                 dma@21300 {
 117                         #address-cells = <1>;
 118                         #size-cells = <1>;
 119                         compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
 120                         reg = <0x21300 0x4>;
 121                         ranges = <0x0 0x21100 0x200>;
 122                         cell-index = <0>;
 123                         dma-channel@0 {
 124                                 compatible = "fsl,mpc8548-dma-channel",
 125                                                 "fsl,eloplus-dma-channel";
 126                                 reg = <0x0 0x80>;
 127                                 cell-index = <0>;
 128                                 interrupt-parent = <&mpic>;
 129                                 interrupts = <20 2>;
 130                         };
 131                         dma-channel@80 {
 132                                 compatible = "fsl,mpc8548-dma-channel",
 133                                                 "fsl,eloplus-dma-channel";
 134                                 reg = <0x80 0x80>;
 135                                 cell-index = <1>;
 136                                 interrupt-parent = <&mpic>;
 137                                 interrupts = <21 2>;
 138                         };
 139                         dma-channel@100 {
 140                                 compatible = "fsl,mpc8548-dma-channel",
 141                                                 "fsl,eloplus-dma-channel";
 142                                 reg = <0x100 0x80>;
 143                                 cell-index = <2>;
 144                                 interrupt-parent = <&mpic>;
 145                                 interrupts = <22 2>;
 146                         };
 147                         dma-channel@180 {
 148                                 compatible = "fsl,mpc8548-dma-channel",
 149                                                 "fsl,eloplus-dma-channel";
 150                                 reg = <0x180 0x80>;
 151                                 cell-index = <3>;
 152                                 interrupt-parent = <&mpic>;
 153                                 interrupts = <23 2>;
 154                         };
 155                 };
 156
 157                 enet0: ethernet@24000 {
 158                         #address-cells = <1>;
 159                         #size-cells = <1>;
 160                         cell-index = <0>;
 161                         device_type = "network";
 162                         model = "eTSEC";
 163                         compatible = "gianfar";
 164                         reg = <0x24000 0x1000>;
 165                         ranges = <0x0 0x24000 0x1000>;
 166                         local-mac-address = [ 00 00 00 00 00 00 ];
 167                         interrupts = <29 2 30 2 34 2>;
 168                         interrupt-parent = <&mpic>;
 169                         tbi-handle = <&tbi0>;
 170                         phy-handle = <&phy0>;
 171
 172                         mdio@520 {
 173                                 #address-cells = <1>;
 174                                 #size-cells = <0>;
 175                                 compatible = "fsl,gianfar-mdio";
 176                                 reg = <0x520 0x20>;
 177
 178                                 phy0: ethernet-phy@0 {
 179                                         interrupt-parent = <&mpic>;
 180                                         interrupts = <5 1>;
 181                                         reg = <0x0>;
 182                                         device_type = "ethernet-phy";
 183                                 };
 184                                 phy1: ethernet-phy@1 {
 185                                         interrupt-parent = <&mpic>;
 186                                         interrupts = <5 1>;
 187                                         reg = <0x1>;
 188                                         device_type = "ethernet-phy";
 189                                 };
 190                                 phy2: ethernet-phy@2 {
 191                                         interrupt-parent = <&mpic>;
 192                                         interrupts = <5 1>;
 193                                         reg = <0x2>;
 194                                         device_type = "ethernet-phy";
 195                                 };
 196                                 phy3: ethernet-phy@3 {
 197                                         interrupt-parent = <&mpic>;
 198                                         interrupts = <5 1>;
 199                                         reg = <0x3>;
 200                                         device_type = "ethernet-phy";
 201                                 };
 202                                 tbi0: tbi-phy@11 {
 203                                         reg = <0x11>;
 204                                         device_type = "tbi-phy";
 205                                 };
 206                         };
 207                 };
 208
 209                 enet1: ethernet@25000 {
 210                         #address-cells = <1>;
 211                         #size-cells = <1>;
 212                         cell-index = <1>;
 213                         device_type = "network";
 214                         model = "eTSEC";
 215                         compatible = "gianfar";
 216                         reg = <0x25000 0x1000>;
 217                         ranges = <0x0 0x25000 0x1000>;
 218                         local-mac-address = [ 00 00 00 00 00 00 ];
 219                         interrupts = <35 2 36 2 40 2>;
 220                         interrupt-parent = <&mpic>;
 221                         tbi-handle = <&tbi1>;
 222                         phy-handle = <&phy1>;
 223
 224                         mdio@520 {
 225                                 #address-cells = <1>;
 226                                 #size-cells = <0>;
 227                                 compatible = "fsl,gianfar-tbi";
 228                                 reg = <0x520 0x20>;
 229
 230                                 tbi1: tbi-phy@11 {
 231                                         reg = <0x11>;
 232                                         device_type = "tbi-phy";
 233                                 };
 234                         };
 235                 };
 236
 237 /* eTSEC 3/4 are currently broken
 238                 enet2: ethernet@26000 {
 239                         #address-cells = <1>;
 240                         #size-cells = <1>;
 241                         cell-index = <2>;
 242                         device_type = "network";
 243                         model = "eTSEC";
 244                         compatible = "gianfar";
 245                         reg = <0x26000 0x1000>;
 246                         ranges = <0x0 0x26000 0x1000>;
 247                         local-mac-address = [ 00 00 00 00 00 00 ];
 248                         interrupts = <31 2 32 2 33 2>;
 249                         interrupt-parent = <&mpic>;
 250                         tbi-handle = <&tbi2>;
 251                         phy-handle = <&phy2>;
 252
 253                         mdio@520 {
 254                                 #address-cells = <1>;
 255                                 #size-cells = <0>;
 256                                 compatible = "fsl,gianfar-tbi";
 257                                 reg = <0x520 0x20>;
 258
 259                                 tbi2: tbi-phy@11 {
 260                                         reg = <0x11>;
 261                                         device_type = "tbi-phy";
 262                                 };
 263                         };
 264                 };
 265
 266                 enet3: ethernet@27000 {
 267                         #address-cells = <1>;
 268                         #size-cells = <1>;
 269                         cell-index = <3>;
 270                         device_type = "network";
 271                         model = "eTSEC";
 272                         compatible = "gianfar";
 273                         reg = <0x27000 0x1000>;
 274                         ranges = <0x0 0x27000 0x1000>;
 275                         local-mac-address = [ 00 00 00 00 00 00 ];
 276                         interrupts = <37 2 38 2 39 2>;
 277                         interrupt-parent = <&mpic>;
 278                         tbi-handle = <&tbi3>;
 279                         phy-handle = <&phy3>;
 280
 281                         mdio@520 {
 282                                 #address-cells = <1>;
 283                                 #size-cells = <0>;
 284                                 compatible = "fsl,gianfar-tbi";
 285                                 reg = <0x520 0x20>;
 286
 287                                 tbi3: tbi-phy@11 {
 288                                         reg = <0x11>;
 289                                         device_type = "tbi-phy";
 290                                 };
 291                         };
 292                 };
 293  */
 294
 295                 serial0: serial@4500 {
 296                         cell-index = <0>;
 297                         device_type = "serial";
 298                         compatible = "ns16550";
 299                         reg = <0x4500 0x100>;   // reg base, size
 300                         clock-frequency = <0>;  // should we fill in in uboot?
 301                         interrupts = <42 2>;
 302                         interrupt-parent = <&mpic>;
 303                 };
 304
 305                 serial1: serial@4600 {
 306                         cell-index = <1>;
 307                         device_type = "serial";
 308                         compatible = "ns16550";
 309                         reg = <0x4600 0x100>;   // reg base, size
 310                         clock-frequency = <0>;  // should we fill in in uboot?
 311                         interrupts = <42 2>;
 312                         interrupt-parent = <&mpic>;
 313                 };
 314
 315                 global-utilities@e0000 {        //global utilities reg
 316                         compatible = "fsl,mpc8548-guts";
 317                         reg = <0xe0000 0x1000>;
 318                         fsl,has-rstcr;
 319                 };
 320
 321                 crypto@30000 {
 322                         compatible = "fsl,sec2.1", "fsl,sec2.0";
 323                         reg = <0x30000 0x10000>;
 324                         interrupts = <45 2>;
 325                         interrupt-parent = <&mpic>;
 326                         fsl,num-channels = <4>;
 327                         fsl,channel-fifo-len = <24>;
 328                         fsl,exec-units-mask = <0xfe>;
 329                         fsl,descriptor-types-mask = <0x12b0ebf>;
 330                 };
 331
 332                 mpic: pic@40000 {
 333                         interrupt-controller;
 334                         #address-cells = <0>;
 335                         #interrupt-cells = <2>;
 336                         reg = <0x40000 0x40000>;
 337                         compatible = "chrp,open-pic";
 338                         device_type = "open-pic";
 339                 };
 340         };
 341
 342         pci0: pci@e0008000 {
 343                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 344                 interrupt-map = <
 345                         /* IDSEL 0x4 (PCIX Slot 2) */
 346                         0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
 347                         0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
 348                         0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
 349                         0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
 350
 351                         /* IDSEL 0x5 (PCIX Slot 3) */
 352                         0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
 353                         0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
 354                         0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
 355                         0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
 356
 357                         /* IDSEL 0x6 (PCIX Slot 4) */
 358                         0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
 359                         0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
 360                         0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
 361                         0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
 362
 363                         /* IDSEL 0x8 (PCIX Slot 5) */
 364                         0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
 365                         0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
 366                         0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
 367                         0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
 368
 369                         /* IDSEL 0xC (Tsi310 bridge) */
 370                         0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
 371                         0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
 372                         0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
 373                         0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
 374
 375                         /* IDSEL 0x14 (Slot 2) */
 376                         0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
 377                         0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
 378                         0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
 379                         0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
 380
 381                         /* IDSEL 0x15 (Slot 3) */
 382                         0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
 383                         0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
 384                         0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
 385                         0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
 386
 387                         /* IDSEL 0x16 (Slot 4) */
 388                         0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
 389                         0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
 390                         0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
 391                         0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
 392
 393                         /* IDSEL 0x18 (Slot 5) */
 394                         0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
 395                         0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
 396                         0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
 397                         0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
 398
 399                         /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
 400                         0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
 401                         0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
 402                         0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
 403                         0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 404
 405                 interrupt-parent = <&mpic>;
 406                 interrupts = <24 2>;
 407                 bus-range = <0 0>;
 408                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 409                           0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
 410                 clock-frequency = <66666666>;
 411                 #interrupt-cells = <1>;
 412                 #size-cells = <2>;
 413                 #address-cells = <3>;
 414                 reg = <0xe0008000 0x1000>;
 415                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
 416                 device_type = "pci";
 417
 418                 pci_bridge@1c {
 419                         interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 420                         interrupt-map = <
 421
 422                                 /* IDSEL 0x00 (PrPMC Site) */
 423                                 0000 0x0 0x0 0x1 &mpic 0x0 0x1
 424                                 0000 0x0 0x0 0x2 &mpic 0x1 0x1
 425                                 0000 0x0 0x0 0x3 &mpic 0x2 0x1
 426                                 0000 0x0 0x0 0x4 &mpic 0x3 0x1
 427
 428                                 /* IDSEL 0x04 (VIA chip) */
 429                                 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
 430                                 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
 431                                 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
 432                                 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
 433
 434                                 /* IDSEL 0x05 (8139) */
 435                                 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
 436
 437                                 /* IDSEL 0x06 (Slot 6) */
 438                                 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
 439                                 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
 440                                 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
 441                                 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
 442
 443                                 /* IDESL 0x07 (Slot 7) */
 444                                 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
 445                                 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
 446                                 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
 447                                 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
 448
 449                         reg = <0xe000 0x0 0x0 0x0 0x0>;
 450                         #interrupt-cells = <1>;
 451                         #size-cells = <2>;
 452                         #address-cells = <3>;
 453                         ranges = <0x2000000 0x0 0x80000000
 454                                   0x2000000 0x0 0x80000000
 455                                   0x0 0x20000000
 456                                   0x1000000 0x0 0x0
 457                                   0x1000000 0x0 0x0
 458                                   0x0 0x80000>;
 459                         clock-frequency = <33333333>;
 460
 461                         isa@4 {
 462                                 device_type = "isa";
 463                                 #interrupt-cells = <2>;
 464                                 #size-cells = <1>;
 465                                 #address-cells = <2>;
 466                                 reg = <0x2000 0x0 0x0 0x0 0x0>;
 467                                 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
 468                                 interrupt-parent = <&i8259>;
 469
 470                                 i8259: interrupt-controller@20 {
 471                                         interrupt-controller;
 472                                         device_type = "interrupt-controller";
 473                                         reg = <0x1 0x20 0x2
 474                                                0x1 0xa0 0x2
 475                                                0x1 0x4d0 0x2>;
 476                                         #address-cells = <0>;
 477                                         #interrupt-cells = <2>;
 478                                         compatible = "chrp,iic";
 479                                         interrupts = <0 1>;
 480                                         interrupt-parent = <&mpic>;
 481                                 };
 482
 483                                 rtc@70 {
 484                                         compatible = "pnpPNP,b00";
 485                                         reg = <0x1 0x70 0x2>;
 486                                 };
 487                         };
 488                 };
 489         };
 490
 491         pci1: pci@e0009000 {
 492                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 493                 interrupt-map = <
 494
 495                         /* IDSEL 0x15 */
 496                         0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
 497                         0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
 498                         0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
 499                         0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
 500
 501                 interrupt-parent = <&mpic>;
 502                 interrupts = <25 2>;
 503                 bus-range = <0 0>;
 504                 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
 505                           0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
 506                 clock-frequency = <66666666>;
 507                 #interrupt-cells = <1>;
 508                 #size-cells = <2>;
 509                 #address-cells = <3>;
 510                 reg = <0xe0009000 0x1000>;
 511                 compatible = "fsl,mpc8540-pci";
 512                 device_type = "pci";
 513         };
 514
 515         pci2: pcie@e000a000 {
 516                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 517                 interrupt-map = <
 518
 519                         /* IDSEL 0x0 (PEX) */
 520                         00000 0x0 0x0 0x1 &mpic 0x0 0x1
 521                         00000 0x0 0x0 0x2 &mpic 0x1 0x1
 522                         00000 0x0 0x0 0x3 &mpic 0x2 0x1
 523                         00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 524
 525                 interrupt-parent = <&mpic>;
 526                 interrupts = <26 2>;
 527                 bus-range = <0 255>;
 528                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
 529                           0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
 530                 clock-frequency = <33333333>;
 531                 #interrupt-cells = <1>;
 532                 #size-cells = <2>;
 533                 #address-cells = <3>;
 534                 reg = <0xe000a000 0x1000>;
 535                 compatible = "fsl,mpc8548-pcie";
 536                 device_type = "pci";
 537                 pcie@0 {
 538                         reg = <0x0 0x0 0x0 0x0 0x0>;
 539                         #size-cells = <2>;
 540                         #address-cells = <3>;
 541                         device_type = "pci";
 542                         ranges = <0x2000000 0x0 0xa0000000
 543                                   0x2000000 0x0 0xa0000000
 544                                   0x0 0x20000000
 545
 546                                   0x1000000 0x0 0x0
 547                                   0x1000000 0x0 0x0
 548                                   0x0 0x100000>;
 549                 };
 550         };
 551 };