arch/powerpc/boot/dts/mpc8544ds.dts

   1 /*
   2  * MPC8544 DS Device Tree Source
   3  *
   4  * Copyright 2007 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 / {
  13         model = "MPC8544DS";
  14         compatible = "MPC8544DS", "MPC85xxDS";
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         cpus {
  19                 #cpus = <1>;
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 PowerPC,8544@0 {
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         d-cache-line-size = <20>;       // 32 bytes
  27                         i-cache-line-size = <20>;       // 32 bytes
  28                         d-cache-size = <8000>;          // L1, 32K
  29                         i-cache-size = <8000>;          // L1, 32K
  30                         timebase-frequency = <0>;
  31                         bus-frequency = <0>;
  32                         clock-frequency = <0>;
  33                         32-bit;
  34                 };
  35         };
  36
  37         memory {
  38                 device_type = "memory";
  39                 reg = <00000000 00000000>;      // Filled by U-Boot
  40         };
  41
  42         soc8544@e0000000 {
  43                 #address-cells = <1>;
  44                 #size-cells = <1>;
  45                 #interrupt-cells = <2>;
  46                 device_type = "soc";
  47
  48
  49                 ranges = <00001000 e0001000 000ff000
  50                           80000000 80000000 20000000
  51                           a0000000 a0000000 10000000
  52                           b0000000 b0000000 00100000
  53                           c0000000 c0000000 20000000
  54                           b0100000 b0100000 00100000
  55                           e1000000 e1000000 00010000
  56                           e1010000 e1010000 00010000
  57                           e1020000 e1020000 00010000>;
  58                 reg = <e0000000 00001000>;      // CCSRBAR 1M
  59                 bus-frequency = <0>;            // Filled out by uboot.
  60
  61                 memory-controller@2000 {
  62                         compatible = "fsl,8544-memory-controller";
  63                         reg = <2000 1000>;
  64                         interrupt-parent = <&mpic>;
  65                         interrupts = <12 2>;
  66                 };
  67
  68                 l2-cache-controller@20000 {
  69                         compatible = "fsl,8544-l2-cache-controller";
  70                         reg = <20000 1000>;
  71                         cache-line-size = <20>; // 32 bytes
  72                         cache-size = <40000>;   // L2, 256K
  73                         interrupt-parent = <&mpic>;
  74                         interrupts = <10 2>;
  75                 };
  76
  77                 i2c@3000 {
  78                         device_type = "i2c";
  79                         compatible = "fsl-i2c";
  80                         reg = <3000 100>;
  81                         interrupts = <2b 2>;
  82                         interrupt-parent = <&mpic>;
  83                         dfsrr;
  84                 };
  85
  86                 mdio@24520 {
  87                         #address-cells = <1>;
  88                         #size-cells = <0>;
  89                         device_type = "mdio";
  90                         compatible = "gianfar";
  91                         reg = <24520 20>;
  92                         phy0: ethernet-phy@0 {
  93                                 interrupt-parent = <&mpic>;
  94                                 interrupts = <a 1>;
  95                                 reg = <0>;
  96                                 device_type = "ethernet-phy";
  97                         };
  98                         phy1: ethernet-phy@1 {
  99                                 interrupt-parent = <&mpic>;
 100                                 interrupts = <a 1>;
 101                                 reg = <1>;
 102                                 device_type = "ethernet-phy";
 103                         };
 104                 };
 105
 106                 ethernet@24000 {
 107                         #address-cells = <1>;
 108                         #size-cells = <0>;
 109                         device_type = "network";
 110                         model = "TSEC";
 111                         compatible = "gianfar";
 112                         reg = <24000 1000>;
 113                         local-mac-address = [ 00 00 00 00 00 00 ];
 114                         interrupts = <1d 2 1e 2 22 2>;
 115                         interrupt-parent = <&mpic>;
 116                         phy-handle = <&phy0>;
 117                         phy-connection-type = "rgmii-id";
 118                 };
 119
 120                 ethernet@26000 {
 121                         #address-cells = <1>;
 122                         #size-cells = <0>;
 123                         device_type = "network";
 124                         model = "TSEC";
 125                         compatible = "gianfar";
 126                         reg = <26000 1000>;
 127                         local-mac-address = [ 00 00 00 00 00 00 ];
 128                         interrupts = <1f 2 20 2 21 2>;
 129                         interrupt-parent = <&mpic>;
 130                         phy-handle = <&phy1>;
 131                         phy-connection-type = "rgmii-id";
 132                 };
 133
 134                 serial@4500 {
 135                         device_type = "serial";
 136                         compatible = "ns16550";
 137                         reg = <4500 100>;
 138                         clock-frequency = <0>;
 139                         interrupts = <2a 2>;
 140                         interrupt-parent = <&mpic>;
 141                 };
 142
 143                 serial@4600 {
 144                         device_type = "serial";
 145                         compatible = "ns16550";
 146                         reg = <4600 100>;
 147                         clock-frequency = <0>;
 148                         interrupts = <2a 2>;
 149                         interrupt-parent = <&mpic>;
 150                 };
 151
 152                 pci@8000 {
 153                         compatible = "fsl,mpc8540-pci";
 154                         device_type = "pci";
 155                         interrupt-map-mask = <f800 0 0 7>;
 156                         interrupt-map = <
 157
 158                                 /* IDSEL 0x11 J17 Slot 1 */
 159                                 8800 0 0 1 &mpic 2 1
 160                                 8800 0 0 2 &mpic 3 1
 161                                 8800 0 0 3 &mpic 4 1
 162                                 8800 0 0 4 &mpic 1 1
 163
 164                                 /* IDSEL 0x12 J16 Slot 2 */
 165
 166                                 9000 0 0 1 &mpic 3 1
 167                                 9000 0 0 2 &mpic 4 1
 168                                 9000 0 0 3 &mpic 2 1
 169                                 9000 0 0 4 &mpic 1 1>;
 170
 171                         interrupt-parent = <&mpic>;
 172                         interrupts = <18 2>;
 173                         bus-range = <0 ff>;
 174                         ranges = <02000000 0 c0000000 c0000000 0 20000000
 175                                   01000000 0 00000000 e1000000 0 00010000>;
 176                         clock-frequency = <3f940aa>;
 177                         #interrupt-cells = <1>;
 178                         #size-cells = <2>;
 179                         #address-cells = <3>;
 180                         reg = <8000 1000>;
 181                 };
 182
 183                 pcie@9000 {
 184                         compatible = "fsl,mpc8548-pcie";
 185                         device_type = "pci";
 186                         #interrupt-cells = <1>;
 187                         #size-cells = <2>;
 188                         #address-cells = <3>;
 189                         reg = <9000 1000>;
 190                         bus-range = <0 ff>;
 191                         ranges = <02000000 0 80000000 80000000 0 20000000
 192                                   01000000 0 00000000 e1010000 0 00010000>;
 193                         clock-frequency = <1fca055>;
 194                         interrupt-parent = <&mpic>;
 195                         interrupts = <1a 2>;
 196                         interrupt-map-mask = <f800 0 0 7>;
 197                         interrupt-map = <
 198                                 /* IDSEL 0x0 */
 199                                 0000 0 0 1 &mpic 4 1
 200                                 0000 0 0 2 &mpic 5 1
 201                                 0000 0 0 3 &mpic 6 1
 202                                 0000 0 0 4 &mpic 7 1
 203                                 >;
 204                 };
 205
 206                 pcie@a000 {
 207                         compatible = "fsl,mpc8548-pcie";
 208                         device_type = "pci";
 209                         #interrupt-cells = <1>;
 210                         #size-cells = <2>;
 211                         #address-cells = <3>;
 212                         reg = <a000 1000>;
 213                         bus-range = <0 ff>;
 214                         ranges = <02000000 0 a0000000 a0000000 0 10000000
 215                                   01000000 0 00000000 e1020000 0 00010000>;
 216                         clock-frequency = <1fca055>;
 217                         interrupt-parent = <&mpic>;
 218                         interrupts = <19 2>;
 219                         interrupt-map-mask = <f800 0 0 7>;
 220                         interrupt-map = <
 221                                 /* IDSEL 0x0 */
 222                                 0000 0 0 1 &mpic 0 1
 223                                 0000 0 0 2 &mpic 1 1
 224                                 0000 0 0 3 &mpic 2 1
 225                                 0000 0 0 4 &mpic 3 1
 226                                 >;
 227                 };
 228
 229                 pcie@b000 {
 230                         compatible = "fsl,mpc8548-pcie";
 231                         device_type = "pci";
 232                         #interrupt-cells = <1>;
 233                         #size-cells = <2>;
 234                         #address-cells = <3>;
 235                         reg = <b000 1000>;
 236                         bus-range = <0 ff>;
 237                         ranges = <02000000 0 b0000000 b0000000 0 00100000
 238                                   01000000 0 00000000 b0100000 0 00100000>;
 239                         clock-frequency = <1fca055>;
 240                         interrupt-parent = <&mpic>;
 241                         interrupts = <1b 2>;
 242                         interrupt-map-mask = <fb00 0 0 0>;
 243                         interrupt-map = <
 244                                 // IDSEL 0x1c  USB
 245                                 e000 0 0 0 &i8259 c 2
 246                                 e100 0 0 0 &i8259 9 2
 247                                 e200 0 0 0 &i8259 a 2
 248                                 e300 0 0 0 &i8259 b 2
 249
 250                                 // IDSEL 0x1d  Audio
 251                                 e800 0 0 0 &i8259 6 2
 252
 253                                 // IDSEL 0x1e Legacy
 254                                 f000 0 0 0 &i8259 7 2
 255                                 f100 0 0 0 &i8259 7 2
 256
 257                                 // IDSEL 0x1f IDE/SATA
 258                                 f800 0 0 0 &i8259 e 2
 259                                 f900 0 0 0 &i8259 5 2
 260                         >;
 261                         uli1575@0 {
 262                                 reg = <0 0 0 0 0>;
 263                                 #size-cells = <2>;
 264                                 #address-cells = <3>;
 265                                 ranges = <02000000 0 b0000000
 266                                           02000000 0 b0000000
 267                                           0 00100000
 268                                           01000000 0 00000000
 269                                           01000000 0 00000000
 270                                           0 00100000>;
 271
 272                                 pci_bridge@0 {
 273                                         reg = <0 0 0 0 0>;
 274                                         #size-cells = <2>;
 275                                         #address-cells = <3>;
 276                                         ranges = <02000000 0 b0000000
 277                                                   02000000 0 b0000000
 278                                                   0 00100000
 279                                                   01000000 0 00000000
 280                                                   01000000 0 00000000
 281                                                   0 00100000>;
 282
 283                                         isa@1e {
 284                                                 device_type = "isa";
 285                                                 #interrupt-cells = <2>;
 286                                                 #size-cells = <1>;
 287                                                 #address-cells = <2>;
 288                                                 reg = <f000 0 0 0 0>;
 289                                                 ranges = <1 0
 290                                                           01000000 0 0
 291                                                           00001000>;
 292                                                 interrupt-parent = <&i8259>;
 293
 294                                                 i8259: interrupt-controller@20 {
 295                                                         reg = <1 20 2
 296                                                                1 a0 2
 297                                                                1 4d0 2>;
 298                                                         clock-frequency = <0>;
 299                                                         interrupt-controller;
 300                                                         device_type = "interrupt-controller";
 301                                                         #address-cells = <0>;
 302                                                         #interrupt-cells = <2>;
 303                                                         built-in;
 304                                                         compatible = "chrp,iic";
 305                                                         interrupts = <9 2>;
 306                                                         interrupt-parent = <&mpic>;
 307                                                 };
 308
 309                                                 i8042@60 {
 310                                                         #size-cells = <0>;
 311                                                         #address-cells = <1>;
 312                                                         reg = <1 60 1 1 64 1>;
 313                                                         interrupts = <1 3 c 3>;
 314                                                         interrupt-parent = <&i8259>;
 315
 316                                                         keyboard@0 {
 317                                                                 reg = <0>;
 318                                                                 compatible = "pnpPNP,303";
 319                                                         };
 320
 321                                                         mouse@1 {
 322                                                                 reg = <1>;
 323                                                                 compatible = "pnpPNP,f03";
 324                                                         };
 325                                                 };
 326
 327                                                 rtc@70 {
 328                                                         compatible = "pnpPNP,b00";
 329                                                         reg = <1 70 2>;
 330                                                 };
 331
 332                                                 gpio@400 {
 333                                                         reg = <1 400 80>;
 334                                                 };
 335                                         };
 336                                 };
 337                         };
 338
 339                 };
 340
 341                 global-utilities@e0000 {        //global utilities block
 342                         compatible = "fsl,mpc8548-guts";
 343                         reg = <e0000 1000>;
 344                         fsl,has-rstcr;
 345                 };
 346
 347                 mpic: pic@40000 {
 348                         clock-frequency = <0>;
 349                         interrupt-controller;
 350                         #address-cells = <0>;
 351                         #interrupt-cells = <2>;
 352                         reg = <40000 40000>;
 353                         built-in;
 354                         compatible = "chrp,open-pic";
 355                         device_type = "open-pic";
 356                         big-endian;
 357                 };
 358         };
 359 };