arch/powerpc/boot/dts/mpc8540ads.dts

   1 /*
   2  * MPC8540 ADS Device Tree Source
   3  *
   4  * Copyright 2006 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12
  13 / {
  14         model = "MPC8540ADS";
  15         compatible = "MPC8540ADS", "MPC85xxADS";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 PowerPC,8540@0 {
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         d-cache-line-size = <20>;       // 32 bytes
  27                         i-cache-line-size = <20>;       // 32 bytes
  28                         d-cache-size = <8000>;          // L1, 32K
  29                         i-cache-size = <8000>;          // L1, 32K
  30                         timebase-frequency = <0>;       //  33 MHz, from uboot
  31                         bus-frequency = <0>;    // 166 MHz
  32                         clock-frequency = <0>;  // 825 MHz, from uboot
  33                         32-bit;
  34                 };
  35         };
  36
  37         memory {
  38                 device_type = "memory";
  39                 reg = <00000000 08000000>;      // 128M at 0x0
  40         };
  41
  42         soc8540@e0000000 {
  43                 #address-cells = <1>;
  44                 #size-cells = <1>;
  45                 #interrupt-cells = <2>;
  46                 device_type = "soc";
  47                 ranges = <0 e0000000 00100000>;
  48                 reg = <e0000000 00100000>;      // CCSRBAR 1M
  49                 bus-frequency = <0>;
  50
  51                 memory-controller@2000 {
  52                         compatible = "fsl,8540-memory-controller";
  53                         reg = <2000 1000>;
  54                         interrupt-parent = <&mpic>;
  55                         interrupts = <2 2>;
  56                 };
  57
  58                 l2-cache-controller@20000 {
  59                         compatible = "fsl,8540-l2-cache-controller";
  60                         reg = <20000 1000>;
  61                         cache-line-size = <20>; // 32 bytes
  62                         cache-size = <40000>;   // L2, 256K
  63                         interrupt-parent = <&mpic>;
  64                         interrupts = <0 2>;
  65                 };
  66
  67                 i2c@3000 {
  68                         device_type = "i2c";
  69                         compatible = "fsl-i2c";
  70                         reg = <3000 100>;
  71                         interrupts = <1b 2>;
  72                         interrupt-parent = <&mpic>;
  73                         dfsrr;
  74                 };
  75
  76                 mdio@24520 {
  77                         #address-cells = <1>;
  78                         #size-cells = <0>;
  79                         device_type = "mdio";
  80                         compatible = "gianfar";
  81                         reg = <24520 20>;
  82                         phy0: ethernet-phy@0 {
  83                                 interrupt-parent = <&mpic>;
  84                                 interrupts = <35 1>;
  85                                 reg = <0>;
  86                                 device_type = "ethernet-phy";
  87                         };
  88                         phy1: ethernet-phy@1 {
  89                                 interrupt-parent = <&mpic>;
  90                                 interrupts = <35 1>;
  91                                 reg = <1>;
  92                                 device_type = "ethernet-phy";
  93                         };
  94                         phy3: ethernet-phy@3 {
  95                                 interrupt-parent = <&mpic>;
  96                                 interrupts = <37 1>;
  97                                 reg = <3>;
  98                                 device_type = "ethernet-phy";
  99                         };
 100                 };
 101
 102                 ethernet@24000 {
 103                         #address-cells = <1>;
 104                         #size-cells = <0>;
 105                         device_type = "network";
 106                         model = "TSEC";
 107                         compatible = "gianfar";
 108                         reg = <24000 1000>;
 109                         address = [ 00 E0 0C 00 73 00 ];
 110                         local-mac-address = [ 00 E0 0C 00 73 00 ];
 111                         interrupts = <d 2 e 2 12 2>;
 112                         interrupt-parent = <&mpic>;
 113                         phy-handle = <&phy0>;
 114                 };
 115
 116                 ethernet@25000 {
 117                         #address-cells = <1>;
 118                         #size-cells = <0>;
 119                         device_type = "network";
 120                         model = "TSEC";
 121                         compatible = "gianfar";
 122                         reg = <25000 1000>;
 123                         address = [ 00 E0 0C 00 73 01 ];
 124                         local-mac-address = [ 00 E0 0C 00 73 01 ];
 125                         interrupts = <13 2 14 2 18 2>;
 126                         interrupt-parent = <&mpic>;
 127                         phy-handle = <&phy1>;
 128                 };
 129
 130                 ethernet@26000 {
 131                         #address-cells = <1>;
 132                         #size-cells = <0>;
 133                         device_type = "network";
 134                         model = "FEC";
 135                         compatible = "gianfar";
 136                         reg = <26000 1000>;
 137                         address = [ 00 E0 0C 00 73 02 ];
 138                         local-mac-address = [ 00 E0 0C 00 73 02 ];
 139                         interrupts = <19 2>;
 140                         interrupt-parent = <&mpic>;
 141                         phy-handle = <&phy3>;
 142                 };
 143
 144                 serial@4500 {
 145                         device_type = "serial";
 146                         compatible = "ns16550";
 147                         reg = <4500 100>;       // reg base, size
 148                         clock-frequency = <0>;  // should we fill in in uboot?
 149                         interrupts = <1a 2>;
 150                         interrupt-parent = <&mpic>;
 151                 };
 152
 153                 serial@4600 {
 154                         device_type = "serial";
 155                         compatible = "ns16550";
 156                         reg = <4600 100>;       // reg base, size
 157                         clock-frequency = <0>;  // should we fill in in uboot?
 158                         interrupts = <1a 2>;
 159                         interrupt-parent = <&mpic>;
 160                 };
 161                 pci@8000 {
 162                         interrupt-map-mask = <f800 0 0 7>;
 163                         interrupt-map = <
 164
 165                                 /* IDSEL 0x02 */
 166                                 1000 0 0 1 &mpic 31 1
 167                                 1000 0 0 2 &mpic 32 1
 168                                 1000 0 0 3 &mpic 33 1
 169                                 1000 0 0 4 &mpic 34 1
 170
 171                                 /* IDSEL 0x03 */
 172                                 1800 0 0 1 &mpic 34 1
 173                                 1800 0 0 2 &mpic 31 1
 174                                 1800 0 0 3 &mpic 32 1
 175                                 1800 0 0 4 &mpic 33 1
 176
 177                                 /* IDSEL 0x04 */
 178                                 2000 0 0 1 &mpic 33 1
 179                                 2000 0 0 2 &mpic 34 1
 180                                 2000 0 0 3 &mpic 31 1
 181                                 2000 0 0 4 &mpic 32 1
 182
 183                                 /* IDSEL 0x05 */
 184                                 2800 0 0 1 &mpic 32 1
 185                                 2800 0 0 2 &mpic 33 1
 186                                 2800 0 0 3 &mpic 34 1
 187                                 2800 0 0 4 &mpic 31 1
 188
 189                                 /* IDSEL 0x0c */
 190                                 6000 0 0 1 &mpic 31 1
 191                                 6000 0 0 2 &mpic 32 1
 192                                 6000 0 0 3 &mpic 33 1
 193                                 6000 0 0 4 &mpic 34 1
 194
 195                                 /* IDSEL 0x0d */
 196                                 6800 0 0 1 &mpic 34 1
 197                                 6800 0 0 2 &mpic 31 1
 198                                 6800 0 0 3 &mpic 32 1
 199                                 6800 0 0 4 &mpic 33 1
 200
 201                                 /* IDSEL 0x0e */
 202                                 7000 0 0 1 &mpic 33 1
 203                                 7000 0 0 2 &mpic 34 1
 204                                 7000 0 0 3 &mpic 31 1
 205                                 7000 0 0 4 &mpic 32 1
 206
 207                                 /* IDSEL 0x0f */
 208                                 7800 0 0 1 &mpic 32 1
 209                                 7800 0 0 2 &mpic 33 1
 210                                 7800 0 0 3 &mpic 34 1
 211                                 7800 0 0 4 &mpic 31 1
 212
 213                                 /* IDSEL 0x12 */
 214                                 9000 0 0 1 &mpic 31 1
 215                                 9000 0 0 2 &mpic 32 1
 216                                 9000 0 0 3 &mpic 33 1
 217                                 9000 0 0 4 &mpic 34 1
 218
 219                                 /* IDSEL 0x13 */
 220                                 9800 0 0 1 &mpic 34 1
 221                                 9800 0 0 2 &mpic 31 1
 222                                 9800 0 0 3 &mpic 32 1
 223                                 9800 0 0 4 &mpic 33 1
 224
 225                                 /* IDSEL 0x14 */
 226                                 a000 0 0 1 &mpic 33 1
 227                                 a000 0 0 2 &mpic 34 1
 228                                 a000 0 0 3 &mpic 31 1
 229                                 a000 0 0 4 &mpic 32 1
 230
 231                                 /* IDSEL 0x15 */
 232                                 a800 0 0 1 &mpic 32 1
 233                                 a800 0 0 2 &mpic 33 1
 234                                 a800 0 0 3 &mpic 34 1
 235                                 a800 0 0 4 &mpic 31 1>;
 236                         interrupt-parent = <&mpic>;
 237                         interrupts = <08 2>;
 238                         bus-range = <0 0>;
 239                         ranges = <02000000 0 80000000 80000000 0 20000000
 240                                   01000000 0 00000000 e2000000 0 00100000>;
 241                         clock-frequency = <3f940aa>;
 242                         #interrupt-cells = <1>;
 243                         #size-cells = <2>;
 244                         #address-cells = <3>;
 245                         reg = <8000 1000>;
 246                         compatible = "85xx";
 247                         device_type = "pci";
 248                 };
 249
 250                 mpic: pic@40000 {
 251                         clock-frequency = <0>;
 252                         interrupt-controller;
 253                         #address-cells = <0>;
 254                         #interrupt-cells = <2>;
 255                         reg = <40000 40000>;
 256                         built-in;
 257                         compatible = "chrp,open-pic";
 258                         device_type = "open-pic";
 259                         big-endian;
 260                 };
 261         };
 262 };