arch/powerpc/boot/dts/mpc8540ads.dts

   1 /*
   2  * MPC8540 ADS Device Tree Source
   3  *
   4  * Copyright 2006, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8540ADS";
  16         compatible = "MPC8540ADS", "MPC85xxADS";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23                 ethernet2 = &enet2;
  24                 serial0 = &serial0;
  25                 serial1 = &serial1;
  26                 pci0 = &pci0;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 PowerPC,8540@0 {
  34                         device_type = "cpu";
  35                         reg = <0x0>;
  36                         d-cache-line-size = <32>;       // 32 bytes
  37                         i-cache-line-size = <32>;       // 32 bytes
  38                         d-cache-size = <0x8000>;                // L1, 32K
  39                         i-cache-size = <0x8000>;                // L1, 32K
  40                         timebase-frequency = <0>;       //  33 MHz, from uboot
  41                         bus-frequency = <0>;    // 166 MHz
  42                         clock-frequency = <0>;  // 825 MHz, from uboot
  43                 };
  44         };
  45
  46         memory {
  47                 device_type = "memory";
  48                 reg = <0x0 0x8000000>;  // 128M at 0x0
  49         };
  50
  51         soc8540@e0000000 {
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 device_type = "soc";
  55                 ranges = <0x0 0xe0000000 0x100000>;
  56                 reg = <0xe0000000 0x100000>;    // CCSRBAR 1M
  57                 bus-frequency = <0>;
  58
  59                 memory-controller@2000 {
  60                         compatible = "fsl,8540-memory-controller";
  61                         reg = <0x2000 0x1000>;
  62                         interrupt-parent = <&mpic>;
  63                         interrupts = <18 2>;
  64                 };
  65
  66                 l2-cache-controller@20000 {
  67                         compatible = "fsl,8540-l2-cache-controller";
  68                         reg = <0x20000 0x1000>;
  69                         cache-line-size = <32>; // 32 bytes
  70                         cache-size = <0x40000>; // L2, 256K
  71                         interrupt-parent = <&mpic>;
  72                         interrupts = <16 2>;
  73                 };
  74
  75                 i2c@3000 {
  76                         #address-cells = <1>;
  77                         #size-cells = <0>;
  78                         cell-index = <0>;
  79                         compatible = "fsl-i2c";
  80                         reg = <0x3000 0x100>;
  81                         interrupts = <43 2>;
  82                         interrupt-parent = <&mpic>;
  83                         dfsrr;
  84                 };
  85
  86                 mdio@24520 {
  87                         #address-cells = <1>;
  88                         #size-cells = <0>;
  89                         compatible = "fsl,gianfar-mdio";
  90                         reg = <0x24520 0x20>;
  91
  92                         phy0: ethernet-phy@0 {
  93                                 interrupt-parent = <&mpic>;
  94                                 interrupts = <5 1>;
  95                                 reg = <0x0>;
  96                                 device_type = "ethernet-phy";
  97                         };
  98                         phy1: ethernet-phy@1 {
  99                                 interrupt-parent = <&mpic>;
 100                                 interrupts = <5 1>;
 101                                 reg = <0x1>;
 102                                 device_type = "ethernet-phy";
 103                         };
 104                         phy3: ethernet-phy@3 {
 105                                 interrupt-parent = <&mpic>;
 106                                 interrupts = <7 1>;
 107                                 reg = <0x3>;
 108                                 device_type = "ethernet-phy";
 109                         };
 110                 };
 111
 112                 enet0: ethernet@24000 {
 113                         cell-index = <0>;
 114                         device_type = "network";
 115                         model = "TSEC";
 116                         compatible = "gianfar";
 117                         reg = <0x24000 0x1000>;
 118                         local-mac-address = [ 00 00 00 00 00 00 ];
 119                         interrupts = <29 2 30 2 34 2>;
 120                         interrupt-parent = <&mpic>;
 121                         phy-handle = <&phy0>;
 122                 };
 123
 124                 enet1: ethernet@25000 {
 125                         cell-index = <1>;
 126                         device_type = "network";
 127                         model = "TSEC";
 128                         compatible = "gianfar";
 129                         reg = <0x25000 0x1000>;
 130                         local-mac-address = [ 00 00 00 00 00 00 ];
 131                         interrupts = <35 2 36 2 40 2>;
 132                         interrupt-parent = <&mpic>;
 133                         phy-handle = <&phy1>;
 134                 };
 135
 136                 enet2: ethernet@26000 {
 137                         cell-index = <2>;
 138                         device_type = "network";
 139                         model = "FEC";
 140                         compatible = "gianfar";
 141                         reg = <0x26000 0x1000>;
 142                         local-mac-address = [ 00 00 00 00 00 00 ];
 143                         interrupts = <41 2>;
 144                         interrupt-parent = <&mpic>;
 145                         phy-handle = <&phy3>;
 146                 };
 147
 148                 serial0: serial@4500 {
 149                         cell-index = <0>;
 150                         device_type = "serial";
 151                         compatible = "ns16550";
 152                         reg = <0x4500 0x100>;   // reg base, size
 153                         clock-frequency = <0>;  // should we fill in in uboot?
 154                         interrupts = <42 2>;
 155                         interrupt-parent = <&mpic>;
 156                 };
 157
 158                 serial1: serial@4600 {
 159                         cell-index = <1>;
 160                         device_type = "serial";
 161                         compatible = "ns16550";
 162                         reg = <0x4600 0x100>;   // reg base, size
 163                         clock-frequency = <0>;  // should we fill in in uboot?
 164                         interrupts = <42 2>;
 165                         interrupt-parent = <&mpic>;
 166                 };
 167                 mpic: pic@40000 {
 168                         clock-frequency = <0>;
 169                         interrupt-controller;
 170                         #address-cells = <0>;
 171                         #interrupt-cells = <2>;
 172                         reg = <0x40000 0x40000>;
 173                         compatible = "chrp,open-pic";
 174                         device_type = "open-pic";
 175                         big-endian;
 176                 };
 177         };
 178
 179         pci0: pci@e0008000 {
 180                 cell-index = <0>;
 181                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 182                 interrupt-map = <
 183
 184                         /* IDSEL 0x02 */
 185                         0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
 186                         0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
 187                         0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
 188                         0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
 189
 190                         /* IDSEL 0x03 */
 191                         0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
 192                         0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
 193                         0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
 194                         0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
 195
 196                         /* IDSEL 0x04 */
 197                         0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
 198                         0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
 199                         0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
 200                         0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
 201
 202                         /* IDSEL 0x05 */
 203                         0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
 204                         0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
 205                         0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
 206                         0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
 207
 208                         /* IDSEL 0x0c */
 209                         0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
 210                         0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
 211                         0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
 212                         0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
 213
 214                         /* IDSEL 0x0d */
 215                         0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
 216                         0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
 217                         0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
 218                         0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
 219
 220                         /* IDSEL 0x0e */
 221                         0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
 222                         0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
 223                         0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
 224                         0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
 225
 226                         /* IDSEL 0x0f */
 227                         0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
 228                         0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
 229                         0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
 230                         0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
 231
 232                         /* IDSEL 0x12 */
 233                         0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
 234                         0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
 235                         0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
 236                         0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
 237
 238                         /* IDSEL 0x13 */
 239                         0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
 240                         0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
 241                         0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
 242                         0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
 243
 244                         /* IDSEL 0x14 */
 245                         0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
 246                         0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
 247                         0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
 248                         0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
 249
 250                         /* IDSEL 0x15 */
 251                         0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
 252                         0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
 253                         0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
 254                         0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
 255                 interrupt-parent = <&mpic>;
 256                 interrupts = <24 2>;
 257                 bus-range = <0 0>;
 258                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 259                           0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
 260                 clock-frequency = <66666666>;
 261                 #interrupt-cells = <1>;
 262                 #size-cells = <2>;
 263                 #address-cells = <3>;
 264                 reg = <0xe0008000 0x1000>;
 265                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
 266                 device_type = "pci";
 267         };
 268 };