arch/powerpc/boot/dts/mpc8377_mds.dts

   1 /*
   2  * MPC8377E MDS Device Tree Source
   3  *
   4  * Copyright 2007 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "fsl,mpc8377emds";
  16         compatible = "fsl,mpc8377emds","fsl,mpc837xmds";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23                 serial0 = &serial0;
  24                 serial1 = &serial1;
  25                 pci0 = &pci0;
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 PowerPC,8377@0 {
  33                         device_type = "cpu";
  34                         reg = <0x0>;
  35                         d-cache-line-size = <32>;
  36                         i-cache-line-size = <32>;
  37                         d-cache-size = <32768>;
  38                         i-cache-size = <32768>;
  39                         timebase-frequency = <0>;
  40                         bus-frequency = <0>;
  41                         clock-frequency = <0>;
  42                 };
  43         };
  44
  45         memory {
  46                 device_type = "memory";
  47                 reg = <0x00000000 0x20000000>;  // 512MB at 0
  48         };
  49
  50         localbus@e0005000 {
  51                 #address-cells = <2>;
  52                 #size-cells = <1>;
  53                 compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
  54                 reg = <0xe0005000 0x1000>;
  55                 interrupts = <77 0x8>;
  56                 interrupt-parent = <&ipic>;
  57
  58                 // booting from NOR flash
  59                 ranges = <0 0x0 0xfe000000 0x02000000
  60                           1 0x0 0xf8000000 0x00008000
  61                           3 0x0 0xe0600000 0x00008000>;
  62
  63                 flash@0,0 {
  64                         #address-cells = <1>;
  65                         #size-cells = <1>;
  66                         compatible = "cfi-flash";
  67                         reg = <0 0x0 0x2000000>;
  68                         bank-width = <2>;
  69                         device-width = <1>;
  70
  71                         u-boot@0 {
  72                                 reg = <0x0 0x100000>;
  73                                 read-only;
  74                         };
  75
  76                         fs@100000 {
  77                                 reg = <0x100000 0x800000>;
  78                         };
  79
  80                         kernel@1d00000 {
  81                                 reg = <0x1d00000 0x200000>;
  82                         };
  83
  84                         dtb@1f00000 {
  85                                 reg = <0x1f00000 0x100000>;
  86                         };
  87                 };
  88
  89                 bcsr@1,0 {
  90                         reg = <1 0x0 0x8000>;
  91                         compatible = "fsl,mpc837xmds-bcsr";
  92                 };
  93
  94                 nand@3,0 {
  95                         #address-cells = <1>;
  96                         #size-cells = <1>;
  97                         compatible = "fsl,mpc8377-fcm-nand",
  98                                      "fsl,elbc-fcm-nand";
  99                         reg = <3 0x0 0x8000>;
 100
 101                         u-boot@0 {
 102                                 reg = <0x0 0x100000>;
 103                                 read-only;
 104                         };
 105
 106                         kernel@100000 {
 107                                 reg = <0x100000 0x300000>;
 108                         };
 109
 110                         fs@400000 {
 111                                 reg = <0x400000 0x1c00000>;
 112                         };
 113                 };
 114         };
 115
 116         soc@e0000000 {
 117                 #address-cells = <1>;
 118                 #size-cells = <1>;
 119                 device_type = "soc";
 120                 compatible = "simple-bus";
 121                 ranges = <0x0 0xe0000000 0x00100000>;
 122                 reg = <0xe0000000 0x00000200>;
 123                 bus-frequency = <0>;
 124
 125                 wdt@200 {
 126                         compatible = "mpc83xx_wdt";
 127                         reg = <0x200 0x100>;
 128                 };
 129
 130                 i2c@3000 {
 131                         #address-cells = <1>;
 132                         #size-cells = <0>;
 133                         cell-index = <0>;
 134                         compatible = "fsl-i2c";
 135                         reg = <0x3000 0x100>;
 136                         interrupts = <14 0x8>;
 137                         interrupt-parent = <&ipic>;
 138                         dfsrr;
 139
 140                         rtc@68 {
 141                                 compatible = "dallas,ds1374";
 142                                 reg = <0x68>;
 143                                 interrupts = <19 0x8>;
 144                                 interrupt-parent = <&ipic>;
 145                         };
 146                 };
 147
 148                 i2c@3100 {
 149                         #address-cells = <1>;
 150                         #size-cells = <0>;
 151                         cell-index = <1>;
 152                         compatible = "fsl-i2c";
 153                         reg = <0x3100 0x100>;
 154                         interrupts = <15 0x8>;
 155                         interrupt-parent = <&ipic>;
 156                         dfsrr;
 157                 };
 158
 159                 spi@7000 {
 160                         cell-index = <0>;
 161                         compatible = "fsl,spi";
 162                         reg = <0x7000 0x1000>;
 163                         interrupts = <16 0x8>;
 164                         interrupt-parent = <&ipic>;
 165                         mode = "cpu";
 166                 };
 167
 168                 usb@23000 {
 169                         compatible = "fsl-usb2-dr";
 170                         reg = <0x23000 0x1000>;
 171                         #address-cells = <1>;
 172                         #size-cells = <0>;
 173                         interrupt-parent = <&ipic>;
 174                         interrupts = <38 0x8>;
 175                         dr_mode = "host";
 176                         phy_type = "ulpi";
 177                 };
 178
 179                 mdio@24520 {
 180                         #address-cells = <1>;
 181                         #size-cells = <0>;
 182                         compatible = "fsl,gianfar-mdio";
 183                         reg = <0x24520 0x20>;
 184                         phy2: ethernet-phy@2 {
 185                                 interrupt-parent = <&ipic>;
 186                                 interrupts = <17 0x8>;
 187                                 reg = <0x2>;
 188                                 device_type = "ethernet-phy";
 189                         };
 190                         phy3: ethernet-phy@3 {
 191                                 interrupt-parent = <&ipic>;
 192                                 interrupts = <18 0x8>;
 193                                 reg = <0x3>;
 194                                 device_type = "ethernet-phy";
 195                         };
 196                         tbi0: tbi-phy@11 {
 197                                 reg = <0x11>;
 198                                 device_type = "tbi-phy";
 199                         };
 200                 };
 201
 202                 mdio@25520 {
 203                         #address-cells = <1>;
 204                         #size-cells = <0>;
 205                         compatible = "fsl,gianfar-tbi";
 206                         reg = <0x25520 0x20>;
 207
 208                         tbi1: tbi-phy@11 {
 209                                 reg = <0x11>;
 210                                 device_type = "tbi-phy";
 211                         };
 212                 };
 213
 214
 215                 enet0: ethernet@24000 {
 216                         cell-index = <0>;
 217                         device_type = "network";
 218                         model = "eTSEC";
 219                         compatible = "gianfar";
 220                         reg = <0x24000 0x1000>;
 221                         local-mac-address = [ 00 00 00 00 00 00 ];
 222                         interrupts = <32 0x8 33 0x8 34 0x8>;
 223                         phy-connection-type = "mii";
 224                         interrupt-parent = <&ipic>;
 225                         tbi-handle = <&tbi0>;
 226                         phy-handle = <&phy2>;
 227                 };
 228
 229                 enet1: ethernet@25000 {
 230                         cell-index = <1>;
 231                         device_type = "network";
 232                         model = "eTSEC";
 233                         compatible = "gianfar";
 234                         reg = <0x25000 0x1000>;
 235                         local-mac-address = [ 00 00 00 00 00 00 ];
 236                         interrupts = <35 0x8 36 0x8 37 0x8>;
 237                         phy-connection-type = "mii";
 238                         interrupt-parent = <&ipic>;
 239                         tbi-handle = <&tbi1>;
 240                         phy-handle = <&phy3>;
 241                 };
 242
 243                 serial0: serial@4500 {
 244                         cell-index = <0>;
 245                         device_type = "serial";
 246                         compatible = "ns16550";
 247                         reg = <0x4500 0x100>;
 248                         clock-frequency = <0>;
 249                         interrupts = <9 0x8>;
 250                         interrupt-parent = <&ipic>;
 251                 };
 252
 253                 serial1: serial@4600 {
 254                         cell-index = <1>;
 255                         device_type = "serial";
 256                         compatible = "ns16550";
 257                         reg = <0x4600 0x100>;
 258                         clock-frequency = <0>;
 259                         interrupts = <10 0x8>;
 260                         interrupt-parent = <&ipic>;
 261                 };
 262
 263                 dma@82a8 {
 264                         #address-cells = <1>;
 265                         #size-cells = <1>;
 266                         compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
 267                         reg = <0x82a8 4>;
 268                         ranges = <0 0x8100 0x1a8>;
 269                         interrupt-parent = <&ipic>;
 270                         interrupts = <0x47 8>;
 271                         cell-index = <0>;
 272                         dma-channel@0 {
 273                                 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
 274                                 reg = <0 0x80>;
 275                                 cell-index = <0>;
 276                                 interrupt-parent = <&ipic>;
 277                                 interrupts = <0x47 8>;
 278                         };
 279                         dma-channel@80 {
 280                                 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
 281                                 reg = <0x80 0x80>;
 282                                 cell-index = <1>;
 283                                 interrupt-parent = <&ipic>;
 284                                 interrupts = <0x47 8>;
 285                         };
 286                         dma-channel@100 {
 287                                 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
 288                                 reg = <0x100 0x80>;
 289                                 cell-index = <2>;
 290                                 interrupt-parent = <&ipic>;
 291                                 interrupts = <0x47 8>;
 292                         };
 293                         dma-channel@180 {
 294                                 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
 295                                 reg = <0x180 0x28>;
 296                                 cell-index = <3>;
 297                                 interrupt-parent = <&ipic>;
 298                                 interrupts = <0x47 8>;
 299                         };
 300                 };
 301
 302                 crypto@30000 {
 303                         compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
 304                                      "fsl,sec2.1", "fsl,sec2.0";
 305                         reg = <0x30000 0x10000>;
 306                         interrupts = <11 0x8>;
 307                         interrupt-parent = <&ipic>;
 308                         fsl,num-channels = <4>;
 309                         fsl,channel-fifo-len = <24>;
 310                         fsl,exec-units-mask = <0x9fe>;
 311                         fsl,descriptor-types-mask = <0x3ab0ebf>;
 312                 };
 313
 314                 sdhc@2e000 {
 315                         model = "eSDHC";
 316                         compatible = "fsl,esdhc";
 317                         reg = <0x2e000 0x1000>;
 318                         interrupts = <42 0x8>;
 319                         interrupt-parent = <&ipic>;
 320                 };
 321
 322                 sata@18000 {
 323                         compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
 324                         reg = <0x18000 0x1000>;
 325                         interrupts = <44 0x8>;
 326                         interrupt-parent = <&ipic>;
 327                 };
 328
 329                 sata@19000 {
 330                         compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
 331                         reg = <0x19000 0x1000>;
 332                         interrupts = <45 0x8>;
 333                         interrupt-parent = <&ipic>;
 334                 };
 335
 336                 /* IPIC
 337                  * interrupts cell = <intr #, sense>
 338                  * sense values match linux IORESOURCE_IRQ_* defines:
 339                  * sense == 8: Level, low assertion
 340                  * sense == 2: Edge, high-to-low change
 341                  */
 342                 ipic: pic@700 {
 343                         compatible = "fsl,ipic";
 344                         interrupt-controller;
 345                         #address-cells = <0>;
 346                         #interrupt-cells = <2>;
 347                         reg = <0x700 0x100>;
 348                 };
 349         };
 350
 351         pci0: pci@e0008500 {
 352                 cell-index = <0>;
 353                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 354                 interrupt-map = <
 355
 356                                 /* IDSEL 0x11 */
 357                                  0x8800 0x0 0x0 0x1 &ipic 20 0x8
 358                                  0x8800 0x0 0x0 0x2 &ipic 21 0x8
 359                                  0x8800 0x0 0x0 0x3 &ipic 22 0x8
 360                                  0x8800 0x0 0x0 0x4 &ipic 23 0x8
 361
 362                                 /* IDSEL 0x12 */
 363                                  0x9000 0x0 0x0 0x1 &ipic 22 0x8
 364                                  0x9000 0x0 0x0 0x2 &ipic 23 0x8
 365                                  0x9000 0x0 0x0 0x3 &ipic 20 0x8
 366                                  0x9000 0x0 0x0 0x4 &ipic 21 0x8
 367
 368                                 /* IDSEL 0x13 */
 369                                  0x9800 0x0 0x0 0x1 &ipic 23 0x8
 370                                  0x9800 0x0 0x0 0x2 &ipic 20 0x8
 371                                  0x9800 0x0 0x0 0x3 &ipic 21 0x8
 372                                  0x9800 0x0 0x0 0x4 &ipic 22 0x8
 373
 374                                 /* IDSEL 0x15 */
 375                                  0xa800 0x0 0x0 0x1 &ipic 20 0x8
 376                                  0xa800 0x0 0x0 0x2 &ipic 21 0x8
 377                                  0xa800 0x0 0x0 0x3 &ipic 22 0x8
 378                                  0xa800 0x0 0x0 0x4 &ipic 23 0x8
 379
 380                                 /* IDSEL 0x16 */
 381                                  0xb000 0x0 0x0 0x1 &ipic 23 0x8
 382                                  0xb000 0x0 0x0 0x2 &ipic 20 0x8
 383                                  0xb000 0x0 0x0 0x3 &ipic 21 0x8
 384                                  0xb000 0x0 0x0 0x4 &ipic 22 0x8
 385
 386                                 /* IDSEL 0x17 */
 387                                  0xb800 0x0 0x0 0x1 &ipic 22 0x8
 388                                  0xb800 0x0 0x0 0x2 &ipic 23 0x8
 389                                  0xb800 0x0 0x0 0x3 &ipic 20 0x8
 390                                  0xb800 0x0 0x0 0x4 &ipic 21 0x8
 391
 392                                 /* IDSEL 0x18 */
 393                                  0xc000 0x0 0x0 0x1 &ipic 21 0x8
 394                                  0xc000 0x0 0x0 0x2 &ipic 22 0x8
 395                                  0xc000 0x0 0x0 0x3 &ipic 23 0x8
 396                                  0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
 397                 interrupt-parent = <&ipic>;
 398                 interrupts = <66 0x8>;
 399                 bus-range = <0x0 0x0>;
 400                 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
 401                           0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 402                           0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
 403                 clock-frequency = <0>;
 404                 #interrupt-cells = <1>;
 405                 #size-cells = <2>;
 406                 #address-cells = <3>;
 407                 reg = <0xe0008500 0x100         /* internal registers */
 408                        0xe0008300 0x8>;         /* config space access registers */
 409                 compatible = "fsl,mpc8349-pci";
 410                 device_type = "pci";
 411         };
 412 };