arch/powerpc/boot/dts/mpc832x_rdb.dts

   1 /*
   2  * MPC832x RDB Device Tree Source
   3  *
   4  * Copyright 2007 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8323ERDB";
  16         compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23                 serial0 = &serial0;
  24                 serial1 = &serial1;
  25                 pci0 = &pci0;
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 PowerPC,8323@0 {
  33                         device_type = "cpu";
  34                         reg = <0x0>;
  35                         d-cache-line-size = <0x20>;     // 32 bytes
  36                         i-cache-line-size = <0x20>;     // 32 bytes
  37                         d-cache-size = <16384>; // L1, 16K
  38                         i-cache-size = <16384>; // L1, 16K
  39                         timebase-frequency = <0>;
  40                         bus-frequency = <0>;
  41                         clock-frequency = <0>;
  42                 };
  43         };
  44
  45         memory {
  46                 device_type = "memory";
  47                 reg = <0x00000000 0x04000000>;
  48         };
  49
  50         soc8323@e0000000 {
  51                 #address-cells = <1>;
  52                 #size-cells = <1>;
  53                 device_type = "soc";
  54                 ranges = <0x0 0xe0000000 0x00100000>;
  55                 reg = <0xe0000000 0x00000200>;
  56                 bus-frequency = <0>;
  57
  58                 wdt@200 {
  59                         device_type = "watchdog";
  60                         compatible = "mpc83xx_wdt";
  61                         reg = <0x200 0x100>;
  62                 };
  63
  64                 i2c@3000 {
  65                         #address-cells = <1>;
  66                         #size-cells = <0>;
  67                         cell-index = <0>;
  68                         compatible = "fsl-i2c";
  69                         reg = <0x3000 0x100>;
  70                         interrupts = <14 0x8>;
  71                         interrupt-parent = <&pic>;
  72                         dfsrr;
  73                 };
  74
  75                 serial0: serial@4500 {
  76                         cell-index = <0>;
  77                         device_type = "serial";
  78                         compatible = "ns16550";
  79                         reg = <0x4500 0x100>;
  80                         clock-frequency = <0>;
  81                         interrupts = <9 0x8>;
  82                         interrupt-parent = <&pic>;
  83                 };
  84
  85                 serial1: serial@4600 {
  86                         cell-index = <1>;
  87                         device_type = "serial";
  88                         compatible = "ns16550";
  89                         reg = <0x4600 0x100>;
  90                         clock-frequency = <0>;
  91                         interrupts = <10 0x8>;
  92                         interrupt-parent = <&pic>;
  93                 };
  94
  95                 crypto@30000 {
  96                         device_type = "crypto";
  97                         model = "SEC2";
  98                         compatible = "talitos";
  99                         reg = <0x30000 0x7000>;
 100                         interrupts = <11 0x8>;
 101                         interrupt-parent = <&pic>;
 102                         /* Rev. 2.2 */
 103                         num-channels = <1>;
 104                         channel-fifo-len = <24>;
 105                         exec-units-mask = <0x0000004c>;
 106                         descriptor-types-mask = <0x0122003f>;
 107                 };
 108
 109                 pic:pic@700 {
 110                         interrupt-controller;
 111                         #address-cells = <0>;
 112                         #interrupt-cells = <2>;
 113                         reg = <0x700 0x100>;
 114                         device_type = "ipic";
 115                 };
 116
 117                 par_io@1400 {
 118                         reg = <0x1400 0x100>;
 119                         device_type = "par_io";
 120                         num-ports = <7>;
 121
 122                         ucc2pio:ucc_pin@02 {
 123                                 pio-map = <
 124                         /* port  pin  dir  open_drain  assignment  has_irq */
 125                                         3  4  3  0  2  0        /* MDIO */
 126                                         3  5  1  0  2  0        /* MDC */
 127                                         3 21  2  0  1  0        /* RX_CLK (CLK16) */
 128                                         3 23  2  0  1  0        /* TX_CLK (CLK3) */
 129                                         0 18  1  0  1  0        /* TxD0 */
 130                                         0 19  1  0  1  0        /* TxD1 */
 131                                         0 20  1  0  1  0        /* TxD2 */
 132                                         0 21  1  0  1  0        /* TxD3 */
 133                                         0 22  2  0  1  0        /* RxD0 */
 134                                         0 23  2  0  1  0        /* RxD1 */
 135                                         0 24  2  0  1  0        /* RxD2 */
 136                                         0 25  2  0  1  0        /* RxD3 */
 137                                         0 26  2  0  1  0        /* RX_ER */
 138                                         0 27  1  0  1  0        /* TX_ER */
 139                                         0 28  2  0  1  0        /* RX_DV */
 140                                         0 29  2  0  1  0        /* COL */
 141                                         0 30  1  0  1  0        /* TX_EN */
 142                                         0 31  2  0  1  0>;      /* CRS */
 143                         };
 144                         ucc3pio:ucc_pin@03 {
 145                                 pio-map = <
 146                         /* port  pin  dir  open_drain  assignment  has_irq */
 147                                         0 13  2  0  1  0        /* RX_CLK (CLK9) */
 148                                         3 24  2  0  1  0        /* TX_CLK (CLK10) */
 149                                         1  0  1  0  1  0        /* TxD0 */
 150                                         1  1  1  0  1  0        /* TxD1 */
 151                                         1  2  1  0  1  0        /* TxD2 */
 152                                         1  3  1  0  1  0        /* TxD3 */
 153                                         1  4  2  0  1  0        /* RxD0 */
 154                                         1  5  2  0  1  0        /* RxD1 */
 155                                         1  6  2  0  1  0        /* RxD2 */
 156                                         1  7  2  0  1  0        /* RxD3 */
 157                                         1  8  2  0  1  0        /* RX_ER */
 158                                         1  9  1  0  1  0        /* TX_ER */
 159                                         1 10  2  0  1  0        /* RX_DV */
 160                                         1 11  2  0  1  0        /* COL */
 161                                         1 12  1  0  1  0        /* TX_EN */
 162                                         1 13  2  0  1  0>;      /* CRS */
 163                         };
 164                 };
 165         };
 166
 167         qe@e0100000 {
 168                 #address-cells = <1>;
 169                 #size-cells = <1>;
 170                 device_type = "qe";
 171                 compatible = "fsl,qe";
 172                 ranges = <0x0 0xe0100000 0x00100000>;
 173                 reg = <0xe0100000 0x480>;
 174                 brg-frequency = <0>;
 175                 bus-frequency = <198000000>;
 176
 177                 muram@10000 {
 178                         #address-cells = <1>;
 179                         #size-cells = <1>;
 180                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
 181                         ranges = <0x0 0x00010000 0x00004000>;
 182
 183                         data-only@0 {
 184                                 compatible = "fsl,qe-muram-data",
 185                                              "fsl,cpm-muram-data";
 186                                 reg = <0x0 0x4000>;
 187                         };
 188                 };
 189
 190                 spi@4c0 {
 191                         cell-index = <0>;
 192                         compatible = "fsl,spi";
 193                         reg = <0x4c0 0x40>;
 194                         interrupts = <2>;
 195                         interrupt-parent = <&qeic>;
 196                         mode = "cpu-qe";
 197                 };
 198
 199                 spi@500 {
 200                         cell-index = <1>;
 201                         compatible = "fsl,spi";
 202                         reg = <0x500 0x40>;
 203                         interrupts = <1>;
 204                         interrupt-parent = <&qeic>;
 205                         mode = "cpu";
 206                 };
 207
 208                 enet0: ucc@3000 {
 209                         device_type = "network";
 210                         compatible = "ucc_geth";
 211                         cell-index = <2>;
 212                         reg = <0x3000 0x200>;
 213                         interrupts = <33>;
 214                         interrupt-parent = <&qeic>;
 215                         local-mac-address = [ 00 00 00 00 00 00 ];
 216                         rx-clock-name = "clk16";
 217                         tx-clock-name = "clk3";
 218                         phy-handle = <&phy00>;
 219                         pio-handle = <&ucc2pio>;
 220                 };
 221
 222                 enet1: ucc@2200 {
 223                         device_type = "network";
 224                         compatible = "ucc_geth";
 225                         cell-index = <3>;
 226                         reg = <0x2200 0x200>;
 227                         interrupts = <34>;
 228                         interrupt-parent = <&qeic>;
 229                         local-mac-address = [ 00 00 00 00 00 00 ];
 230                         rx-clock-name = "clk9";
 231                         tx-clock-name = "clk10";
 232                         phy-handle = <&phy04>;
 233                         pio-handle = <&ucc3pio>;
 234                 };
 235
 236                 mdio@3120 {
 237                         #address-cells = <1>;
 238                         #size-cells = <0>;
 239                         reg = <0x3120 0x18>;
 240                         compatible = "fsl,ucc-mdio";
 241
 242                         phy00:ethernet-phy@00 {
 243                                 interrupt-parent = <&pic>;
 244                                 interrupts = <0>;
 245                                 reg = <0x0>;
 246                                 device_type = "ethernet-phy";
 247                         };
 248                         phy04:ethernet-phy@04 {
 249                                 interrupt-parent = <&pic>;
 250                                 interrupts = <0>;
 251                                 reg = <0x4>;
 252                                 device_type = "ethernet-phy";
 253                         };
 254                 };
 255
 256                 qeic:interrupt-controller@80 {
 257                         interrupt-controller;
 258                         compatible = "fsl,qe-ic";
 259                         #address-cells = <0>;
 260                         #interrupt-cells = <1>;
 261                         reg = <0x80 0x80>;
 262                         big-endian;
 263                         interrupts = <32 0x8 33 0x8>; //high:32 low:33
 264                         interrupt-parent = <&pic>;
 265                 };
 266         };
 267
 268         pci0: pci@e0008500 {
 269                 cell-index = <1>;
 270                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 271                 interrupt-map = <
 272                                 /* IDSEL 0x10 AD16 (USB) */
 273                                  0x8000 0x0 0x0 0x1 &pic 17 0x8
 274
 275                                 /* IDSEL 0x11 AD17 (Mini1)*/
 276                                  0x8800 0x0 0x0 0x1 &pic 18 0x8
 277                                  0x8800 0x0 0x0 0x2 &pic 19 0x8
 278                                  0x8800 0x0 0x0 0x3 &pic 20 0x8
 279                                  0x8800 0x0 0x0 0x4 &pic 48 0x8
 280
 281                                 /* IDSEL 0x12 AD18 (PCI/Mini2) */
 282                                  0x9000 0x0 0x0 0x1 &pic 19 0x8
 283                                  0x9000 0x0 0x0 0x2 &pic 20 0x8
 284                                  0x9000 0x0 0x0 0x3 &pic 48 0x8
 285                                  0x9000 0x0 0x0 0x4 &pic 17 0x8>;
 286
 287                 interrupt-parent = <&pic>;
 288                 interrupts = <66 0x8>;
 289                 bus-range = <0x0 0x0>;
 290                 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 291                           0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
 292                           0x01000000 0x0 0xd0000000 0xd0000000 0x0 0x04000000>;
 293                 clock-frequency = <0>;
 294                 #interrupt-cells = <1>;
 295                 #size-cells = <2>;
 296                 #address-cells = <3>;
 297                 reg = <0xe0008500 0x100>;
 298                 compatible = "fsl,mpc8349-pci";
 299                 device_type = "pci";
 300         };
 301 };