arch/powerpc/boot/dts/lite5200b.dts

   1 /*
   2  * Lite5200B board Device Tree Source
   3  *
   4  * Copyright 2006-2007 Secret Lab Technologies Ltd.
   5  * Grant Likely <grant.likely@secretlab.ca>
   6  *
   7  * This program is free software; you can redistribute  it and/or modify it
   8  * under  the terms of  the GNU General  Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  */
  12
  13 /*
  14  * WARNING: Do not depend on this tree layout remaining static just yet.
  15  * The MPC5200 device tree conventions are still in flux
  16  * Keep an eye on the linuxppc-dev mailing list for more details
  17  */
  18
  19 / {
  20         model = "fsl,lite5200b";
  21         compatible = "fsl,lite5200b";
  22         #address-cells = <1>;
  23         #size-cells = <1>;
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 PowerPC,5200@0 {
  30                         device_type = "cpu";
  31                         reg = <0>;
  32                         d-cache-line-size = <20>;
  33                         i-cache-line-size = <20>;
  34                         d-cache-size = <4000>;          // L1, 16K
  35                         i-cache-size = <4000>;          // L1, 16K
  36                         timebase-frequency = <0>;       // from bootloader
  37                         bus-frequency = <0>;            // from bootloader
  38                         clock-frequency = <0>;          // from bootloader
  39                 };
  40         };
  41
  42         memory {
  43                 device_type = "memory";
  44                 reg = <00000000 10000000>;      // 256MB
  45         };
  46
  47         soc5200@f0000000 {
  48                 #address-cells = <1>;
  49                 #size-cells = <1>;
  50                 compatible = "fsl,mpc5200b-immr";
  51                 ranges = <0 f0000000 0000c000>;
  52                 reg = <f0000000 00000100>;
  53                 bus-frequency = <0>;            // from bootloader
  54                 system-frequency = <0>;         // from bootloader
  55
  56                 cdm@200 {
  57                         compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
  58                         reg = <200 38>;
  59                 };
  60
  61                 mpc5200_pic: interrupt-controller@500 {
  62                         // 5200 interrupts are encoded into two levels;
  63                         interrupt-controller;
  64                         #interrupt-cells = <3>;
  65                         device_type = "interrupt-controller";
  66                         compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
  67                         reg = <500 80>;
  68                 };
  69
  70                 timer@600 {     // General Purpose Timer
  71                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
  72                         cell-index = <0>;
  73                         reg = <600 10>;
  74                         interrupts = <1 9 0>;
  75                         interrupt-parent = <&mpc5200_pic>;
  76                         fsl,has-wdt;
  77                 };
  78
  79                 timer@610 {     // General Purpose Timer
  80                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
  81                         cell-index = <1>;
  82                         reg = <610 10>;
  83                         interrupts = <1 a 0>;
  84                         interrupt-parent = <&mpc5200_pic>;
  85                 };
  86
  87                 timer@620 {     // General Purpose Timer
  88                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
  89                         cell-index = <2>;
  90                         reg = <620 10>;
  91                         interrupts = <1 b 0>;
  92                         interrupt-parent = <&mpc5200_pic>;
  93                 };
  94
  95                 timer@630 {     // General Purpose Timer
  96                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
  97                         cell-index = <3>;
  98                         reg = <630 10>;
  99                         interrupts = <1 c 0>;
 100                         interrupt-parent = <&mpc5200_pic>;
 101                 };
 102
 103                 timer@640 {     // General Purpose Timer
 104                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
 105                         cell-index = <4>;
 106                         reg = <640 10>;
 107                         interrupts = <1 d 0>;
 108                         interrupt-parent = <&mpc5200_pic>;
 109                 };
 110
 111                 timer@650 {     // General Purpose Timer
 112                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
 113                         cell-index = <5>;
 114                         reg = <650 10>;
 115                         interrupts = <1 e 0>;
 116                         interrupt-parent = <&mpc5200_pic>;
 117                 };
 118
 119                 timer@660 {     // General Purpose Timer
 120                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
 121                         cell-index = <6>;
 122                         reg = <660 10>;
 123                         interrupts = <1 f 0>;
 124                         interrupt-parent = <&mpc5200_pic>;
 125                 };
 126
 127                 timer@670 {     // General Purpose Timer
 128                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
 129                         cell-index = <7>;
 130                         reg = <670 10>;
 131                         interrupts = <1 10 0>;
 132                         interrupt-parent = <&mpc5200_pic>;
 133                 };
 134
 135                 rtc@800 {       // Real time clock
 136                         compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
 137                         device_type = "rtc";
 138                         reg = <800 100>;
 139                         interrupts = <1 5 0 1 6 0>;
 140                         interrupt-parent = <&mpc5200_pic>;
 141                 };
 142
 143                 can@900 {
 144                         compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
 145                         cell-index = <0>;
 146                         interrupts = <2 11 0>;
 147                         interrupt-parent = <&mpc5200_pic>;
 148                         reg = <900 80>;
 149                 };
 150
 151                 can@980 {
 152                         compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
 153                         cell-index = <1>;
 154                         interrupts = <2 12 0>;
 155                         interrupt-parent = <&mpc5200_pic>;
 156                         reg = <980 80>;
 157                 };
 158
 159                 gpio@b00 {
 160                         compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
 161                         reg = <b00 40>;
 162                         interrupts = <1 7 0>;
 163                         interrupt-parent = <&mpc5200_pic>;
 164                 };
 165
 166                 gpio@c00 {
 167                         compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
 168                         reg = <c00 40>;
 169                         interrupts = <1 8 0 0 3 0>;
 170                         interrupt-parent = <&mpc5200_pic>;
 171                 };
 172
 173                 spi@f00 {
 174                         compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
 175                         reg = <f00 20>;
 176                         interrupts = <2 d 0 2 e 0>;
 177                         interrupt-parent = <&mpc5200_pic>;
 178                 };
 179
 180                 usb@1000 {
 181                         compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
 182                         reg = <1000 ff>;
 183                         interrupts = <2 6 0>;
 184                         interrupt-parent = <&mpc5200_pic>;
 185                 };
 186
 187                 dma-controller@1200 {
 188                         device_type = "dma-controller";
 189                         compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
 190                         reg = <1200 80>;
 191                         interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
 192                                       3 4 0  3 5 0  3 6 0  3 7 0
 193                                       3 8 0  3 9 0  3 a 0  3 b 0
 194                                       3 c 0  3 d 0  3 e 0  3 f 0>;
 195                         interrupt-parent = <&mpc5200_pic>;
 196                 };
 197
 198                 xlb@1f00 {
 199                         compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
 200                         reg = <1f00 100>;
 201                 };
 202
 203                 serial@2000 {           // PSC1
 204                         device_type = "serial";
 205                         compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
 206                         port-number = <0>;  // Logical port assignment
 207                         cell-index = <0>;
 208                         reg = <2000 100>;
 209                         interrupts = <2 1 0>;
 210                         interrupt-parent = <&mpc5200_pic>;
 211                 };
 212
 213                 // PSC2 in ac97 mode example
 214                 //ac97@2200 {           // PSC2
 215                 //      compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
 216                 //      cell-index = <1>;
 217                 //      reg = <2200 100>;
 218                 //      interrupts = <2 2 0>;
 219                 //      interrupt-parent = <&mpc5200_pic>;
 220                 //};
 221
 222                 // PSC3 in CODEC mode example
 223                 //i2s@2400 {            // PSC3
 224                 //      compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible
 225                 //      cell-index = <2>;
 226                 //      reg = <2400 100>;
 227                 //      interrupts = <2 3 0>;
 228                 //      interrupt-parent = <&mpc5200_pic>;
 229                 //};
 230
 231                 // PSC4 in uart mode example
 232                 //serial@2600 {         // PSC4
 233                 //      device_type = "serial";
 234                 //      compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
 235                 //      cell-index = <3>;
 236                 //      reg = <2600 100>;
 237                 //      interrupts = <2 b 0>;
 238                 //      interrupt-parent = <&mpc5200_pic>;
 239                 //};
 240
 241                 // PSC5 in uart mode example
 242                 //serial@2800 {         // PSC5
 243                 //      device_type = "serial";
 244                 //      compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
 245                 //      cell-index = <4>;
 246                 //      reg = <2800 100>;
 247                 //      interrupts = <2 c 0>;
 248                 //      interrupt-parent = <&mpc5200_pic>;
 249                 //};
 250
 251                 // PSC6 in spi mode example
 252                 //spi@2c00 {            // PSC6
 253                 //      compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
 254                 //      cell-index = <5>;
 255                 //      reg = <2c00 100>;
 256                 //      interrupts = <2 4 0>;
 257                 //      interrupt-parent = <&mpc5200_pic>;
 258                 //};
 259
 260                 ethernet@3000 {
 261                         device_type = "network";
 262                         compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
 263                         reg = <3000 400>;
 264                         local-mac-address = [ 00 00 00 00 00 00 ];
 265                         interrupts = <2 5 0>;
 266                         interrupt-parent = <&mpc5200_pic>;
 267                         phy-handle = <&phy0>;
 268                 };
 269
 270                 mdio@3000 {
 271                         #address-cells = <1>;
 272                         #size-cells = <0>;
 273                         compatible = "fsl,mpc5200b-mdio";
 274                         reg = <3000 400>;       // fec range, since we need to setup fec interrupts
 275                         interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
 276                         interrupt-parent = <&mpc5200_pic>;
 277
 278                         phy0:ethernet-phy@0 {
 279                                 device_type = "ethernet-phy";
 280                                 reg = <0>;
 281                         };
 282                 };
 283
 284                 ata@3a00 {
 285                         device_type = "ata";
 286                         compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
 287                         reg = <3a00 100>;
 288                         interrupts = <2 7 0>;
 289                         interrupt-parent = <&mpc5200_pic>;
 290                 };
 291
 292                 i2c@3d00 {
 293                         #address-cells = <1>;
 294                         #size-cells = <0>;
 295                         compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
 296                         cell-index = <0>;
 297                         reg = <3d00 40>;
 298                         interrupts = <2 f 0>;
 299                         interrupt-parent = <&mpc5200_pic>;
 300                         fsl5200-clocking;
 301                 };
 302
 303                 i2c@3d40 {
 304                         #address-cells = <1>;
 305                         #size-cells = <0>;
 306                         compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
 307                         cell-index = <1>;
 308                         reg = <3d40 40>;
 309                         interrupts = <2 10 0>;
 310                         interrupt-parent = <&mpc5200_pic>;
 311                         fsl5200-clocking;
 312                 };
 313                 sram@8000 {
 314                         compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram";
 315                         reg = <8000 4000>;
 316                 };
 317         };
 318
 319         pci@f0000d00 {
 320                 #interrupt-cells = <1>;
 321                 #size-cells = <2>;
 322                 #address-cells = <3>;
 323                 device_type = "pci";
 324                 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
 325                 reg = <f0000d00 100>;
 326                 interrupt-map-mask = <f800 0 0 7>;
 327                 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
 328                                  c000 0 0 2 &mpc5200_pic 1 1 3
 329                                  c000 0 0 3 &mpc5200_pic 1 2 3
 330                                  c000 0 0 4 &mpc5200_pic 1 3 3
 331
 332                                  c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
 333                                  c800 0 0 2 &mpc5200_pic 1 2 3
 334                                  c800 0 0 3 &mpc5200_pic 1 3 3
 335                                  c800 0 0 4 &mpc5200_pic 0 0 3>;
 336                 clock-frequency = <0>; // From boot loader
 337                 interrupts = <2 8 0 2 9 0 2 a 0>;
 338                 interrupt-parent = <&mpc5200_pic>;
 339                 bus-range = <0 0>;
 340                 ranges = <42000000 0 80000000 80000000 0 20000000
 341                           02000000 0 a0000000 a0000000 0 10000000
 342                           01000000 0 00000000 b0000000 0 01000000>;
 343         };
 344 };