arch/powerpc/boot/dts/lite5200b.dts

   1 /*
   2  * Lite5200B board Device Tree Source
   3  *
   4  * Copyright 2006-2007 Secret Lab Technologies Ltd.
   5  * Grant Likely <grant.likely@secretlab.ca>
   6  *
   7  * This program is free software; you can redistribute  it and/or modify it
   8  * under  the terms of  the GNU General  Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  */
  12
  13 /*
  14  * WARNING: Do not depend on this tree layout remaining static just yet.
  15  * The MPC5200 device tree conventions are still in flux
  16  * Keep an eye on the linuxppc-dev mailing list for more details
  17  */
  18
  19 / {
  20         model = "fsl,lite5200b";
  21         // revision = "1.0";
  22         compatible = "fsl,lite5200b";
  23         #address-cells = <1>;
  24         #size-cells = <1>;
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 PowerPC,5200@0 {
  31                         device_type = "cpu";
  32                         reg = <0>;
  33                         d-cache-line-size = <20>;
  34                         i-cache-line-size = <20>;
  35                         d-cache-size = <4000>;          // L1, 16K
  36                         i-cache-size = <4000>;          // L1, 16K
  37                         timebase-frequency = <0>;       // from bootloader
  38                         bus-frequency = <0>;            // from bootloader
  39                         clock-frequency = <0>;          // from bootloader
  40                 };
  41         };
  42
  43         memory {
  44                 device_type = "memory";
  45                 reg = <00000000 10000000>;      // 256MB
  46         };
  47
  48         soc5200@f0000000 {
  49                 #address-cells = <1>;
  50                 #size-cells = <1>;
  51                 model = "fsl,mpc5200b";
  52                 compatible = "mpc5200";
  53                 revision = "";                  // from bootloader
  54                 device_type = "soc";
  55                 ranges = <0 f0000000 0000c000>;
  56                 reg = <f0000000 00000100>;
  57                 bus-frequency = <0>;            // from bootloader
  58                 system-frequency = <0>;         // from bootloader
  59
  60                 cdm@200 {
  61                         compatible = "mpc5200b-cdm","mpc5200-cdm";
  62                         reg = <200 38>;
  63                 };
  64
  65                 mpc5200_pic: pic@500 {
  66                         // 5200 interrupts are encoded into two levels;
  67                         interrupt-controller;
  68                         #interrupt-cells = <3>;
  69                         device_type = "interrupt-controller";
  70                         compatible = "mpc5200b-pic","mpc5200-pic";
  71                         reg = <500 80>;
  72                 };
  73
  74                 gpt@600 {       // General Purpose Timer
  75                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
  76                         cell-index = <0>;
  77                         reg = <600 10>;
  78                         interrupts = <1 9 0>;
  79                         interrupt-parent = <&mpc5200_pic>;
  80                         fsl,has-wdt;
  81                 };
  82
  83                 gpt@610 {       // General Purpose Timer
  84                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
  85                         cell-index = <1>;
  86                         reg = <610 10>;
  87                         interrupts = <1 a 0>;
  88                         interrupt-parent = <&mpc5200_pic>;
  89                 };
  90
  91                 gpt@620 {       // General Purpose Timer
  92                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
  93                         cell-index = <2>;
  94                         reg = <620 10>;
  95                         interrupts = <1 b 0>;
  96                         interrupt-parent = <&mpc5200_pic>;
  97                 };
  98
  99                 gpt@630 {       // General Purpose Timer
 100                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
 101                         cell-index = <3>;
 102                         reg = <630 10>;
 103                         interrupts = <1 c 0>;
 104                         interrupt-parent = <&mpc5200_pic>;
 105                 };
 106
 107                 gpt@640 {       // General Purpose Timer
 108                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
 109                         cell-index = <4>;
 110                         reg = <640 10>;
 111                         interrupts = <1 d 0>;
 112                         interrupt-parent = <&mpc5200_pic>;
 113                 };
 114
 115                 gpt@650 {       // General Purpose Timer
 116                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
 117                         cell-index = <5>;
 118                         reg = <650 10>;
 119                         interrupts = <1 e 0>;
 120                         interrupt-parent = <&mpc5200_pic>;
 121                 };
 122
 123                 gpt@660 {       // General Purpose Timer
 124                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
 125                         cell-index = <6>;
 126                         reg = <660 10>;
 127                         interrupts = <1 f 0>;
 128                         interrupt-parent = <&mpc5200_pic>;
 129                 };
 130
 131                 gpt@670 {       // General Purpose Timer
 132                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
 133                         cell-index = <7>;
 134                         reg = <670 10>;
 135                         interrupts = <1 10 0>;
 136                         interrupt-parent = <&mpc5200_pic>;
 137                 };
 138
 139                 rtc@800 {       // Real time clock
 140                         compatible = "mpc5200b-rtc","mpc5200-rtc";
 141                         device_type = "rtc";
 142                         reg = <800 100>;
 143                         interrupts = <1 5 0 1 6 0>;
 144                         interrupt-parent = <&mpc5200_pic>;
 145                 };
 146
 147                 mscan@900 {
 148                         device_type = "mscan";
 149                         compatible = "mpc5200b-mscan","mpc5200-mscan";
 150                         cell-index = <0>;
 151                         interrupts = <2 11 0>;
 152                         interrupt-parent = <&mpc5200_pic>;
 153                         reg = <900 80>;
 154                 };
 155
 156                 mscan@980 {
 157                         device_type = "mscan";
 158                         compatible = "mpc5200b-mscan","mpc5200-mscan";
 159                         cell-index = <1>;
 160                         interrupts = <2 12 0>;
 161                         interrupt-parent = <&mpc5200_pic>;
 162                         reg = <980 80>;
 163                 };
 164
 165                 gpio@b00 {
 166                         compatible = "mpc5200b-gpio","mpc5200-gpio";
 167                         reg = <b00 40>;
 168                         interrupts = <1 7 0>;
 169                         interrupt-parent = <&mpc5200_pic>;
 170                 };
 171
 172                 gpio-wkup@c00 {
 173                         compatible = "mpc5200b-gpio-wkup","mpc5200-gpio-wkup";
 174                         reg = <c00 40>;
 175                         interrupts = <1 8 0 0 3 0>;
 176                         interrupt-parent = <&mpc5200_pic>;
 177                 };
 178
 179                 spi@f00 {
 180                         device_type = "spi";
 181                         compatible = "mpc5200b-spi","mpc5200-spi";
 182                         reg = <f00 20>;
 183                         interrupts = <2 d 0 2 e 0>;
 184                         interrupt-parent = <&mpc5200_pic>;
 185                 };
 186
 187                 usb@1000 {
 188                         device_type = "usb-ohci-be";
 189                         compatible = "mpc5200b-ohci","mpc5200-ohci","ohci-be";
 190                         reg = <1000 ff>;
 191                         interrupts = <2 6 0>;
 192                         interrupt-parent = <&mpc5200_pic>;
 193                 };
 194
 195                 bestcomm@1200 {
 196                         device_type = "dma-controller";
 197                         compatible = "mpc5200b-bestcomm","mpc5200-bestcomm";
 198                         reg = <1200 80>;
 199                         interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
 200                                       3 4 0  3 5 0  3 6 0  3 7 0
 201                                       3 8 0  3 9 0  3 a 0  3 b 0
 202                                       3 c 0  3 d 0  3 e 0  3 f 0>;
 203                         interrupt-parent = <&mpc5200_pic>;
 204                 };
 205
 206                 xlb@1f00 {
 207                         compatible = "mpc5200b-xlb","mpc5200-xlb";
 208                         reg = <1f00 100>;
 209                 };
 210
 211                 serial@2000 {           // PSC1
 212                         device_type = "serial";
 213                         compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
 214                         port-number = <0>;  // Logical port assignment
 215                         cell-index = <0>;
 216                         reg = <2000 100>;
 217                         interrupts = <2 1 0>;
 218                         interrupt-parent = <&mpc5200_pic>;
 219                 };
 220
 221                 // PSC2 in ac97 mode example
 222                 //ac97@2200 {           // PSC2
 223                 //      device_type = "sound";
 224                 //      compatible = "mpc5200b-psc-ac97","mpc5200-psc-ac97";
 225                 //      cell-index = <1>;
 226                 //      reg = <2200 100>;
 227                 //      interrupts = <2 2 0>;
 228                 //      interrupt-parent = <&mpc5200_pic>;
 229                 //};
 230
 231                 // PSC3 in CODEC mode example
 232                 //i2s@2400 {            // PSC3
 233                 //      device_type = "sound";
 234                 //      compatible = "mpc5200b-psc-i2s"; //not 5200 compatible
 235                 //      cell-index = <2>;
 236                 //      reg = <2400 100>;
 237                 //      interrupts = <2 3 0>;
 238                 //      interrupt-parent = <&mpc5200_pic>;
 239                 //};
 240
 241                 // PSC4 in uart mode example
 242                 //serial@2600 {         // PSC4
 243                 //      device_type = "serial";
 244                 //      compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
 245                 //      cell-index = <3>;
 246                 //      reg = <2600 100>;
 247                 //      interrupts = <2 b 0>;
 248                 //      interrupt-parent = <&mpc5200_pic>;
 249                 //};
 250
 251                 // PSC5 in uart mode example
 252                 //serial@2800 {         // PSC5
 253                 //      device_type = "serial";
 254                 //      compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
 255                 //      cell-index = <4>;
 256                 //      reg = <2800 100>;
 257                 //      interrupts = <2 c 0>;
 258                 //      interrupt-parent = <&mpc5200_pic>;
 259                 //};
 260
 261                 // PSC6 in spi mode example
 262                 //spi@2c00 {            // PSC6
 263                 //      device_type = "spi";
 264                 //      compatible = "mpc5200b-psc-spi","mpc5200-psc-spi";
 265                 //      cell-index = <5>;
 266                 //      reg = <2c00 100>;
 267                 //      interrupts = <2 4 0>;
 268                 //      interrupt-parent = <&mpc5200_pic>;
 269                 //};
 270
 271                 ethernet@3000 {
 272                         device_type = "network";
 273                         compatible = "mpc5200b-fec","mpc5200-fec";
 274                         reg = <3000 400>;
 275                         mac-address = [ 02 03 04 05 06 07 ]; // Bad!
 276                         interrupts = <2 5 0>;
 277                         interrupt-parent = <&mpc5200_pic>;
 278                         phy-handle = <&phy0>;
 279                 };
 280
 281                 mdio@3000 {
 282                         #address-cells = <1>;
 283                         #size-cells = <0>;
 284                         device_type = "mdio";
 285                         compatible = "mpc5200b-fec-phy";
 286                         reg = <3000 400>;       // fec range, since we need to setup fec interrupts
 287                         interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
 288                         interrupt-parent = <&mpc5200_pic>;
 289
 290                         phy0:ethernet-phy@0 {
 291                                 device_type = "ethernet-phy";
 292                                 reg = <0>;
 293                         };
 294                 };
 295
 296                 ata@3a00 {
 297                         device_type = "ata";
 298                         compatible = "mpc5200b-ata","mpc5200-ata";
 299                         reg = <3a00 100>;
 300                         interrupts = <2 7 0>;
 301                         interrupt-parent = <&mpc5200_pic>;
 302                 };
 303
 304                 i2c@3d00 {
 305                         #address-cells = <1>;
 306                         #size-cells = <0>;
 307                         compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c";
 308                         cell-index = <0>;
 309                         reg = <3d00 40>;
 310                         interrupts = <2 f 0>;
 311                         interrupt-parent = <&mpc5200_pic>;
 312                         fsl5200-clocking;
 313                 };
 314
 315                 i2c@3d40 {
 316                         #address-cells = <1>;
 317                         #size-cells = <0>;
 318                         compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c";
 319                         cell-index = <1>;
 320                         reg = <3d40 40>;
 321                         interrupts = <2 10 0>;
 322                         interrupt-parent = <&mpc5200_pic>;
 323                         fsl5200-clocking;
 324                 };
 325                 sram@8000 {
 326                         device_type = "sram";
 327                         compatible = "mpc5200b-sram","mpc5200-sram","sram";
 328                         reg = <8000 4000>;
 329                 };
 330         };
 331
 332         pci@f0000d00 {
 333                 #interrupt-cells = <1>;
 334                 #size-cells = <2>;
 335                 #address-cells = <3>;
 336                 device_type = "pci";
 337                 compatible = "mpc5200b-pci","mpc5200-pci";
 338                 reg = <f0000d00 100>;
 339                 interrupt-map-mask = <f800 0 0 7>;
 340                 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
 341                                  c000 0 0 2 &mpc5200_pic 1 1 3
 342                                  c000 0 0 3 &mpc5200_pic 1 2 3
 343                                  c000 0 0 4 &mpc5200_pic 1 3 3
 344
 345                                  c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
 346                                  c800 0 0 2 &mpc5200_pic 1 2 3
 347                                  c800 0 0 3 &mpc5200_pic 1 3 3
 348                                  c800 0 0 4 &mpc5200_pic 0 0 3>;
 349                 clock-frequency = <0>; // From boot loader
 350                 interrupts = <2 8 0 2 9 0 2 a 0>;
 351                 interrupt-parent = <&mpc5200_pic>;
 352                 bus-range = <0 0>;
 353                 ranges = <42000000 0 80000000 80000000 0 20000000
 354                           02000000 0 a0000000 a0000000 0 10000000
 355                           01000000 0 00000000 b0000000 0 01000000>;
 356         };
 357 };