arch/powerpc/boot/dts/lite5200.dts

   1 /*
   2  * Lite5200 board Device Tree Source
   3  *
   4  * Copyright 2006-2007 Secret Lab Technologies Ltd.
   5  * Grant Likely <grant.likely@secretlab.ca>
   6  *
   7  * This program is free software; you can redistribute  it and/or modify it
   8  * under  the terms of  the GNU General  Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  */
  12
  13 /*
  14  * WARNING: Do not depend on this tree layout remaining static just yet.
  15  * The MPC5200 device tree conventions are still in flux
  16  * Keep an eye on the linuxppc-dev mailing list for more details
  17  */
  18
  19 / {
  20         model = "fsl,lite5200";
  21         // revision = "1.0";
  22         compatible = "fsl,lite5200\0generic-mpc5200";
  23         #address-cells = <1>;
  24         #size-cells = <1>;
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 PowerPC,5200@0 {
  31                         device_type = "cpu";
  32                         reg = <0>;
  33                         d-cache-line-size = <20>;
  34                         i-cache-line-size = <20>;
  35                         d-cache-size = <4000>;          // L1, 16K
  36                         i-cache-size = <4000>;          // L1, 16K
  37                         timebase-frequency = <0>;       // from bootloader
  38                         bus-frequency = <0>;            // from bootloader
  39                         clock-frequency = <0>;          // from bootloader
  40                 };
  41         };
  42
  43         memory {
  44                 device_type = "memory";
  45                 reg = <00000000 04000000>;      // 64MB
  46         };
  47
  48         soc5200@f0000000 {
  49                 model = "fsl,mpc5200";
  50                 compatible = "mpc5200";
  51                 revision = "";                  // from bootloader
  52                 device_type = "soc";
  53                 ranges = <0 f0000000 0000c000>;
  54                 reg = <f0000000 00000100>;
  55                 bus-frequency = <0>;            // from bootloader
  56                 system-frequency = <0>;         // from bootloader
  57
  58                 cdm@200 {
  59                         compatible = "mpc5200-cdm";
  60                         reg = <200 38>;
  61                 };
  62
  63                 mpc5200_pic: pic@500 {
  64                         // 5200 interrupts are encoded into two levels;
  65                         interrupt-controller;
  66                         #interrupt-cells = <3>;
  67                         device_type = "interrupt-controller";
  68                         compatible = "mpc5200-pic";
  69                         reg = <500 80>;
  70                 };
  71
  72                 gpt@600 {       // General Purpose Timer
  73                         compatible = "mpc5200-gpt";
  74                         device_type = "gpt";
  75                         cell-index = <0>;
  76                         reg = <600 10>;
  77                         interrupts = <1 9 0>;
  78                         interrupt-parent = <&mpc5200_pic>;
  79                         has-wdt;
  80                 };
  81
  82                 gpt@610 {       // General Purpose Timer
  83                         compatible = "mpc5200-gpt";
  84                         device_type = "gpt";
  85                         cell-index = <1>;
  86                         reg = <610 10>;
  87                         interrupts = <1 a 0>;
  88                         interrupt-parent = <&mpc5200_pic>;
  89                 };
  90
  91                 gpt@620 {       // General Purpose Timer
  92                         compatible = "mpc5200-gpt";
  93                         device_type = "gpt";
  94                         cell-index = <2>;
  95                         reg = <620 10>;
  96                         interrupts = <1 b 0>;
  97                         interrupt-parent = <&mpc5200_pic>;
  98                 };
  99
 100                 gpt@630 {       // General Purpose Timer
 101                         compatible = "mpc5200-gpt";
 102                         device_type = "gpt";
 103                         cell-index = <3>;
 104                         reg = <630 10>;
 105                         interrupts = <1 c 0>;
 106                         interrupt-parent = <&mpc5200_pic>;
 107                 };
 108
 109                 gpt@640 {       // General Purpose Timer
 110                         compatible = "mpc5200-gpt";
 111                         device_type = "gpt";
 112                         cell-index = <4>;
 113                         reg = <640 10>;
 114                         interrupts = <1 d 0>;
 115                         interrupt-parent = <&mpc5200_pic>;
 116                 };
 117
 118                 gpt@650 {       // General Purpose Timer
 119                         compatible = "mpc5200-gpt";
 120                         device_type = "gpt";
 121                         cell-index = <5>;
 122                         reg = <650 10>;
 123                         interrupts = <1 e 0>;
 124                         interrupt-parent = <&mpc5200_pic>;
 125                 };
 126
 127                 gpt@660 {       // General Purpose Timer
 128                         compatible = "mpc5200-gpt";
 129                         device_type = "gpt";
 130                         cell-index = <6>;
 131                         reg = <660 10>;
 132                         interrupts = <1 f 0>;
 133                         interrupt-parent = <&mpc5200_pic>;
 134                 };
 135
 136                 gpt@670 {       // General Purpose Timer
 137                         compatible = "mpc5200-gpt";
 138                         device_type = "gpt";
 139                         cell-index = <7>;
 140                         reg = <670 10>;
 141                         interrupts = <1 10 0>;
 142                         interrupt-parent = <&mpc5200_pic>;
 143                 };
 144
 145                 rtc@800 {       // Real time clock
 146                         compatible = "mpc5200-rtc";
 147                         device_type = "rtc";
 148                         reg = <800 100>;
 149                         interrupts = <1 5 0 1 6 0>;
 150                         interrupt-parent = <&mpc5200_pic>;
 151                 };
 152
 153                 mscan@900 {
 154                         device_type = "mscan";
 155                         compatible = "mpc5200-mscan";
 156                         cell-index = <0>;
 157                         interrupts = <2 11 0>;
 158                         interrupt-parent = <&mpc5200_pic>;
 159                         reg = <900 80>;
 160                 };
 161
 162                 mscan@980 {
 163                         device_type = "mscan";
 164                         compatible = "mpc5200-mscan";
 165                         cell-index = <1>;
 166                         interrupts = <2 12 0>;
 167                         interrupt-parent = <&mpc5200_pic>;
 168                         reg = <980 80>;
 169                 };
 170
 171                 gpio@b00 {
 172                         compatible = "mpc5200-gpio";
 173                         reg = <b00 40>;
 174                         interrupts = <1 7 0>;
 175                         interrupt-parent = <&mpc5200_pic>;
 176                 };
 177
 178                 gpio-wkup@c00 {
 179                         compatible = "mpc5200-gpio-wkup";
 180                         reg = <c00 40>;
 181                         interrupts = <1 8 0 0 3 0>;
 182                         interrupt-parent = <&mpc5200_pic>;
 183                 };
 184
 185                 pci@0d00 {
 186                         #interrupt-cells = <1>;
 187                         #size-cells = <2>;
 188                         #address-cells = <3>;
 189                         device_type = "pci";
 190                         compatible = "mpc5200-pci";
 191                         reg = <d00 100>;
 192                         interrupt-map-mask = <f800 0 0 7>;
 193                         interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
 194                                          c000 0 0 2 &mpc5200_pic 0 0 3
 195                                          c000 0 0 3 &mpc5200_pic 0 0 3
 196                                          c000 0 0 4 &mpc5200_pic 0 0 3>;
 197                         clock-frequency = <0>; // From boot loader
 198                         interrupts = <2 8 0 2 9 0 2 a 0>;
 199                         interrupt-parent = <&mpc5200_pic>;
 200                         bus-range = <0 0>;
 201                         ranges = <42000000 0 80000000 80000000 0 20000000
 202                                   02000000 0 a0000000 a0000000 0 10000000
 203                                   01000000 0 00000000 b0000000 0 01000000>;
 204                 };
 205
 206                 spi@f00 {
 207                         device_type = "spi";
 208                         compatible = "mpc5200-spi";
 209                         reg = <f00 20>;
 210                         interrupts = <2 d 0 2 e 0>;
 211                         interrupt-parent = <&mpc5200_pic>;
 212                 };
 213
 214                 usb@1000 {
 215                         device_type = "usb-ohci-be";
 216                         compatible = "mpc5200-ohci\0ohci-be";
 217                         reg = <1000 ff>;
 218                         interrupts = <2 6 0>;
 219                         interrupt-parent = <&mpc5200_pic>;
 220                 };
 221
 222                 bestcomm@1200 {
 223                         device_type = "dma-controller";
 224                         compatible = "mpc5200-bestcomm";
 225                         reg = <1200 80>;
 226                         interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
 227                                       3 4 0  3 5 0  3 6 0  3 7 0
 228                                       3 8 0  3 9 0  3 a 0  3 b 0
 229                                       3 c 0  3 d 0  3 e 0  3 f 0>;
 230                         interrupt-parent = <&mpc5200_pic>;
 231                 };
 232
 233                 xlb@1f00 {
 234                         compatible = "mpc5200-xlb";
 235                         reg = <1f00 100>;
 236                 };
 237
 238                 serial@2000 {           // PSC1
 239                         device_type = "serial";
 240                         compatible = "mpc5200-psc-uart";
 241                         port-number = <0>;  // Logical port assignment
 242                         cell-index = <0>;
 243                         reg = <2000 100>;
 244                         interrupts = <2 1 0>;
 245                         interrupt-parent = <&mpc5200_pic>;
 246                 };
 247
 248                 // PSC2 in ac97 mode example
 249                 //ac97@2200 {           // PSC2
 250                 //      device_type = "sound";
 251                 //      compatible = "mpc5200-psc-ac97";
 252                 //      cell-index = <1>;
 253                 //      reg = <2200 100>;
 254                 //      interrupts = <2 2 0>;
 255                 //      interrupt-parent = <&mpc5200_pic>;
 256                 //};
 257
 258                 // PSC3 in CODEC mode example
 259                 //i2s@2400 {            // PSC3
 260                 //      device_type = "sound";
 261                 //      compatible = "mpc5200-psc-i2s";
 262                 //      cell-index = <2>;
 263                 //      reg = <2400 100>;
 264                 //      interrupts = <2 3 0>;
 265                 //      interrupt-parent = <&mpc5200_pic>;
 266                 //};
 267
 268                 // PSC4 in uart mode example
 269                 //serial@2600 {         // PSC4
 270                 //      device_type = "serial";
 271                 //      compatible = "mpc5200-psc-uart";
 272                 //      cell-index = <3>;
 273                 //      reg = <2600 100>;
 274                 //      interrupts = <2 b 0>;
 275                 //      interrupt-parent = <&mpc5200_pic>;
 276                 //};
 277
 278                 // PSC5 in uart mode example
 279                 //serial@2800 {         // PSC5
 280                 //      device_type = "serial";
 281                 //      compatible = "mpc5200-psc-uart";
 282                 //      cell-index = <4>;
 283                 //      reg = <2800 100>;
 284                 //      interrupts = <2 c 0>;
 285                 //      interrupt-parent = <&mpc5200_pic>;
 286                 //};
 287
 288                 // PSC6 in spi mode example
 289                 //spi@2c00 {            // PSC6
 290                 //      device_type = "spi";
 291                 //      compatible = "mpc5200-psc-spi";
 292                 //      cell-index = <5>;
 293                 //      reg = <2c00 100>;
 294                 //      interrupts = <2 4 0>;
 295                 //      interrupt-parent = <&mpc5200_pic>;
 296                 //};
 297
 298                 ethernet@3000 {
 299                         device_type = "network";
 300                         compatible = "mpc5200-fec";
 301                         reg = <3000 800>;
 302                         mac-address = [ 02 03 04 05 06 07 ]; // Bad!
 303                         interrupts = <2 5 0>;
 304                         interrupt-parent = <&mpc5200_pic>;
 305                 };
 306
 307                 ata@3a00 {
 308                         device_type = "ata";
 309                         compatible = "mpc5200-ata";
 310                         reg = <3a00 100>;
 311                         interrupts = <2 7 0>;
 312                         interrupt-parent = <&mpc5200_pic>;
 313                 };
 314
 315                 i2c@3d00 {
 316                         device_type = "i2c";
 317                         compatible = "mpc5200-i2c\0fsl-i2c";
 318                         cell-index = <0>;
 319                         reg = <3d00 40>;
 320                         interrupts = <2 f 0>;
 321                         interrupt-parent = <&mpc5200_pic>;
 322                         fsl5200-clocking;
 323                 };
 324
 325                 i2c@3d40 {
 326                         device_type = "i2c";
 327                         compatible = "mpc5200-i2c\0fsl-i2c";
 328                         cell-index = <1>;
 329                         reg = <3d40 40>;
 330                         interrupts = <2 10 0>;
 331                         interrupt-parent = <&mpc5200_pic>;
 332                         fsl5200-clocking;
 333                 };
 334                 sram@8000 {
 335                         device_type = "sram";
 336                         compatible = "mpc5200-sram\0sram";
 337                         reg = <8000 4000>;
 338                 };
 339         };
 340 };