arch/powerpc/boot/dts/kuroboxHG.dts

   1 /*
   2  * Device Tree Souce for Buffalo KuroboxHG
   3  *
   4  * Choose CONFIG_LINKSTATION to build a kernel for KuroboxHG, or use
   5  * the default configuration linkstation_defconfig.
   6  *
   7  * Based on sandpoint.dts
   8  *
   9  * 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de>
  10  *
  11  * This file is licensed under
  12  * the terms of the GNU General Public License version 2.  This program
  13  * is licensed "as is" without any warranty of any kind, whether express
  14  * or implied.
  15
  16 XXXX add flash parts, rtc, ??
  17
  18 build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
  19
  20
  21  */
  22
  23 / {
  24         model = "KuroboxHG";
  25         compatible = "linkstation";
  26         #address-cells = <1>;
  27         #size-cells = <1>;
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 PowerPC,603e { /* Really 8241 */
  34                         device_type = "cpu";
  35                         reg = <0>;
  36                         clock-frequency = <fdad680>;    /* Fixed by bootloader */
  37                         timebase-frequency = <1F04000>; /* Fixed by bootloader */
  38                         bus-frequency = <0>;            /* Fixed by bootloader */
  39                         /* Following required by dtc but not used */
  40                         i-cache-size = <4000>;
  41                         d-cache-size = <4000>;
  42                 };
  43         };
  44
  45         memory {
  46                 device_type = "memory";
  47                 reg = <00000000 08000000>;
  48         };
  49
  50         soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
  51                 #address-cells = <1>;
  52                 #size-cells = <1>;
  53                 #interrupt-cells = <2>;
  54                 device_type = "soc";
  55                 compatible = "mpc10x";
  56                 store-gathering = <0>; /* 0 == off, !0 == on */
  57                 reg = <80000000 00100000>;
  58                 ranges = <80000000 80000000 70000000    /* pci mem space */
  59                           fc000000 fc000000 00100000    /* EUMB */
  60                           fe000000 fe000000 00c00000    /* pci i/o space */
  61                           fec00000 fec00000 00300000    /* pci cfg regs */
  62                           fef00000 fef00000 00100000>;  /* pci iack */
  63
  64                 i2c@80003000 {
  65                         #address-cells = <1>;
  66                         #size-cells = <0>;
  67                         device_type = "i2c";
  68                         compatible = "fsl-i2c";
  69                         reg = <80003000 1000>;
  70                         interrupts = <5 2>;
  71                         interrupt-parent = <&mpic>;
  72
  73                         rtc@32 {
  74                                 device_type = "rtc";
  75                                 compatible = "ricoh,rs5c372b";
  76                                 reg = <32>;
  77                         };
  78                 };
  79
  80                 serial@80004500 {
  81                         device_type = "serial";
  82                         compatible = "ns16550";
  83                         reg = <80004500 8>;
  84                         clock-frequency = <7c044a8>;
  85                         current-speed = <2580>;
  86                         interrupts = <9 2>;
  87                         interrupt-parent = <&mpic>;
  88                 };
  89
  90                 serial@80004600 {
  91                         device_type = "serial";
  92                         compatible = "ns16550";
  93                         reg = <80004600 8>;
  94                         clock-frequency = <7c044a8>;
  95                         current-speed = <e100>;
  96                         interrupts = <a 0>;
  97                         interrupt-parent = <&mpic>;
  98                 };
  99
 100                 mpic: interrupt-controller@80040000 {
 101                         #interrupt-cells = <2>;
 102                         #address-cells = <0>;
 103                         device_type = "open-pic";
 104                         compatible = "chrp,open-pic";
 105                         interrupt-controller;
 106                         reg = <80040000 40000>;
 107                         built-in;
 108                 };
 109
 110                 pci@fec00000 {
 111                         #address-cells = <3>;
 112                         #size-cells = <2>;
 113                         #interrupt-cells = <1>;
 114                         device_type = "pci";
 115                         compatible = "mpc10x-pci";
 116                         reg = <fec00000 400000>;
 117                         ranges = <01000000 0        0 fe000000 0 00c00000
 118                                   02000000 0 80000000 80000000 0 70000000>;
 119                         bus-range = <0 ff>;
 120                         clock-frequency = <7f28155>;
 121                         interrupt-parent = <&mpic>;
 122                         interrupt-map-mask = <f800 0 0 7>;
 123                         interrupt-map = <
 124                                 /* IDSEL 11 - IRQ0 ETH */
 125                                 5800 0 0 1 &mpic 0 1
 126                                 5800 0 0 2 &mpic 1 1
 127                                 5800 0 0 3 &mpic 2 1
 128                                 5800 0 0 4 &mpic 3 1
 129                                 /* IDSEL 12 - IRQ1 IDE0 */
 130                                 6000 0 0 1 &mpic 1 1
 131                                 6000 0 0 2 &mpic 2 1
 132                                 6000 0 0 3 &mpic 3 1
 133                                 6000 0 0 4 &mpic 0 1
 134                                 /* IDSEL 14 - IRQ3 USB2.0 */
 135                                 7000 0 0 1 &mpic 3 1
 136                                 7000 0 0 2 &mpic 3 1
 137                                 7000 0 0 3 &mpic 3 1
 138                                 7000 0 0 4 &mpic 3 1
 139                         >;
 140                 };
 141         };
 142 };