arch/powerpc/boot/dts/gef_sbc610.dts

   1 /*
   2  * GE Fanuc SBC610 Device Tree Source
   3  *
   4  * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  *
  11  * Based on: SBS CM6 Device Tree Source
  12  * Copyright 2007 SBS Technologies GmbH & Co. KG
  13  * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
  14  * Copyright 2006 Freescale Semiconductor Inc.
  15  */
  16
  17 /*
  18  * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
  19  */
  20
  21 /dts-v1/;
  22
  23 / {
  24         model = "GEF_SBC610";
  25         compatible = "gef,sbc610";
  26         #address-cells = <1>;
  27         #size-cells = <1>;
  28
  29         aliases {
  30                 ethernet0 = &enet0;
  31                 ethernet1 = &enet1;
  32                 serial0 = &serial0;
  33                 serial1 = &serial1;
  34                 pci0 = &pci0;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 PowerPC,8641@0 {
  42                         device_type = "cpu";
  43                         reg = <0>;
  44                         d-cache-line-size = <32>;       // 32 bytes
  45                         i-cache-line-size = <32>;       // 32 bytes
  46                         d-cache-size = <32768>;         // L1, 32K
  47                         i-cache-size = <32768>;         // L1, 32K
  48                         timebase-frequency = <0>;       // From uboot
  49                         bus-frequency = <0>;            // From uboot
  50                         clock-frequency = <0>;          // From uboot
  51                 };
  52                 PowerPC,8641@1 {
  53                         device_type = "cpu";
  54                         reg = <1>;
  55                         d-cache-line-size = <32>;       // 32 bytes
  56                         i-cache-line-size = <32>;       // 32 bytes
  57                         d-cache-size = <32768>;         // L1, 32K
  58                         i-cache-size = <32768>;         // L1, 32K
  59                         timebase-frequency = <0>;       // From uboot
  60                         bus-frequency = <0>;            // From uboot
  61                         clock-frequency = <0>;          // From uboot
  62                 };
  63         };
  64
  65         memory {
  66                 device_type = "memory";
  67                 reg = <0x0 0x40000000>; // set by uboot
  68         };
  69
  70         localbus@fef05000 {
  71                 #address-cells = <2>;
  72                 #size-cells = <1>;
  73                 compatible = "fsl,mpc8641-localbus", "simple-bus";
  74                 reg = <0xf8005000 0x1000>;
  75                 interrupts = <19 2>;
  76                 interrupt-parent = <&mpic>;
  77
  78                 ranges = <0 0 0xff000000 0x01000000     // 16MB Boot flash
  79                           1 0 0xe8000000 0x08000000     // Paged Flash 0
  80                           2 0 0xe0000000 0x08000000     // Paged Flash 1
  81                           3 0 0xfc100000 0x00020000     // NVRAM
  82                           4 0 0xfc000000 0x00008000     // FPGA
  83                           5 0 0xfc008000 0x00008000     // AFIX FPGA
  84                           6 0 0xfd000000 0x00800000     // IO FPGA (8-bit)
  85                           7 0 0xfd800000 0x00800000>;   // IO FPGA (32-bit)
  86
  87                 fpga@4,0 {
  88                         compatible = "gef,fpga-regs";
  89                         reg = <0x4 0x0 0x40>;
  90                 };
  91
  92                 wdt@4,2000 {
  93                         compatible = "gef,fpga-wdt";
  94                         reg = <0x4 0x2000 0x8>;
  95                         interrupts = <0x1a 0x4>;
  96                         interrupt-parent = <&gef_pic>;
  97                 };
  98                 /* Second watchdog available, driver currently supports one.
  99                 wdt@4,2010 {
 100                         compatible = "gef,fpga-wdt";
 101                         reg = <0x4 0x2010 0x8>;
 102                         interrupts = <0x1b 0x4>;
 103                         interrupt-parent = <&gef_pic>;
 104                 };
 105                 */
 106                 gef_pic: pic@4,4000 {
 107                         #interrupt-cells = <1>;
 108                         interrupt-controller;
 109                         compatible = "gef,fpga-pic";
 110                         reg = <0x4 0x4000 0x20>;
 111                         interrupts = <0x8
 112                                       0x9>;
 113                         interrupt-parent = <&mpic>;
 114
 115                 };
 116                 gef_gpio: gpio@7,14000 {
 117                         #gpio-cells = <2>;
 118                         compatible = "gef,sbc610-gpio";
 119                         reg = <0x7 0x14000 0x24>;
 120                         gpio-controller;
 121                 };
 122         };
 123
 124         soc@fef00000 {
 125                 #address-cells = <1>;
 126                 #size-cells = <1>;
 127                 #interrupt-cells = <2>;
 128                 device_type = "soc";
 129                 compatible = "simple-bus";
 130                 ranges = <0x0 0xfef00000 0x00100000>;
 131                 reg = <0xfef00000 0x100000>;    // CCSRBAR 1M
 132                 bus-frequency = <33333333>;
 133
 134                 i2c1: i2c@3000 {
 135                         #address-cells = <1>;
 136                         #size-cells = <0>;
 137                         compatible = "fsl-i2c";
 138                         reg = <0x3000 0x100>;
 139                         interrupts = <0x2b 0x2>;
 140                         interrupt-parent = <&mpic>;
 141                         dfsrr;
 142
 143                         rtc@51 {
 144                                 compatible = "epson,rx8581";
 145                                 reg = <0x00000051>;
 146                         };
 147
 148                         eti@6b {
 149                                 compatible = "dallas,ds1682";
 150                                 reg = <0x6b>;
 151                         };
 152                 };
 153
 154                 i2c2: i2c@3100 {
 155                         #address-cells = <1>;
 156                         #size-cells = <0>;
 157                         compatible = "fsl-i2c";
 158                         reg = <0x3100 0x100>;
 159                         interrupts = <0x2b 0x2>;
 160                         interrupt-parent = <&mpic>;
 161                         dfsrr;
 162                 };
 163
 164                 dma@21300 {
 165                         #address-cells = <1>;
 166                         #size-cells = <1>;
 167                         compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
 168                         reg = <0x21300 0x4>;
 169                         ranges = <0x0 0x21100 0x200>;
 170                         cell-index = <0>;
 171                         dma-channel@0 {
 172                                 compatible = "fsl,mpc8641-dma-channel",
 173                                            "fsl,eloplus-dma-channel";
 174                                 reg = <0x0 0x80>;
 175                                 cell-index = <0>;
 176                                 interrupt-parent = <&mpic>;
 177                                 interrupts = <20 2>;
 178                         };
 179                         dma-channel@80 {
 180                                 compatible = "fsl,mpc8641-dma-channel",
 181                                            "fsl,eloplus-dma-channel";
 182                                 reg = <0x80 0x80>;
 183                                 cell-index = <1>;
 184                                 interrupt-parent = <&mpic>;
 185                                 interrupts = <21 2>;
 186                         };
 187                         dma-channel@100 {
 188                                 compatible = "fsl,mpc8641-dma-channel",
 189                                            "fsl,eloplus-dma-channel";
 190                                 reg = <0x100 0x80>;
 191                                 cell-index = <2>;
 192                                 interrupt-parent = <&mpic>;
 193                                 interrupts = <22 2>;
 194                         };
 195                         dma-channel@180 {
 196                                 compatible = "fsl,mpc8641-dma-channel",
 197                                            "fsl,eloplus-dma-channel";
 198                                 reg = <0x180 0x80>;
 199                                 cell-index = <3>;
 200                                 interrupt-parent = <&mpic>;
 201                                 interrupts = <23 2>;
 202                         };
 203                 };
 204
 205                 mdio@24520 {
 206                         #address-cells = <1>;
 207                         #size-cells = <0>;
 208                         compatible = "fsl,gianfar-mdio";
 209                         reg = <0x24520 0x20>;
 210
 211                         phy0: ethernet-phy@0 {
 212                                 interrupt-parent = <&gef_pic>;
 213                                 interrupts = <0x9 0x4>;
 214                                 reg = <1>;
 215                         };
 216                         phy2: ethernet-phy@2 {
 217                                 interrupt-parent = <&gef_pic>;
 218                                 interrupts = <0x8 0x4>;
 219                                 reg = <3>;
 220                         };
 221                 };
 222
 223                 enet0: ethernet@24000 {
 224                         device_type = "network";
 225                         model = "eTSEC";
 226                         compatible = "gianfar";
 227                         reg = <0x24000 0x1000>;
 228                         local-mac-address = [ 00 00 00 00 00 00 ];
 229                         interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
 230                         interrupt-parent = <&mpic>;
 231                         phy-handle = <&phy0>;
 232                         phy-connection-type = "gmii";
 233                 };
 234
 235                 enet1: ethernet@26000 {
 236                         device_type = "network";
 237                         model = "eTSEC";
 238                         compatible = "gianfar";
 239                         reg = <0x26000 0x1000>;
 240                         local-mac-address = [ 00 00 00 00 00 00 ];
 241                         interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
 242                         interrupt-parent = <&mpic>;
 243                         phy-handle = <&phy2>;
 244                         phy-connection-type = "gmii";
 245                 };
 246
 247                 serial0: serial@4500 {
 248                         cell-index = <0>;
 249                         device_type = "serial";
 250                         compatible = "ns16550";
 251                         reg = <0x4500 0x100>;
 252                         clock-frequency = <0>;
 253                         interrupts = <0x2a 0x2>;
 254                         interrupt-parent = <&mpic>;
 255                 };
 256
 257                 serial1: serial@4600 {
 258                         cell-index = <1>;
 259                         device_type = "serial";
 260                         compatible = "ns16550";
 261                         reg = <0x4600 0x100>;
 262                         clock-frequency = <0>;
 263                         interrupts = <0x1c 0x2>;
 264                         interrupt-parent = <&mpic>;
 265                 };
 266
 267                 mpic: pic@40000 {
 268                         clock-frequency = <0>;
 269                         interrupt-controller;
 270                         #address-cells = <0>;
 271                         #interrupt-cells = <2>;
 272                         reg = <0x40000 0x40000>;
 273                         compatible = "chrp,open-pic";
 274                         device_type = "open-pic";
 275                 };
 276
 277                 global-utilities@e0000 {
 278                         compatible = "fsl,mpc8641-guts";
 279                         reg = <0xe0000 0x1000>;
 280                         fsl,has-rstcr;
 281                 };
 282         };
 283
 284         pci0: pcie@fef08000 {
 285                 compatible = "fsl,mpc8641-pcie";
 286                 device_type = "pci";
 287                 #interrupt-cells = <1>;
 288                 #size-cells = <2>;
 289                 #address-cells = <3>;
 290                 reg = <0xfef08000 0x1000>;
 291                 bus-range = <0x0 0xff>;
 292                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
 293                           0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
 294                 clock-frequency = <33333333>;
 295                 interrupt-parent = <&mpic>;
 296                 interrupts = <0x18 0x2>;
 297                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 298                 interrupt-map = <
 299                         0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
 300                         0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
 301                         0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
 302                         0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
 303                 >;
 304
 305                 pcie@0 {
 306                         reg = <0 0 0 0 0>;
 307                         #size-cells = <2>;
 308                         #address-cells = <3>;
 309                         device_type = "pci";
 310                         ranges = <0x02000000 0x0 0x80000000
 311                                   0x02000000 0x0 0x80000000
 312                                   0x0 0x40000000
 313
 314                                   0x01000000 0x0 0x00000000
 315                                   0x01000000 0x0 0x00000000
 316                                   0x0 0x00400000>;
 317                 };
 318         };
 319 };