arch/powerpc/boot/dts/gef_sbc310.dts

   1 /*
   2  * GE Fanuc SBC310 Device Tree Source
   3  *
   4  * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  *
  11  * Based on: SBS CM6 Device Tree Source
  12  * Copyright 2007 SBS Technologies GmbH & Co. KG
  13  * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
  14  * Copyright 2006 Freescale Semiconductor Inc.
  15  */
  16
  17 /*
  18  * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
  19  */
  20
  21 /dts-v1/;
  22
  23 / {
  24         model = "GEF_SBC310";
  25         compatible = "gef,sbc310";
  26         #address-cells = <1>;
  27         #size-cells = <1>;
  28
  29         aliases {
  30                 ethernet0 = &enet0;
  31                 ethernet1 = &enet1;
  32                 serial0 = &serial0;
  33                 serial1 = &serial1;
  34                 pci0 = &pci0;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 PowerPC,8641@0 {
  42                         device_type = "cpu";
  43                         reg = <0>;
  44                         d-cache-line-size = <32>;       // 32 bytes
  45                         i-cache-line-size = <32>;       // 32 bytes
  46                         d-cache-size = <32768>;         // L1, 32K
  47                         i-cache-size = <32768>;         // L1, 32K
  48                         timebase-frequency = <0>;       // From uboot
  49                         bus-frequency = <0>;            // From uboot
  50                         clock-frequency = <0>;          // From uboot
  51                 };
  52                 PowerPC,8641@1 {
  53                         device_type = "cpu";
  54                         reg = <1>;
  55                         d-cache-line-size = <32>;       // 32 bytes
  56                         i-cache-line-size = <32>;       // 32 bytes
  57                         d-cache-size = <32768>;         // L1, 32K
  58                         i-cache-size = <32768>;         // L1, 32K
  59                         timebase-frequency = <0>;       // From uboot
  60                         bus-frequency = <0>;            // From uboot
  61                         clock-frequency = <0>;          // From uboot
  62                 };
  63         };
  64
  65         memory {
  66                 device_type = "memory";
  67                 reg = <0x0 0x40000000>; // set by uboot
  68         };
  69
  70         localbus@fef05000 {
  71                 #address-cells = <2>;
  72                 #size-cells = <1>;
  73                 compatible = "fsl,mpc8641-localbus", "simple-bus";
  74                 reg = <0xfef05000 0x1000>;
  75                 interrupts = <19 2>;
  76                 interrupt-parent = <&mpic>;
  77
  78                 ranges = <0 0 0xff000000 0x01000000     // 16MB Boot flash
  79                           1 0 0xe0000000 0x08000000     // Paged Flash 0
  80                           2 0 0xe8000000 0x08000000     // Paged Flash 1
  81                           3 0 0xfc100000 0x00020000     // NVRAM
  82                           4 0 0xfc000000 0x00010000>;   // FPGA
  83
  84                 /* flash@0,0 is a mirror of part of the memory in flash@1,0
  85                 flash@0,0 {
  86                         compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
  87                         reg = <0x0 0x0 0x01000000>;
  88                         bank-width = <2>;
  89                         device-width = <2>;
  90                         #address-cells = <1>;
  91                         #size-cells = <1>;
  92                         partition@0 {
  93                                 label = "firmware";
  94                                 reg = <0x0 0x01000000>;
  95                                 read-only;
  96                         };
  97                 };
  98                 */
  99
 100                 flash@1,0 {
 101                         compatible = "gef,sbc310-paged-flash", "cfi-flash";
 102                         reg = <0x1 0x0 0x8000000>;
 103                         bank-width = <2>;
 104                         device-width = <2>;
 105                         #address-cells = <1>;
 106                         #size-cells = <1>;
 107                         partition@0 {
 108                                 label = "user";
 109                                 reg = <0x0 0x7800000>;
 110                         };
 111                         partition@7800000 {
 112                                 label = "firmware";
 113                                 reg = <0x7800000 0x800000>;
 114                                 read-only;
 115                         };
 116                 };
 117
 118                 fpga@4,0 {
 119                         compatible = "gef,fpga-regs";
 120                         reg = <0x4 0x0 0x40>;
 121                 };
 122
 123                 wdt@4,2000 {
 124                         compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
 125                                 "gef,fpga-wdt";
 126                         reg = <0x4 0x2000 0x8>;
 127                         interrupts = <0x1a 0x4>;
 128                         interrupt-parent = <&gef_pic>;
 129                 };
 130 /*
 131                 wdt@4,2010 {
 132                         compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
 133                                 "gef,fpga-wdt";
 134                         reg = <0x4 0x2010 0x8>;
 135                         interrupts = <0x1b 0x4>;
 136                         interrupt-parent = <&gef_pic>;
 137                 };
 138 */
 139                 gef_pic: pic@4,4000 {
 140                         #interrupt-cells = <1>;
 141                         interrupt-controller;
 142                         compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic";
 143                         reg = <0x4 0x4000 0x20>;
 144                         interrupts = <0x8
 145                                       0x9>;
 146                         interrupt-parent = <&mpic>;
 147
 148                 };
 149                 gef_gpio: gpio@4,8000 {
 150                         #gpio-cells = <2>;
 151                         compatible = "gef,sbc310-gpio";
 152                         reg = <0x4 0x8000 0x24>;
 153                         gpio-controller;
 154                 };
 155         };
 156
 157         soc@fef00000 {
 158                 #address-cells = <1>;
 159                 #size-cells = <1>;
 160                 #interrupt-cells = <2>;
 161                 device_type = "soc";
 162                 compatible = "fsl,mpc8641-soc", "simple-bus";
 163                 ranges = <0x0 0xfef00000 0x00100000>;
 164                 bus-frequency = <33333333>;
 165
 166                 mcm-law@0 {
 167                         compatible = "fsl,mcm-law";
 168                         reg = <0x0 0x1000>;
 169                         fsl,num-laws = <10>;
 170                 };
 171
 172                 mcm@1000 {
 173                         compatible = "fsl,mpc8641-mcm", "fsl,mcm";
 174                         reg = <0x1000 0x1000>;
 175                         interrupts = <17 2>;
 176                         interrupt-parent = <&mpic>;
 177                 };
 178
 179                 i2c1: i2c@3000 {
 180                         #address-cells = <1>;
 181                         #size-cells = <0>;
 182                         compatible = "fsl-i2c";
 183                         reg = <0x3000 0x100>;
 184                         interrupts = <0x2b 0x2>;
 185                         interrupt-parent = <&mpic>;
 186                         dfsrr;
 187
 188                         rtc@51 {
 189                                 compatible = "epson,rx8581";
 190                                 reg = <0x00000051>;
 191                         };
 192                 };
 193
 194                 i2c2: i2c@3100 {
 195                         #address-cells = <1>;
 196                         #size-cells = <0>;
 197                         compatible = "fsl-i2c";
 198                         reg = <0x3100 0x100>;
 199                         interrupts = <0x2b 0x2>;
 200                         interrupt-parent = <&mpic>;
 201                         dfsrr;
 202
 203                         hwmon@48 {
 204                                 compatible = "national,lm92";
 205                                 reg = <0x48>;
 206                         };
 207
 208                         hwmon@4c {
 209                                 compatible = "adi,adt7461";
 210                                 reg = <0x4c>;
 211                         };
 212
 213                         eti@6b {
 214                                 compatible = "dallas,ds1682";
 215                                 reg = <0x6b>;
 216                         };
 217                 };
 218
 219                 dma@21300 {
 220                         #address-cells = <1>;
 221                         #size-cells = <1>;
 222                         compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
 223                         reg = <0x21300 0x4>;
 224                         ranges = <0x0 0x21100 0x200>;
 225                         cell-index = <0>;
 226                         dma-channel@0 {
 227                                 compatible = "fsl,mpc8641-dma-channel",
 228                                            "fsl,eloplus-dma-channel";
 229                                 reg = <0x0 0x80>;
 230                                 cell-index = <0>;
 231                                 interrupt-parent = <&mpic>;
 232                                 interrupts = <20 2>;
 233                         };
 234                         dma-channel@80 {
 235                                 compatible = "fsl,mpc8641-dma-channel",
 236                                            "fsl,eloplus-dma-channel";
 237                                 reg = <0x80 0x80>;
 238                                 cell-index = <1>;
 239                                 interrupt-parent = <&mpic>;
 240                                 interrupts = <21 2>;
 241                         };
 242                         dma-channel@100 {
 243                                 compatible = "fsl,mpc8641-dma-channel",
 244                                            "fsl,eloplus-dma-channel";
 245                                 reg = <0x100 0x80>;
 246                                 cell-index = <2>;
 247                                 interrupt-parent = <&mpic>;
 248                                 interrupts = <22 2>;
 249                         };
 250                         dma-channel@180 {
 251                                 compatible = "fsl,mpc8641-dma-channel",
 252                                            "fsl,eloplus-dma-channel";
 253                                 reg = <0x180 0x80>;
 254                                 cell-index = <3>;
 255                                 interrupt-parent = <&mpic>;
 256                                 interrupts = <23 2>;
 257                         };
 258                 };
 259
 260                 enet0: ethernet@24000 {
 261                         #address-cells = <1>;
 262                         #size-cells = <1>;
 263                         device_type = "network";
 264                         model = "eTSEC";
 265                         compatible = "gianfar";
 266                         reg = <0x24000 0x1000>;
 267                         ranges = <0x0 0x24000 0x1000>;
 268                         local-mac-address = [ 00 00 00 00 00 00 ];
 269                         interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
 270                         interrupt-parent = <&mpic>;
 271                         phy-handle = <&phy0>;
 272                         phy-connection-type = "gmii";
 273
 274                         mdio@520 {
 275                                 #address-cells = <1>;
 276                                 #size-cells = <0>;
 277                                 compatible = "fsl,gianfar-mdio";
 278                                 reg = <0x520 0x20>;
 279
 280                                 phy0: ethernet-phy@0 {
 281                                         interrupt-parent = <&gef_pic>;
 282                                         interrupts = <0x9 0x4>;
 283                                         reg = <1>;
 284                                 };
 285                                 phy2: ethernet-phy@2 {
 286                                         interrupt-parent = <&gef_pic>;
 287                                         interrupts = <0x8 0x4>;
 288                                         reg = <3>;
 289                                 };
 290                         };
 291                 };
 292
 293                 enet1: ethernet@26000 {
 294                         device_type = "network";
 295                         model = "eTSEC";
 296                         compatible = "gianfar";
 297                         reg = <0x26000 0x1000>;
 298                         local-mac-address = [ 00 00 00 00 00 00 ];
 299                         interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
 300                         interrupt-parent = <&mpic>;
 301                         phy-handle = <&phy2>;
 302                         phy-connection-type = "gmii";
 303                 };
 304
 305                 serial0: serial@4500 {
 306                         cell-index = <0>;
 307                         device_type = "serial";
 308                         compatible = "ns16550";
 309                         reg = <0x4500 0x100>;
 310                         clock-frequency = <0>;
 311                         interrupts = <0x2a 0x2>;
 312                         interrupt-parent = <&mpic>;
 313                 };
 314
 315                 serial1: serial@4600 {
 316                         cell-index = <1>;
 317                         device_type = "serial";
 318                         compatible = "ns16550";
 319                         reg = <0x4600 0x100>;
 320                         clock-frequency = <0>;
 321                         interrupts = <0x1c 0x2>;
 322                         interrupt-parent = <&mpic>;
 323                 };
 324
 325                 mpic: pic@40000 {
 326                         clock-frequency = <0>;
 327                         interrupt-controller;
 328                         #address-cells = <0>;
 329                         #interrupt-cells = <2>;
 330                         reg = <0x40000 0x40000>;
 331                         compatible = "chrp,open-pic";
 332                         device_type = "open-pic";
 333                 };
 334
 335                 global-utilities@e0000 {
 336                         compatible = "fsl,mpc8641-guts";
 337                         reg = <0xe0000 0x1000>;
 338                         fsl,has-rstcr;
 339                 };
 340         };
 341
 342         pci0: pcie@fef08000 {
 343                 compatible = "fsl,mpc8641-pcie";
 344                 device_type = "pci";
 345                 #interrupt-cells = <1>;
 346                 #size-cells = <2>;
 347                 #address-cells = <3>;
 348                 reg = <0xfef08000 0x1000>;
 349                 bus-range = <0x0 0xff>;
 350                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
 351                           0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
 352                 clock-frequency = <33333333>;
 353                 interrupt-parent = <&mpic>;
 354                 interrupts = <0x18 0x2>;
 355                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 356                 interrupt-map = <
 357                         0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
 358                         0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
 359                         0x0000 0x0 0x0 0x3 &mpic 0x2 0x2
 360                         0x0000 0x0 0x0 0x4 &mpic 0x3 0x2
 361                 >;
 362
 363                 pcie@0 {
 364                         reg = <0 0 0 0 0>;
 365                         #size-cells = <2>;
 366                         #address-cells = <3>;
 367                         device_type = "pci";
 368                         ranges = <0x02000000 0x0 0x80000000
 369                                   0x02000000 0x0 0x80000000
 370                                   0x0 0x40000000
 371
 372                                   0x01000000 0x0 0x00000000
 373                                   0x01000000 0x0 0x00000000
 374                                   0x0 0x00400000>;
 375                 };
 376         };
 377
 378         pci1: pcie@fef09000 {
 379                 compatible = "fsl,mpc8641-pcie";
 380                 device_type = "pci";
 381                 #interrupt-cells = <1>;
 382                 #size-cells = <2>;
 383                 #address-cells = <3>;
 384                 reg = <0xfef09000 0x1000>;
 385                 bus-range = <0x0 0xff>;
 386                 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
 387                           0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>;
 388                 clock-frequency = <33333333>;
 389                 interrupt-parent = <&mpic>;
 390                 interrupts = <0x19 0x2>;
 391                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 392                 interrupt-map = <
 393                         0x0000 0x0 0x0 0x1 &mpic 0x4 0x2
 394                         0x0000 0x0 0x0 0x2 &mpic 0x5 0x2
 395                         0x0000 0x0 0x0 0x3 &mpic 0x6 0x2
 396                         0x0000 0x0 0x0 0x4 &mpic 0x7 0x2
 397                         >;
 398
 399                 pcie@0 {
 400                         reg = <0 0 0 0 0>;
 401                         #size-cells = <2>;
 402                         #address-cells = <3>;
 403                         device_type = "pci";
 404                         ranges = <0x02000000 0x0 0xc0000000
 405                                   0x02000000 0x0 0xc0000000
 406                                   0x0 0x20000000
 407
 408                                   0x01000000 0x0 0x00000000
 409                                   0x01000000 0x0 0x00000000
 410                                   0x0 0x00400000>;
 411                 };
 412         };
 413 };