2 * Code to handle x86 style IRQs plus some generic interrupt stuff.
4 * Copyright (C) 1992 Linus Torvalds
5 * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
6 * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
7 * Copyright (C) 1999-2000 Grant Grundler
8 * Copyright (c) 2005 Matthew Wilcox
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/bitops.h>
25 #include <linux/config.h>
26 #include <linux/errno.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
29 #include <linux/kernel_stat.h>
30 #include <linux/seq_file.h>
31 #include <linux/spinlock.h>
32 #include <linux/types.h>
36 #undef PARISC_IRQ_CR16_COUNTS
38 extern irqreturn_t timer_interrupt(int, void *, struct pt_regs *);
39 extern irqreturn_t ipi_interrupt(int, void *, struct pt_regs *);
41 #define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq))
43 /* Bits in EIEM correlate with cpu_irq_action[].
44 ** Numbered *Big Endian*! (ie bit 0 is MSB)
46 static volatile unsigned long cpu_eiem = 0;
48 static void cpu_disable_irq(unsigned int irq)
50 unsigned long eirr_bit = EIEM_MASK(irq);
52 cpu_eiem &= ~eirr_bit;
53 /* Do nothing on the other CPUs. If they get this interrupt,
54 * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
55 * handle it, and the set_eiem() at the bottom will ensure it
56 * then gets disabled */
59 static void cpu_enable_irq(unsigned int irq)
61 unsigned long eirr_bit = EIEM_MASK(irq);
65 /* FIXME: while our interrupts aren't nested, we cannot reset
66 * the eiem mask if we're already in an interrupt. Once we
67 * implement nested interrupts, this can go away
72 /* This is just a simple NOP IPI. But what it does is cause
73 * all the other CPUs to do a set_eiem(cpu_eiem) at the end
74 * of the interrupt handler */
78 static unsigned int cpu_startup_irq(unsigned int irq)
84 void no_ack_irq(unsigned int irq) { }
85 void no_end_irq(unsigned int irq) { }
87 static struct hw_interrupt_type cpu_interrupt_type = {
89 .startup = cpu_startup_irq,
90 .shutdown = cpu_disable_irq,
91 .enable = cpu_enable_irq,
92 .disable = cpu_disable_irq,
95 // .set_affinity = cpu_set_affinity_irq,
98 int show_interrupts(struct seq_file *p, void *v)
100 int i = *(loff_t *) v, j;
105 for_each_online_cpu(j)
106 seq_printf(p, " CPU%d", j);
108 #ifdef PARISC_IRQ_CR16_COUNTS
109 seq_printf(p, " [min/avg/max] (CPU cycle counts)");
115 struct irqaction *action;
117 spin_lock_irqsave(&irq_desc[i].lock, flags);
118 action = irq_desc[i].action;
121 seq_printf(p, "%3d: ", i);
123 for_each_online_cpu(j)
124 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
126 seq_printf(p, "%10u ", kstat_irqs(i));
129 seq_printf(p, " %14s", irq_desc[i].handler->typename);
130 #ifndef PARISC_IRQ_CR16_COUNTS
131 seq_printf(p, " %s", action->name);
133 while ((action = action->next))
134 seq_printf(p, ", %s", action->name);
136 for ( ;action; action = action->next) {
137 unsigned int k, avg, min, max;
139 min = max = action->cr16_hist[0];
141 for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
142 int hist = action->cr16_hist[k];
149 if (hist > max) max = hist;
150 if (hist < min) min = hist;
154 seq_printf(p, " %s[%d/%d/%d]", action->name,
161 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
170 ** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
171 ** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
173 ** To use txn_XXX() interfaces, get a Virtual IRQ first.
174 ** Then use that to get the Transaction address and data.
177 int cpu_claim_irq(unsigned int irq, struct hw_interrupt_type *type, void *data)
179 if (irq_desc[irq].action)
181 if (irq_desc[irq].handler != &cpu_interrupt_type)
185 irq_desc[irq].handler = type;
186 irq_desc[irq].handler_data = data;
187 cpu_interrupt_type.enable(irq);
192 int txn_claim_irq(int irq)
194 return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq;
198 * The bits_wide parameter accommodates the limitations of the HW/SW which
200 * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
201 * V-class (EPIC): 6 bits
202 * N/L/A-class (iosapic): 8 bits
203 * PCI 2.2 MSI: 16 bits
204 * Some PCI devices: 32 bits (Symbios SCSI/ATM/HyperFabric)
206 * On the service provider side:
207 * o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register)
208 * o PA 2.0 wide mode 6-bits (per processor)
209 * o IA64 8-bits (0-256 total)
211 * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
212 * by the processor...and the N/L-class I/O subsystem supports more bits than
213 * PA2.0 has. The first case is the problem.
215 int txn_alloc_irq(unsigned int bits_wide)
219 /* never return irq 0 cause that's the interval timer */
220 for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) {
221 if (cpu_claim_irq(irq, NULL, NULL) < 0)
223 if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide))
228 /* unlikely, but be prepared */
232 unsigned long txn_alloc_addr(unsigned int virt_irq)
234 static int next_cpu = -1;
236 next_cpu++; /* assign to "next" CPU we want this bugger on */
239 while ((next_cpu < NR_CPUS) && (!cpu_data[next_cpu].txn_addr ||
240 !cpu_online(next_cpu)))
243 if (next_cpu >= NR_CPUS)
244 next_cpu = 0; /* nothing else, assign monarch */
246 return cpu_data[next_cpu].txn_addr;
250 unsigned int txn_alloc_data(unsigned int virt_irq)
252 return virt_irq - CPU_IRQ_BASE;
255 /* ONLY called from entry.S:intr_extint() */
256 void do_cpu_irq_mask(struct pt_regs *regs)
258 unsigned long eirr_val;
263 * Don't allow TIMER or IPI nested interrupts.
264 * Allowing any single interrupt to nest can lead to that CPU
265 * handling interrupts with all enabled interrupts unmasked.
269 /* 1) only process IRQs that are enabled/unmasked (cpu_eiem)
270 * 2) We loop here on EIRR contents in order to avoid
271 * nested interrupts or having to take another interrupt
272 * when we could have just handled it right away.
275 unsigned long bit = (1UL << (BITS_PER_LONG - 1));
277 eirr_val = mfctl(23) & cpu_eiem;
281 mtctl(eirr_val, 23); /* reset bits we are going to process */
283 /* Work our way from MSb to LSb...same order we alloc EIRs */
284 for (irq = TIMER_IRQ; eirr_val && bit; bit>>=1, irq++) {
285 if (!(bit & eirr_val))
288 /* clear bit in mask - can exit loop sooner */
295 set_eiem(cpu_eiem); /* restore original mask */
300 static struct irqaction timer_action = {
301 .handler = timer_interrupt,
303 .flags = SA_INTERRUPT,
307 static struct irqaction ipi_action = {
308 .handler = ipi_interrupt,
310 .flags = SA_INTERRUPT,
314 static void claim_cpu_irqs(void)
317 for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
318 irq_desc[i].handler = &cpu_interrupt_type;
321 irq_desc[TIMER_IRQ].action = &timer_action;
322 irq_desc[TIMER_IRQ].status |= IRQ_PER_CPU;
324 irq_desc[IPI_IRQ].action = &ipi_action;
325 irq_desc[IPI_IRQ].status = IRQ_PER_CPU;
329 void __init init_IRQ(void)
331 local_irq_disable(); /* PARANOID - should already be disabled */
332 mtctl(~0UL, 23); /* EIRR : clear all pending external intr */
336 cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ);
338 cpu_eiem = EIEM_MASK(TIMER_IRQ);
340 set_eiem(cpu_eiem); /* EIEM : enable all external intr */
344 void hw_resend_irq(struct hw_interrupt_type *type, unsigned int irq)
346 /* XXX: Needs to be written. We managed without it so far, but
347 * we really ought to write it.
351 void ack_bad_irq(unsigned int irq)
353 printk("unexpected IRQ %d\n", irq);