1 /* MN10300 Arch-specific interrupt handling
3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
11 #include <linux/module.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel_stat.h>
14 #include <linux/seq_file.h>
15 #include <linux/cpumask.h>
16 #include <asm/setup.h>
17 #include <asm/serial-regs.h>
19 unsigned long __mn10300_irq_enabled_epsw[NR_CPUS] __cacheline_aligned_in_smp = {
20 [0 ... NR_CPUS - 1] = EPSW_IE | EPSW_IM_7
22 EXPORT_SYMBOL(__mn10300_irq_enabled_epsw);
25 static char irq_affinity_online[NR_IRQS] = {
26 [0 ... NR_IRQS - 1] = 0
29 #define NR_IRQ_WORDS ((NR_IRQS + 31) / 32)
30 static unsigned long irq_affinity_request[NR_IRQ_WORDS] = {
31 [0 ... NR_IRQ_WORDS - 1] = 0
33 #endif /* CONFIG_SMP */
35 atomic_t irq_err_count;
38 * MN10300 interrupt controller operations
40 static void mn10300_cpupic_ack(struct irq_data *d)
42 unsigned int irq = d->irq;
46 flags = arch_local_cli_save();
47 GxICR_u8(irq) = GxICR_DETECT;
49 arch_local_irq_restore(flags);
52 static void __mask_and_set_icr(unsigned int irq,
53 unsigned int mask, unsigned int set)
58 flags = arch_local_cli_save();
60 GxICR(irq) = (tmp & mask) | set;
62 arch_local_irq_restore(flags);
65 static void mn10300_cpupic_mask(struct irq_data *d)
67 __mask_and_set_icr(d->irq, GxICR_LEVEL, 0);
70 static void mn10300_cpupic_mask_ack(struct irq_data *d)
72 unsigned int irq = d->irq;
77 flags = arch_local_cli_save();
79 if (!test_and_clear_bit(irq, irq_affinity_request)) {
81 GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_DETECT;
86 GxICR(irq) = (tmp & GxICR_LEVEL);
89 irq_affinity_online[irq] =
90 cpumask_any_and(d->affinity, cpu_online_mask);
91 CROSS_GxICR(irq, irq_affinity_online[irq]) =
92 (tmp & (GxICR_LEVEL | GxICR_ENABLE)) | GxICR_DETECT;
93 tmp = CROSS_GxICR(irq, irq_affinity_online[irq]);
96 arch_local_irq_restore(flags);
97 #else /* CONFIG_SMP */
98 __mask_and_set_icr(irq, GxICR_LEVEL, GxICR_DETECT);
99 #endif /* CONFIG_SMP */
102 static void mn10300_cpupic_unmask(struct irq_data *d)
104 __mask_and_set_icr(d->irq, GxICR_LEVEL, GxICR_ENABLE);
107 static void mn10300_cpupic_unmask_clear(struct irq_data *d)
109 unsigned int irq = d->irq;
110 /* the MN10300 PIC latches its interrupt request bit, even after the
111 * device has ceased to assert its interrupt line and the interrupt
112 * channel has been disabled in the PIC, so for level-triggered
113 * interrupts we need to clear the request bit when we re-enable */
118 flags = arch_local_cli_save();
120 if (!test_and_clear_bit(irq, irq_affinity_request)) {
122 GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT;
127 irq_affinity_online[irq] = cpumask_any_and(d->affinity,
129 CROSS_GxICR(irq, irq_affinity_online[irq]) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT;
130 tmp = CROSS_GxICR(irq, irq_affinity_online[irq]);
133 arch_local_irq_restore(flags);
134 #else /* CONFIG_SMP */
135 __mask_and_set_icr(irq, GxICR_LEVEL, GxICR_ENABLE | GxICR_DETECT);
136 #endif /* CONFIG_SMP */
141 mn10300_cpupic_setaffinity(struct irq_data *d, const struct cpumask *mask,
147 flags = arch_local_cli_save();
153 case CALL_FUNC_SINGLE_IPI:
154 case LOCAL_TIMER_IPI:
155 case FLUSH_CACHE_IPI:
156 case CALL_FUNCTION_NMI_IPI:
157 case DEBUGGER_NMI_IPI:
158 #ifdef CONFIG_MN10300_TTYSM0
161 #ifdef CONFIG_MN10300_TTYSM0_TIMER8
163 #elif CONFIG_MN10300_TTYSM0_TIMER2
165 #endif /* CONFIG_MN10300_TTYSM0_TIMER8 */
166 #endif /* CONFIG_MN10300_TTYSM0 */
168 #ifdef CONFIG_MN10300_TTYSM1
171 #ifdef CONFIG_MN10300_TTYSM1_TIMER12
173 #elif CONFIG_MN10300_TTYSM1_TIMER9
175 #elif CONFIG_MN10300_TTYSM1_TIMER3
177 #endif /* CONFIG_MN10300_TTYSM1_TIMER12 */
178 #endif /* CONFIG_MN10300_TTYSM1 */
180 #ifdef CONFIG_MN10300_TTYSM2
184 #endif /* CONFIG_MN10300_TTYSM2 */
189 set_bit(d->irq, irq_affinity_request);
194 arch_local_irq_restore(flags);
197 #endif /* CONFIG_SMP */
200 * MN10300 PIC level-triggered IRQ handling.
202 * The PIC has no 'ACK' function per se. It is possible to clear individual
203 * channel latches, but each latch relatches whether or not the channel is
204 * masked, so we need to clear the latch when we unmask the channel.
206 * Also for this reason, we don't supply an ack() op (it's unused anyway if
207 * mask_ack() is provided), and mask_ack() just masks.
209 static struct irq_chip mn10300_cpu_pic_level = {
211 .irq_disable = mn10300_cpupic_mask,
212 .irq_enable = mn10300_cpupic_unmask_clear,
214 .irq_mask = mn10300_cpupic_mask,
215 .irq_mask_ack = mn10300_cpupic_mask,
216 .irq_unmask = mn10300_cpupic_unmask_clear,
218 .irq_set_affinity = mn10300_cpupic_setaffinity,
223 * MN10300 PIC edge-triggered IRQ handling.
225 * We use the latch clearing function of the PIC as the 'ACK' function.
227 static struct irq_chip mn10300_cpu_pic_edge = {
229 .irq_disable = mn10300_cpupic_mask,
230 .irq_enable = mn10300_cpupic_unmask,
231 .irq_ack = mn10300_cpupic_ack,
232 .irq_mask = mn10300_cpupic_mask,
233 .irq_mask_ack = mn10300_cpupic_mask_ack,
234 .irq_unmask = mn10300_cpupic_unmask,
236 .irq_set_affinity = mn10300_cpupic_setaffinity,
241 * 'what should we do if we get a hw irq event on an illegal vector'.
242 * each architecture has to answer this themselves.
244 void ack_bad_irq(int irq)
246 printk(KERN_WARNING "unexpected IRQ trap at vector %02x\n", irq);
250 * change the level at which an IRQ executes
251 * - must not be called whilst interrupts are being processed!
253 void set_intr_level(int irq, u16 level)
255 BUG_ON(in_interrupt());
257 __mask_and_set_icr(irq, GxICR_ENABLE, level);
261 * mark an interrupt to be ACK'd after interrupt handlers have been run rather
263 * - see Documentation/mn10300/features.txt
265 void mn10300_set_lateack_irq_type(int irq)
267 irq_set_chip_and_handler(irq, &mn10300_cpu_pic_level,
272 * initialise the interrupt system
274 void __init init_IRQ(void)
278 for (irq = 0; irq < NR_IRQS; irq++)
279 if (irq_get_chip(irq) == &no_irq_chip)
280 /* due to the PIC latching interrupt requests, even
281 * when the IRQ is disabled, IRQ_PENDING is superfluous
282 * and we can use handle_level_irq() for edge-triggered
284 irq_set_chip_and_handler(irq, &mn10300_cpu_pic_edge,
291 * handle normal device IRQs
293 asmlinkage void do_IRQ(void)
295 unsigned long sp, epsw, irq_disabled_epsw, old_irq_enabled_epsw;
296 unsigned int cpu_id = smp_processor_id();
299 sp = current_stack_pointer();
300 BUG_ON(sp - (sp & ~(THREAD_SIZE - 1)) < STACK_WARN);
302 /* make sure local_irq_enable() doesn't muck up the interrupt priority
304 old_irq_enabled_epsw = __mn10300_irq_enabled_epsw[cpu_id];
305 local_save_flags(epsw);
306 __mn10300_irq_enabled_epsw[cpu_id] = EPSW_IE | (EPSW_IM & epsw);
307 irq_disabled_epsw = EPSW_IE | MN10300_CLI_LEVEL;
309 #ifdef CONFIG_MN10300_WD_TIMER
310 __IRQ_STAT(cpu_id, __irq_count)++;
316 /* ask the interrupt controller for the next IRQ to process
317 * - the result we get depends on EPSW.IM
319 irq = IAGR & IAGR_GN;
323 local_irq_restore(irq_disabled_epsw);
325 generic_handle_irq(irq >> 2);
327 /* restore IRQ controls for IAGR access */
328 local_irq_restore(epsw);
331 __mn10300_irq_enabled_epsw[cpu_id] = old_irq_enabled_epsw;
337 * Display interrupt management information through /proc/interrupts
339 int arch_show_interrupts(struct seq_file *p, int prec)
341 #ifdef CONFIG_MN10300_WD_TIMER
344 seq_printf(p, "%*s: ", prec, "NMI");
345 for (j = 0; j < NR_CPUS; j++)
347 seq_printf(p, "%10u ", nmi_count(j));
351 seq_printf(p, "%*s: ", prec, "ERR");
352 seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
356 #ifdef CONFIG_HOTPLUG_CPU
357 void migrate_irqs(void)
360 unsigned int self, new;
363 self = smp_processor_id();
364 for (irq = 0; irq < NR_IRQS; irq++) {
365 struct irq_data *data = irq_get_irq_data(irq);
367 if (irqd_is_per_cpu(data))
370 if (cpumask_test_cpu(self, &data->affinity) &&
371 !cpumask_intersects(&irq_affinity[irq], cpu_online_mask)) {
373 cpu_id = cpumask_first(cpu_online_mask);
374 cpumask_set_cpu(cpu_id, &data->affinity);
376 /* We need to operate irq_affinity_online atomically. */
377 arch_local_cli_save(flags);
378 if (irq_affinity_online[irq] == self) {
382 GxICR(irq) = x & GxICR_LEVEL;
385 new = cpumask_any_and(&data->affinity,
387 irq_affinity_online[irq] = new;
389 CROSS_GxICR(irq, new) =
390 (x & GxICR_LEVEL) | GxICR_DETECT;
391 tmp = CROSS_GxICR(irq, new);
393 x &= GxICR_LEVEL | GxICR_ENABLE;
394 if (GxICR(irq) & GxICR_REQUEST)
395 x |= GxICR_REQUEST | GxICR_DETECT;
396 CROSS_GxICR(irq, new) = x;
397 tmp = CROSS_GxICR(irq, new);
399 arch_local_irq_restore(flags);
402 #endif /* CONFIG_HOTPLUG_CPU */