arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c

   1 /*
   2  * Toshiba rbtx4927 specific setup
   3  *
   4  * Author: MontaVista Software, Inc.
   5  *         source@mvista.com
   6  *
   7  * Copyright 2001-2002 MontaVista Software Inc.
   8  *
   9  * Copyright (C) 1996, 97, 2001, 04  Ralf Baechle (ralf@linux-mips.org)
  10  * Copyright (C) 2000 RidgeRun, Inc.
  11  * Author: RidgeRun, Inc.
  12  *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
  13  *
  14  * Copyright 2001 MontaVista Software Inc.
  15  * Author: jsun@mvista.com or jsun@junsun.net
  16  *
  17  * Copyright 2002 MontaVista Software Inc.
  18  * Author: Michael Pruznick, michael_pruznick@mvista.com
  19  *
  20  * Copyright (C) 2000-2001 Toshiba Corporation
  21  *
  22  * Copyright (C) 2004 MontaVista Software Inc.
  23  * Author: Manish Lachwani, mlachwani@mvista.com
  24  *
  25  *  This program is free software; you can redistribute it and/or modify it
  26  *  under the terms of the GNU General Public License as published by the
  27  *  Free Software Foundation; either version 2 of the License, or (at your
  28  *  option) any later version.
  29  *
  30  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  31  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  32  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  33  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  34  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  35  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  36  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  37  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  38  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  39  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  *  You should have received a copy of the GNU General Public License along
  42  *  with this program; if not, write to the Free Software Foundation, Inc.,
  43  *  675 Mass Ave, Cambridge, MA 02139, USA.
  44  */
  45 #include <linux/init.h>
  46 #include <linux/kernel.h>
  47 #include <linux/types.h>
  48 #include <linux/mm.h>
  49 #include <linux/swap.h>
  50 #include <linux/ioport.h>
  51 #include <linux/sched.h>
  52 #include <linux/interrupt.h>
  53 #include <linux/pci.h>
  54 #include <linux/timex.h>
  55 #include <linux/pm.h>
  56 #include <linux/platform_device.h>
  57
  58 #include <asm/bootinfo.h>
  59 #include <asm/page.h>
  60 #include <asm/io.h>
  61 #include <asm/irq.h>
  62 #include <asm/irq_regs.h>
  63 #include <asm/processor.h>
  64 #include <asm/reboot.h>
  65 #include <asm/time.h>
  66 #include <linux/bootmem.h>
  67 #include <linux/blkdev.h>
  68 #ifdef CONFIG_TOSHIBA_FPCIB0
  69 #include <asm/tx4927/smsc_fdc37m81x.h>
  70 #endif
  71 #include <asm/tx4927/toshiba_rbtx4927.h>
  72 #ifdef CONFIG_PCI
  73 #include <asm/tx4927/tx4927_pci.h>
  74 #endif
  75 #ifdef CONFIG_BLK_DEV_IDEPCI
  76 #include <linux/hdreg.h>
  77 #include <linux/ide.h>
  78 #endif
  79 #ifdef CONFIG_SERIAL_TXX9
  80 #include <linux/tty.h>
  81 #include <linux/serial.h>
  82 #include <linux/serial_core.h>
  83 #endif
  84
  85 #undef TOSHIBA_RBTX4927_SETUP_DEBUG
  86
  87 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
  88 #define TOSHIBA_RBTX4927_SETUP_NONE        0x00000000
  89
  90 #define TOSHIBA_RBTX4927_SETUP_INFO        ( 1 <<  0 )
  91 #define TOSHIBA_RBTX4927_SETUP_WARN        ( 1 <<  1 )
  92 #define TOSHIBA_RBTX4927_SETUP_EROR        ( 1 <<  2 )
  93
  94 #define TOSHIBA_RBTX4927_SETUP_EFWFU       ( 1 <<  3 )
  95 #define TOSHIBA_RBTX4927_SETUP_SETUP       ( 1 <<  4 )
  96 #define TOSHIBA_RBTX4927_SETUP_TIME_INIT   ( 1 <<  5 )
  97 #define TOSHIBA_RBTX4927_SETUP_TIMER_SETUP ( 1 <<  6 )
  98 #define TOSHIBA_RBTX4927_SETUP_PCIBIOS     ( 1 <<  7 )
  99 #define TOSHIBA_RBTX4927_SETUP_PCI1        ( 1 <<  8 )
 100 #define TOSHIBA_RBTX4927_SETUP_PCI2        ( 1 <<  9 )
 101 #define TOSHIBA_RBTX4927_SETUP_PCI66       ( 1 << 10 )
 102
 103 #define TOSHIBA_RBTX4927_SETUP_ALL         0xffffffff
 104 #endif
 105
 106 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 107 static const u32 toshiba_rbtx4927_setup_debug_flag =
 108     (TOSHIBA_RBTX4927_SETUP_NONE | TOSHIBA_RBTX4927_SETUP_INFO |
 109      TOSHIBA_RBTX4927_SETUP_WARN | TOSHIBA_RBTX4927_SETUP_EROR |
 110      TOSHIBA_RBTX4927_SETUP_EFWFU | TOSHIBA_RBTX4927_SETUP_SETUP |
 111      TOSHIBA_RBTX4927_SETUP_TIME_INIT | TOSHIBA_RBTX4927_SETUP_TIMER_SETUP
 112      | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 |
 113      TOSHIBA_RBTX4927_SETUP_PCI2 | TOSHIBA_RBTX4927_SETUP_PCI66);
 114 #endif
 115
 116 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 117 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) \
 118         if ( (toshiba_rbtx4927_setup_debug_flag) & (flag) ) \
 119         { \
 120            char tmp[100]; \
 121            sprintf( tmp, str ); \
 122            printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
 123         }
 124 #else
 125 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...)
 126 #endif
 127
 128 /* These functions are used for rebooting or halting the machine*/
 129 extern void toshiba_rbtx4927_restart(char *command);
 130 extern void toshiba_rbtx4927_halt(void);
 131 extern void toshiba_rbtx4927_power_off(void);
 132
 133 int tx4927_using_backplane = 0;
 134
 135 extern void gt64120_time_init(void);
 136 extern void toshiba_rbtx4927_irq_setup(void);
 137
 138 char *prom_getcmdline(void);
 139
 140 #ifdef CONFIG_PCI
 141 #undef TX4927_SUPPORT_COMMAND_IO
 142 #undef  TX4927_SUPPORT_PCI_66
 143 int tx4927_cpu_clock = 100000000;       /* 100MHz */
 144 unsigned long mips_pci_io_base;
 145 unsigned long mips_pci_io_size;
 146 unsigned long mips_pci_mem_base;
 147 unsigned long mips_pci_mem_size;
 148 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
 149 unsigned long mips_pci_io_pciaddr = 0;
 150 unsigned long mips_memory_upper;
 151 static int tx4927_ccfg_toeon = 1;
 152 static int tx4927_pcic_trdyto = 0;      /* default: disabled */
 153 unsigned long tx4927_ce_base[8];
 154 void tx4927_pci_setup(void);
 155 void tx4927_reset_pci_pcic(void);
 156 int tx4927_pci66 = 0;           /* 0:auto */
 157 #endif
 158
 159 char *toshiba_name = "";
 160
 161 #ifdef CONFIG_PCI
 162 static void tx4927_pcierr_interrupt(int irq, void *dev_id)
 163 {
 164 #ifdef CONFIG_BLK_DEV_IDEPCI
 165         /* ignore MasterAbort for ide probing... */
 166         if (irq == TX4927_IRQ_IRC_PCIERR &&
 167             ((tx4927_pcicptr->pcistatus >> 16) & 0xf900) ==
 168             PCI_STATUS_REC_MASTER_ABORT) {
 169                 tx4927_pcicptr->pcistatus =
 170                     (tx4927_pcicptr->
 171                      pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
 172                                                 << 16);
 173
 174                 return;
 175         }
 176 #endif
 177         printk("PCI error interrupt (irq 0x%x).\n", irq);
 178
 179         printk("pcistat:%04x, g2pstatus:%08lx, pcicstatus:%08lx\n",
 180                (unsigned short) (tx4927_pcicptr->pcistatus >> 16),
 181                tx4927_pcicptr->g2pstatus, tx4927_pcicptr->pcicstatus);
 182         printk("ccfg:%08lx, tear:%02lx_%08lx\n",
 183                (unsigned long) tx4927_ccfgptr->ccfg,
 184                (unsigned long) (tx4927_ccfgptr->tear >> 32),
 185                (unsigned long) tx4927_ccfgptr->tear);
 186         show_regs(get_irq_regs());
 187 }
 188
 189 void __init toshiba_rbtx4927_pci_irq_init(void)
 190 {
 191         return;
 192 }
 193
 194 void tx4927_reset_pci_pcic(void)
 195 {
 196         /* Reset PCI Bus */
 197         *tx4927_pcireset_ptr = 1;
 198         /* Reset PCIC */
 199         tx4927_ccfgptr->clkctr |= TX4927_CLKCTR_PCIRST;
 200         udelay(10000);
 201         /* clear PCIC reset */
 202         tx4927_ccfgptr->clkctr &= ~TX4927_CLKCTR_PCIRST;
 203         *tx4927_pcireset_ptr = 0;
 204 }
 205 #endif /* CONFIG_PCI */
 206
 207 #ifdef CONFIG_PCI
 208 void print_pci_status(void)
 209 {
 210         printk("PCI STATUS %lx\n", tx4927_pcicptr->pcistatus);
 211         printk("PCIC STATUS %lx\n", tx4927_pcicptr->pcicstatus);
 212 }
 213
 214 extern struct pci_controller tx4927_controller;
 215
 216 static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
 217                                     int top_bus, int busnr, int devfn)
 218 {
 219         static struct pci_dev dev;
 220         static struct pci_bus bus;
 221
 222         dev.sysdata = (void *)hose;
 223         dev.devfn = devfn;
 224         bus.number = busnr;
 225         bus.ops = hose->pci_ops;
 226         bus.parent = NULL;
 227         dev.bus = &bus;
 228
 229         return &dev;
 230 }
 231
 232 #define EARLY_PCI_OP(rw, size, type)                                    \
 233 static int early_##rw##_config_##size(struct pci_controller *hose,      \
 234         int top_bus, int bus, int devfn, int offset, type value)        \
 235 {                                                                       \
 236         return pci_##rw##_config_##size(                                \
 237                 fake_pci_dev(hose, top_bus, bus, devfn),                \
 238                 offset, value);                                         \
 239 }
 240
 241 EARLY_PCI_OP(read, byte, u8 *)
 242 EARLY_PCI_OP(read, word, u16 *)
 243 EARLY_PCI_OP(read, dword, u32 *)
 244 EARLY_PCI_OP(write, byte, u8)
 245 EARLY_PCI_OP(write, word, u16)
 246 EARLY_PCI_OP(write, dword, u32)
 247
 248 static int __init tx4927_pcibios_init(void)
 249 {
 250         unsigned int id;
 251         u32 pci_devfn;
 252         int devfn_start = 0;
 253         int devfn_stop = 0xff;
 254         int busno = 0; /* One bus on the Toshiba */
 255         struct pci_controller *hose = &tx4927_controller;
 256
 257         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 258                                        "-\n");
 259
 260         for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) {
 261                 early_read_config_dword(hose, busno, busno, pci_devfn,
 262                                         PCI_VENDOR_ID, &id);
 263
 264                 if (id == 0xffffffff) {
 265                         continue;
 266                 }
 267
 268                 if (id == 0x94601055) {
 269                         u8 v08_64;
 270                         u32 v32_b0;
 271                         u8 v08_e1;
 272                         char *s = " sb/isa --";
 273
 274                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 275                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
 276                              s);
 277
 278                         early_read_config_byte(hose, busno, busno,
 279                                                pci_devfn, 0x64, &v08_64);
 280                         early_read_config_dword(hose, busno, busno,
 281                                                 pci_devfn, 0xb0, &v32_b0);
 282                         early_read_config_byte(hose, busno, busno,
 283                                                pci_devfn, 0xe1, &v08_e1);
 284
 285                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 286                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 287                              ":%s beg 0x64 = 0x%02x\n", s, v08_64);
 288                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 289                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 290                              ":%s beg 0xb0 = 0x%02x\n", s, v32_b0);
 291                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 292                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 293                              ":%s beg 0xe1 = 0x%02x\n", s, v08_e1);
 294
 295                         /* serial irq control */
 296                         v08_64 = 0xd0;
 297
 298                         /* serial irq pin */
 299                         v32_b0 |= 0x00010000;
 300
 301                         /* ide irq on isa14 */
 302                         v08_e1 &= 0xf0;
 303                         v08_e1 |= 0x0d;
 304
 305                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 306                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 307                              ":%s mid 0x64 = 0x%02x\n", s, v08_64);
 308                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 309                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 310                              ":%s mid 0xb0 = 0x%02x\n", s, v32_b0);
 311                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 312                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 313                              ":%s mid 0xe1 = 0x%02x\n", s, v08_e1);
 314
 315                         early_write_config_byte(hose, busno, busno,
 316                                                 pci_devfn, 0x64, v08_64);
 317                         early_write_config_dword(hose, busno, busno,
 318                                                  pci_devfn, 0xb0, v32_b0);
 319                         early_write_config_byte(hose, busno, busno,
 320                                                 pci_devfn, 0xe1, v08_e1);
 321
 322 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 323                         {
 324                                 early_read_config_byte(hose, busno, busno,
 325                                                        pci_devfn, 0x64,
 326                                                        &v08_64);
 327                                 early_read_config_dword(hose, busno, busno,
 328                                                         pci_devfn, 0xb0,
 329                                                         &v32_b0);
 330                                 early_read_config_byte(hose, busno, busno,
 331                                                        pci_devfn, 0xe1,
 332                                                        &v08_e1);
 333
 334                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 335                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 336                                      ":%s end 0x64 = 0x%02x\n", s, v08_64);
 337                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 338                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 339                                      ":%s end 0xb0 = 0x%02x\n", s, v32_b0);
 340                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 341                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 342                                      ":%s end 0xe1 = 0x%02x\n", s, v08_e1);
 343                         }
 344 #endif
 345
 346                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 347                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
 348                              s);
 349                 }
 350
 351                 if (id == 0x91301055) {
 352                         u8 v08_04;
 353                         u8 v08_09;
 354                         u8 v08_41;
 355                         u8 v08_43;
 356                         u8 v08_5c;
 357                         char *s = " sb/ide --";
 358
 359                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 360                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
 361                              s);
 362
 363                         early_read_config_byte(hose, busno, busno,
 364                                                pci_devfn, 0x04, &v08_04);
 365                         early_read_config_byte(hose, busno, busno,
 366                                                pci_devfn, 0x09, &v08_09);
 367                         early_read_config_byte(hose, busno, busno,
 368                                                pci_devfn, 0x41, &v08_41);
 369                         early_read_config_byte(hose, busno, busno,
 370                                                pci_devfn, 0x43, &v08_43);
 371                         early_read_config_byte(hose, busno, busno,
 372                                                pci_devfn, 0x5c, &v08_5c);
 373
 374                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 375                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 376                              ":%s beg 0x04 = 0x%02x\n", s, v08_04);
 377                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 378                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 379                              ":%s beg 0x09 = 0x%02x\n", s, v08_09);
 380                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 381                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 382                              ":%s beg 0x41 = 0x%02x\n", s, v08_41);
 383                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 384                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 385                              ":%s beg 0x43 = 0x%02x\n", s, v08_43);
 386                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 387                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 388                              ":%s beg 0x5c = 0x%02x\n", s, v08_5c);
 389
 390                         /* enable ide master/io */
 391                         v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);
 392
 393                         /* enable ide native mode */
 394                         v08_09 |= 0x05;
 395
 396                         /* enable primary ide */
 397                         v08_41 |= 0x80;
 398
 399                         /* enable secondary ide */
 400                         v08_43 |= 0x80;
 401
 402                         /*
 403                          * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
 404                          *
 405                          * This line of code is intended to provide the user with a work
 406                          * around solution to the anomalies cited in SMSC's anomaly sheet
 407                          * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
 408                          *
 409                          * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
 410                          */
 411                         v08_5c |= 0x01;
 412
 413                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 414                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 415                              ":%s mid 0x04 = 0x%02x\n", s, v08_04);
 416                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 417                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 418                              ":%s mid 0x09 = 0x%02x\n", s, v08_09);
 419                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 420                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 421                              ":%s mid 0x41 = 0x%02x\n", s, v08_41);
 422                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 423                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 424                              ":%s mid 0x43 = 0x%02x\n", s, v08_43);
 425                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 426                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 427                              ":%s mid 0x5c = 0x%02x\n", s, v08_5c);
 428
 429                         early_write_config_byte(hose, busno, busno,
 430                                                 pci_devfn, 0x5c, v08_5c);
 431                         early_write_config_byte(hose, busno, busno,
 432                                                 pci_devfn, 0x04, v08_04);
 433                         early_write_config_byte(hose, busno, busno,
 434                                                 pci_devfn, 0x09, v08_09);
 435                         early_write_config_byte(hose, busno, busno,
 436                                                 pci_devfn, 0x41, v08_41);
 437                         early_write_config_byte(hose, busno, busno,
 438                                                 pci_devfn, 0x43, v08_43);
 439
 440 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 441                         {
 442                                 early_read_config_byte(hose, busno, busno,
 443                                                        pci_devfn, 0x04,
 444                                                        &v08_04);
 445                                 early_read_config_byte(hose, busno, busno,
 446                                                        pci_devfn, 0x09,
 447                                                        &v08_09);
 448                                 early_read_config_byte(hose, busno, busno,
 449                                                        pci_devfn, 0x41,
 450                                                        &v08_41);
 451                                 early_read_config_byte(hose, busno, busno,
 452                                                        pci_devfn, 0x43,
 453                                                        &v08_43);
 454                                 early_read_config_byte(hose, busno, busno,
 455                                                        pci_devfn, 0x5c,
 456                                                        &v08_5c);
 457
 458                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 459                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 460                                      ":%s end 0x04 = 0x%02x\n", s, v08_04);
 461                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 462                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 463                                      ":%s end 0x09 = 0x%02x\n", s, v08_09);
 464                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 465                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 466                                      ":%s end 0x41 = 0x%02x\n", s, v08_41);
 467                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 468                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 469                                      ":%s end 0x43 = 0x%02x\n", s, v08_43);
 470                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 471                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 472                                      ":%s end 0x5c = 0x%02x\n", s, v08_5c);
 473                         }
 474 #endif
 475
 476                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 477                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
 478                              s);
 479                 }
 480
 481         }
 482
 483         register_pci_controller(&tx4927_controller);
 484         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 485                                        "+\n");
 486
 487         return 0;
 488 }
 489
 490 arch_initcall(tx4927_pcibios_init);
 491
 492 extern struct resource pci_io_resource;
 493 extern struct resource pci_mem_resource;
 494
 495 void tx4927_pci_setup(void)
 496 {
 497         static int called = 0;
 498         extern unsigned int tx4927_get_mem_size(void);
 499
 500         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n");
 501
 502         mips_memory_upper = tx4927_get_mem_size() << 20;
 503         mips_memory_upper += KSEG0;
 504         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 505                                        "0x%08lx=mips_memory_upper\n",
 506                                        mips_memory_upper);
 507         mips_pci_io_base = TX4927_PCIIO;
 508         mips_pci_io_size = TX4927_PCIIO_SIZE;
 509         mips_pci_mem_base = TX4927_PCIMEM;
 510         mips_pci_mem_size = TX4927_PCIMEM_SIZE;
 511
 512         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 513                                        "0x%08lx=mips_pci_io_base\n",
 514                                        mips_pci_io_base);
 515         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 516                                        "0x%08lx=mips_pci_io_size\n",
 517                                        mips_pci_io_size);
 518         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 519                                        "0x%08lx=mips_pci_mem_base\n",
 520                                        mips_pci_mem_base);
 521         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 522                                        "0x%08lx=mips_pci_mem_size\n",
 523                                        mips_pci_mem_size);
 524         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 525                                        "0x%08lx=pci_io_resource.start\n",
 526                                        pci_io_resource.start);
 527         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 528                                        "0x%08lx=pci_io_resource.end\n",
 529                                        pci_io_resource.end);
 530         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 531                                        "0x%08lx=pci_mem_resource.start\n",
 532                                        pci_mem_resource.start);
 533         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 534                                        "0x%08lx=pci_mem_resource.end\n",
 535                                        pci_mem_resource.end);
 536         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 537                                        "0x%08lx=mips_io_port_base",
 538                                        mips_io_port_base);
 539         if (!called) {
 540                 printk
 541                     ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
 542                      toshiba_name,
 543                      (unsigned short) (tx4927_pcicptr->pciid >> 16),
 544                      (unsigned short) (tx4927_pcicptr->pciid & 0xffff),
 545                      (unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
 546                      (!(tx4927_ccfgptr->
 547                         ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
 548                      "Internal");
 549                 called = 1;
 550         }
 551         printk("%s PCIC --%s PCICLK:",toshiba_name,
 552                (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
 553         if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
 554                 int pciclk = 0;
 555                 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
 556                         switch ((unsigned long) tx4927_ccfgptr->
 557                                 ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
 558                         case TX4937_CCFG_PCIDIVMODE_4:
 559                                 pciclk = tx4927_cpu_clock / 4;
 560                                 break;
 561                         case TX4937_CCFG_PCIDIVMODE_4_5:
 562                                 pciclk = tx4927_cpu_clock * 2 / 9;
 563                                 break;
 564                         case TX4937_CCFG_PCIDIVMODE_5:
 565                                 pciclk = tx4927_cpu_clock / 5;
 566                                 break;
 567                         case TX4937_CCFG_PCIDIVMODE_5_5:
 568                                 pciclk = tx4927_cpu_clock * 2 / 11;
 569                                 break;
 570                         case TX4937_CCFG_PCIDIVMODE_8:
 571                                 pciclk = tx4927_cpu_clock / 8;
 572                                 break;
 573                         case TX4937_CCFG_PCIDIVMODE_9:
 574                                 pciclk = tx4927_cpu_clock / 9;
 575                                 break;
 576                         case TX4937_CCFG_PCIDIVMODE_10:
 577                                 pciclk = tx4927_cpu_clock / 10;
 578                                 break;
 579                         case TX4937_CCFG_PCIDIVMODE_11:
 580                                 pciclk = tx4927_cpu_clock / 11;
 581                                 break;
 582                         }
 583
 584                 else
 585                         switch ((unsigned long) tx4927_ccfgptr->
 586                                 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
 587                         case TX4927_CCFG_PCIDIVMODE_2_5:
 588                                 pciclk = tx4927_cpu_clock * 2 / 5;
 589                                 break;
 590                         case TX4927_CCFG_PCIDIVMODE_3:
 591                                 pciclk = tx4927_cpu_clock / 3;
 592                                 break;
 593                         case TX4927_CCFG_PCIDIVMODE_5:
 594                                 pciclk = tx4927_cpu_clock / 5;
 595                                 break;
 596                         case TX4927_CCFG_PCIDIVMODE_6:
 597                                 pciclk = tx4927_cpu_clock / 6;
 598                                 break;
 599                         }
 600
 601                 printk("Internal(%dMHz)", pciclk / 1000000);
 602         } else {
 603                 int pciclk = 0;
 604                 int pciclk_setting = *tx4927_pci_clk_ptr;
 605                 switch (pciclk_setting & TX4927_PCI_CLK_MASK) {
 606                 case TX4927_PCI_CLK_33:
 607                         pciclk = 33333333;
 608                         break;
 609                 case TX4927_PCI_CLK_25:
 610                         pciclk = 25000000;
 611                         break;
 612                 case TX4927_PCI_CLK_66:
 613                         pciclk = 66666666;
 614                         break;
 615                 case TX4927_PCI_CLK_50:
 616                         pciclk = 50000000;
 617                         break;
 618                 }
 619                 printk("External(%dMHz)", pciclk / 1000000);
 620         }
 621         printk("\n");
 622
 623
 624
 625         /* GB->PCI mappings */
 626         tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
 627         tx4927_pcicptr->g2piogbase = mips_pci_io_base |
 628 #ifdef __BIG_ENDIAN
 629             TX4927_PCIC_G2PIOGBASE_ECHG
 630 #else
 631             TX4927_PCIC_G2PIOGBASE_BSDIS
 632 #endif
 633             ;
 634
 635         tx4927_pcicptr->g2piopbase = 0;
 636
 637         tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
 638         tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
 639 #ifdef __BIG_ENDIAN
 640             TX4927_PCIC_G2PMnGBASE_ECHG
 641 #else
 642             TX4927_PCIC_G2PMnGBASE_BSDIS
 643 #endif
 644             ;
 645         tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;
 646
 647         tx4927_pcicptr->g2pmmask[1] = 0;
 648         tx4927_pcicptr->g2pmgbase[1] = 0;
 649         tx4927_pcicptr->g2pmpbase[1] = 0;
 650         tx4927_pcicptr->g2pmmask[2] = 0;
 651         tx4927_pcicptr->g2pmgbase[2] = 0;
 652         tx4927_pcicptr->g2pmpbase[2] = 0;
 653
 654
 655         /* PCI->GB mappings (I/O 256B) */
 656         tx4927_pcicptr->p2giopbase = 0; /* 256B */
 657
 658         /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
 659         tx4927_pcicptr->p2gm0plbase = 0;
 660         tx4927_pcicptr->p2gm0pubase = 0;
 661         tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
 662 #ifdef __BIG_ENDIAN
 663             TX4927_PCIC_P2GMnGBASE_TECHG
 664 #else
 665             TX4927_PCIC_P2GMnGBASE_TBSDIS
 666 #endif
 667             ;
 668
 669         /* PCI->GB mappings (MEM 16MB) -not used */
 670         tx4927_pcicptr->p2gm1plbase = 0xffffffff;
 671         tx4927_pcicptr->p2gm1pubase = 0xffffffff;
 672         tx4927_pcicptr->p2gmgbase[1] = 0;
 673
 674         /* PCI->GB mappings (MEM 1MB) -not used */
 675         tx4927_pcicptr->p2gm2pbase = 0xffffffff;
 676         tx4927_pcicptr->p2gmgbase[2] = 0;
 677
 678
 679         /* Enable Initiator Memory 0 Space, I/O Space, Config */
 680         tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK;
 681         tx4927_pcicptr->pciccfg |=
 682             TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE |
 683             TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR;
 684
 685
 686         /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
 687         tx4927_pcicptr->pcicfg1 = 0;
 688
 689         if (tx4927_pcic_trdyto >= 0) {
 690                 tx4927_pcicptr->g2ptocnt &= ~0xff;
 691                 tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff);
 692         }
 693
 694         /* Clear All Local Bus Status */
 695         tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL;
 696         /* Enable All Local Bus Interrupts */
 697         tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL;
 698         /* Clear All Initiator Status */
 699         tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL;
 700         /* Enable All Initiator Interrupts */
 701         tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL;
 702         /* Clear All PCI Status Error */
 703         tx4927_pcicptr->pcistatus =
 704             (tx4927_pcicptr->pcistatus & 0x0000ffff) |
 705             (TX4927_PCIC_PCISTATUS_ALL << 16);
 706         /* Enable All PCI Status Error Interrupts */
 707         tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL;
 708
 709         /* PCIC Int => IRC IRQ16 */
 710         tx4927_pcicptr->pcicfg2 =
 711             (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC;
 712
 713         if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) {
 714                 /* XXX */
 715         } else {
 716                 /* Reset Bus Arbiter */
 717                 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA;
 718                 /* Enable Bus Arbiter */
 719                 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
 720         }
 721
 722         tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
 723             PCI_COMMAND_MEMORY |
 724             PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
 725
 726         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 727                                        ":pci setup complete:\n");
 728         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n");
 729 }
 730
 731 #endif /* CONFIG_PCI */
 732
 733 void toshiba_rbtx4927_restart(char *command)
 734 {
 735         printk(KERN_NOTICE "System Rebooting...\n");
 736
 737         /* enable the s/w reset register */
 738         reg_wr08(RBTX4927_SW_RESET_ENABLE, RBTX4927_SW_RESET_ENABLE_SET);
 739
 740         /* wait for enable to be seen */
 741         while ((reg_rd08(RBTX4927_SW_RESET_ENABLE) &
 742                 RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
 743
 744         /* do a s/w reset */
 745         reg_wr08(RBTX4927_SW_RESET_DO, RBTX4927_SW_RESET_DO_SET);
 746
 747         /* do something passive while waiting for reset */
 748         local_irq_disable();
 749         while (1)
 750                 asm_wait();
 751
 752         /* no return */
 753 }
 754
 755
 756 void toshiba_rbtx4927_halt(void)
 757 {
 758         printk(KERN_NOTICE "System Halted\n");
 759         local_irq_disable();
 760         while (1) {
 761                 asm_wait();
 762         }
 763         /* no return */
 764 }
 765
 766 void toshiba_rbtx4927_power_off(void)
 767 {
 768         toshiba_rbtx4927_halt();
 769         /* no return */
 770 }
 771
 772 void __init toshiba_rbtx4927_setup(void)
 773 {
 774         vu32 cp0_config;
 775         char *argptr;
 776
 777         printk("CPU is %s\n", toshiba_name);
 778
 779         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 780                                        "-\n");
 781
 782         /* f/w leaves this on at startup */
 783         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 784                                        ":Clearing STO_ERL.\n");
 785         clear_c0_status(ST0_ERL);
 786
 787         /* enable caches -- HCP5 does this, pmon does not */
 788         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 789                                        ":Enabling TX49_CONF_IC,TX49_CONF_DC.\n");
 790         cp0_config = read_c0_config();
 791         cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
 792         write_c0_config(cp0_config);
 793
 794 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 795         {
 796                 extern void dump_cp0(char *);
 797                 dump_cp0("toshiba_rbtx4927_early_fw_fixup");
 798         }
 799 #endif
 800
 801         /* setup irq stuff */
 802         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 803                                        ":Setting up tx4927 pic.\n");
 804         TX4927_WR(0xff1ff604, 0x00000400);      /* irq trigger */
 805         TX4927_WR(0xff1ff608, 0x00000000);      /* irq trigger */
 806
 807         /* setup serial stuff */
 808         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 809                                        ":Setting up tx4927 sio.\n");
 810         TX4927_WR(0xff1ff314, 0x00000000);      /* h/w flow control off */
 811         TX4927_WR(0xff1ff414, 0x00000000);      /* h/w flow control off */
 812
 813         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 814                                        "+\n");
 815
 816         set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
 817         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 818                                        ":mips_io_port_base=0x%08lx\n",
 819                                        mips_io_port_base);
 820
 821         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 822                                        ":Resource\n");
 823         ioport_resource.end = 0xffffffff;
 824         iomem_resource.end = 0xffffffff;
 825
 826         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 827                                        ":ResetRoutines\n");
 828         _machine_restart = toshiba_rbtx4927_restart;
 829         _machine_halt = toshiba_rbtx4927_halt;
 830         pm_power_off = toshiba_rbtx4927_power_off;
 831
 832 #ifdef CONFIG_PCI
 833
 834         /* PCIC */
 835         /*
 836            * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
 837            *
 838            * For TX4927:
 839            * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
 840            * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
 841            * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
 842            * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
 843            * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
 844            * i.e. S9[3]: ON (83MHz), OFF (100MHz)
 845            *
 846            * For TX4937:
 847            * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
 848            * PCIDIVMODE[10] is 0.
 849            * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
 850            * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
 851            * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
 852            * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
 853            * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
 854            * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
 855            *
 856          */
 857         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
 858                                        "ccfg is %lx, PCIDIVMODE is %x\n",
 859                                        (unsigned long) tx4927_ccfgptr->ccfg,
 860                                        (unsigned long) tx4927_ccfgptr->ccfg &
 861                                        (mips_machtype == MACH_TOSHIBA_RBTX4937 ?
 862                                         TX4937_CCFG_PCIDIVMODE_MASK :
 863                                         TX4927_CCFG_PCIDIVMODE_MASK));
 864
 865         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
 866                                        "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n",
 867                                        (unsigned long) tx4927_ccfgptr->
 868                                        ccfg & TX4927_CCFG_PCI66,
 869                                        (unsigned long) tx4927_ccfgptr->
 870                                        ccfg & TX4927_CCFG_PCIMIDE,
 871                                        (unsigned long) tx4927_ccfgptr->
 872                                        ccfg & TX4927_CCFG_PCIXARB);
 873
 874         if (mips_machtype == MACH_TOSHIBA_RBTX4937)
 875                 switch ((unsigned long)tx4927_ccfgptr->
 876                         ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
 877                 case TX4937_CCFG_PCIDIVMODE_8:
 878                 case TX4937_CCFG_PCIDIVMODE_4:
 879                         tx4927_cpu_clock = 266666666;   /* 266MHz */
 880                         break;
 881                 case TX4937_CCFG_PCIDIVMODE_9:
 882                 case TX4937_CCFG_PCIDIVMODE_4_5:
 883                         tx4927_cpu_clock = 300000000;   /* 300MHz */
 884                         break;
 885                 default:
 886                         tx4927_cpu_clock = 333333333;   /* 333MHz */
 887                 }
 888         else
 889                 switch ((unsigned long)tx4927_ccfgptr->
 890                         ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
 891                 case TX4927_CCFG_PCIDIVMODE_2_5:
 892                 case TX4927_CCFG_PCIDIVMODE_5:
 893                         tx4927_cpu_clock = 166666666;   /* 166MHz */
 894                         break;
 895                 default:
 896                         tx4927_cpu_clock = 200000000;   /* 200MHz */
 897                 }
 898
 899         /* CCFG */
 900         /* enable Timeout BusError */
 901         if (tx4927_ccfg_toeon)
 902                 tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE;
 903
 904         tx4927_pci_setup();
 905         if (tx4927_using_backplane == 1)
 906                 printk("backplane board IS installed\n");
 907         else
 908                 printk("No Backplane \n");
 909
 910         /* this is on ISA bus behind PCI bus, so need PCI up first */
 911 #ifdef CONFIG_TOSHIBA_FPCIB0
 912         {
 913                 if (tx4927_using_backplane) {
 914                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 915                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 916                              ":fpcibo=yes\n");
 917
 918                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 919                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 920                              ":smsc_fdc37m81x_init()\n");
 921                         smsc_fdc37m81x_init(0x3f0);
 922
 923                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 924                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 925                              ":smsc_fdc37m81x_config_beg()\n");
 926                         smsc_fdc37m81x_config_beg();
 927
 928                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 929                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 930                              ":smsc_fdc37m81x_config_set(KBD)\n");
 931                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
 932                                                   SMSC_FDC37M81X_KBD);
 933                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
 934                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
 935                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
 936                                                   1);
 937
 938                         smsc_fdc37m81x_config_end();
 939                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 940                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 941                              ":smsc_fdc37m81x_config_end()\n");
 942                 } else {
 943                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 944                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 945                              ":fpcibo=not_found\n");
 946                 }
 947         }
 948 #else
 949         {
 950                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 951                     (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n");
 952         }
 953 #endif
 954
 955 #endif /* CONFIG_PCI */
 956
 957 #ifdef CONFIG_SERIAL_TXX9
 958         {
 959                 extern int early_serial_txx9_setup(struct uart_port *port);
 960                 int i;
 961                 struct uart_port req;
 962                 for(i = 0; i < 2; i++) {
 963                         memset(&req, 0, sizeof(req));
 964                         req.line = i;
 965                         req.iotype = UPIO_MEM;
 966                         req.membase = (char *)(0xff1ff300 + i * 0x100);
 967                         req.mapbase = 0xff1ff300 + i * 0x100;
 968                         req.irq = 32 + i;
 969                         req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
 970                         req.uartclk = 50000000;
 971                         early_serial_txx9_setup(&req);
 972                 }
 973         }
 974 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
 975         argptr = prom_getcmdline();
 976         if (strstr(argptr, "console=") == NULL) {
 977                 strcat(argptr, " console=ttyS0,38400");
 978         }
 979 #endif
 980 #endif
 981
 982 #ifdef CONFIG_ROOT_NFS
 983         argptr = prom_getcmdline();
 984         if (strstr(argptr, "root=") == NULL) {
 985                 strcat(argptr, " root=/dev/nfs rw");
 986         }
 987 #endif
 988
 989
 990 #ifdef CONFIG_IP_PNP
 991         argptr = prom_getcmdline();
 992         if (strstr(argptr, "ip=") == NULL) {
 993                 strcat(argptr, " ip=any");
 994         }
 995 #endif
 996
 997
 998         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 999                                "+\n");
1000 }
1001
1002 void __init
1003 toshiba_rbtx4927_time_init(void)
1004 {
1005         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "-\n");
1006
1007         mips_hpt_frequency = tx4927_cpu_clock / 2;
1008
1009         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "+\n");
1010
1011 }
1012
1013 void __init toshiba_rbtx4927_timer_setup(struct irqaction *irq)
1014 {
1015         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
1016                                        "-\n");
1017         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
1018                                        "+\n");
1019 }
1020
1021 static int __init toshiba_rbtx4927_rtc_init(void)
1022 {
1023         struct resource res = {
1024                 .start  = 0x1c010000,
1025                 .end    = 0x1c010000 + 0x800 - 1,
1026                 .flags  = IORESOURCE_MEM,
1027         };
1028         struct platform_device *dev =
1029                 platform_device_register_simple("ds1742", -1, &res, 1);
1030         return IS_ERR(dev) ? PTR_ERR(dev) : 0;
1031 }
1032 device_initcall(toshiba_rbtx4927_rtc_init);
1033
1034 static int __init rbtx4927_ne_init(void)
1035 {
1036         static struct resource __initdata res[] = {
1037                 {
1038                         .start  = RBTX4927_RTL_8019_BASE,
1039                         .end    = RBTX4927_RTL_8019_BASE + 0x20 - 1,
1040                         .flags  = IORESOURCE_IO,
1041                 }, {
1042                         .start  = RBTX4927_RTL_8019_IRQ,
1043                         .flags  = IORESOURCE_IRQ,
1044                 }
1045         };
1046         struct platform_device *dev =
1047                 platform_device_register_simple("ne", -1,
1048                                                 res, ARRAY_SIZE(res));
1049         return IS_ERR(dev) ? PTR_ERR(dev) : 0;
1050 }
1051 device_initcall(rbtx4927_ne_init);