2 * linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
4 * Toshiba RBTX4927 specific interrupt handlers
6 * Author: MontaVista Software, Inc.
9 * Copyright 2001-2002 MontaVista Software Inc.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
24 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 01 RBTX4927-ISA/01 PS2/Keyboard
37 02 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15)
47 12 RBTX4927-ISA/12 PS2/Mouse (not supported at this time)
49 14 RBTX4927-ISA/14 IDE
52 16 TX4927-CP0/00 Software 0
53 17 TX4927-CP0/01 Software 1
54 18 TX4927-CP0/02 Cascade TX4927-CP0
55 19 TX4927-CP0/03 Multiplexed -- do not use
56 20 TX4927-CP0/04 Multiplexed -- do not use
57 21 TX4927-CP0/05 Multiplexed -- do not use
58 22 TX4927-CP0/06 Multiplexed -- do not use
59 23 TX4927-CP0/07 CPU TIMER
64 27 TX4927-PIC/03 Cascade RBTX4927-IOC
66 29 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet
69 32 TX4927-PIC/08 TX4927 SerialIO Channel 0
70 33 TX4927-PIC/09 TX4927 SerialIO Channel 1
77 40 TX4927-PIC/16 TX4927 PCI PCI-C
83 46 TX4927-PIC/22 TX4927 PCI PCI-ERR
84 47 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used)
94 56 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed) [RTL-8139=PJ4]
95 57 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed) [RTL-8139=PJ5]
96 58 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported]
97 59 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4) [RTL-8139=PJ6]
104 SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58
105 SouthBridge/ISA/pin=0 no pci irq used by this device
106 SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14
107 SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59
108 SouthBridge/PMC/pin=0 no pci irq used by this device
109 SuperIO/PS2/Keyboard, using INTR via ISA IRQ1
110 SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported)
111 JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6
114 #include <linux/init.h>
115 #include <linux/kernel.h>
116 #include <linux/types.h>
117 #include <linux/mm.h>
118 #include <linux/swap.h>
119 #include <linux/ioport.h>
120 #include <linux/sched.h>
121 #include <linux/interrupt.h>
122 #include <linux/pci.h>
123 #include <linux/timex.h>
124 #include <asm/bootinfo.h>
125 #include <asm/page.h>
129 #include <asm/processor.h>
130 #include <asm/reboot.h>
131 #include <asm/time.h>
132 #include <asm/wbflush.h>
133 #include <linux/bootmem.h>
134 #include <linux/blkdev.h>
135 #ifdef CONFIG_RTC_DS1742
136 #include <linux/ds1742rtc.h>
138 #ifdef CONFIG_TOSHIBA_FPCIB0
139 #include <asm/tx4927/smsc_fdc37m81x.h>
141 #include <asm/tx4927/toshiba_rbtx4927.h>
144 #undef TOSHIBA_RBTX4927_IRQ_DEBUG
146 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
147 #define TOSHIBA_RBTX4927_IRQ_NONE 0x00000000
149 #define TOSHIBA_RBTX4927_IRQ_INFO ( 1 << 0 )
150 #define TOSHIBA_RBTX4927_IRQ_WARN ( 1 << 1 )
151 #define TOSHIBA_RBTX4927_IRQ_EROR ( 1 << 2 )
153 #define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 )
154 #define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 )
155 #define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 )
157 #define TOSHIBA_RBTX4927_IRQ_ISA_INIT ( 1 << 20 )
158 #define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 )
159 #define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE ( 1 << 24 )
160 #define TOSHIBA_RBTX4927_IRQ_ISA_MASK ( 1 << 25 )
161 #define TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ ( 1 << 26 )
163 #define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff
167 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
168 static const u32 toshiba_rbtx4927_irq_debug_flag =
169 (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO |
170 TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR
171 // | TOSHIBA_RBTX4927_IRQ_IOC_INIT
172 // | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
173 // | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
174 // | TOSHIBA_RBTX4927_IRQ_ISA_INIT
175 // | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE
176 // | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE
177 // | TOSHIBA_RBTX4927_IRQ_ISA_MASK
178 // | TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ
183 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
184 #define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...) \
185 if ( (toshiba_rbtx4927_irq_debug_flag) & (flag) ) \
188 sprintf( tmp, str ); \
189 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
192 #define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...)
198 #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0
199 #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END 7
201 #define TOSHIBA_RBTX4927_IRQ_IOC_BEG ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */
202 #define TOSHIBA_RBTX4927_IRQ_IOC_END ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */
205 #define TOSHIBA_RBTX4927_IRQ_ISA_BEG MI8259_IRQ_ISA_BEG
206 #define TOSHIBA_RBTX4927_IRQ_ISA_END MI8259_IRQ_ISA_END
207 #define TOSHIBA_RBTX4927_IRQ_ISA_MID ((TOSHIBA_RBTX4927_IRQ_ISA_BEG+TOSHIBA_RBTX4927_IRQ_ISA_END+1)/2)
210 #define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC
211 #define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2)
212 #define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA (TOSHIBA_RBTX4927_IRQ_ISA_BEG+2)
214 extern int tx4927_using_backplane;
216 #ifdef CONFIG_TOSHIBA_FPCIB0
217 extern void enable_8259A_irq(unsigned int irq);
218 extern void disable_8259A_irq(unsigned int irq);
219 extern void mask_and_ack_8259A(unsigned int irq);
222 static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
223 static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
225 #ifdef CONFIG_TOSHIBA_FPCIB0
226 static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq);
227 static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq);
228 static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq);
229 static void toshiba_rbtx4927_irq_isa_end(unsigned int irq);
232 #define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
233 static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
234 .typename = TOSHIBA_RBTX4927_IOC_NAME,
235 .ack = toshiba_rbtx4927_irq_ioc_disable,
236 .mask = toshiba_rbtx4927_irq_ioc_disable,
237 .mask_ack = toshiba_rbtx4927_irq_ioc_disable,
238 .unmask = toshiba_rbtx4927_irq_ioc_enable,
240 #define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000
241 #define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006
244 #ifdef CONFIG_TOSHIBA_FPCIB0
245 #define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA"
246 static struct irq_chip toshiba_rbtx4927_irq_isa_type = {
247 .typename = TOSHIBA_RBTX4927_ISA_NAME,
248 .ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
249 .mask = toshiba_rbtx4927_irq_isa_disable,
250 .mask_ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
251 .unmask = toshiba_rbtx4927_irq_isa_enable,
252 .end = toshiba_rbtx4927_irq_isa_end,
261 for (i = 0; i < (sizeof(num) * 8); i++) {
262 if (num & (1 << i)) {
269 int toshiba_rbtx4927_irq_nested(int sw_irq)
275 level3 = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
277 sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3);
278 if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) {
282 #ifdef CONFIG_TOSHIBA_FPCIB0
284 if (tx4927_using_backplane) {
286 level4 = inb(0x20) & 0xff;
289 TOSHIBA_RBTX4927_IRQ_ISA_BEG +
292 TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA) {
298 level5 = inb(0xA0) & 0xff;
301 TOSHIBA_RBTX4927_IRQ_ISA_MID +
313 //#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL }
314 #define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, IRQF_SHARED, CPU_MASK_NONE, s, NULL, NULL }
315 static struct irqaction toshiba_rbtx4927_irq_ioc_action =
316 TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_IOC_NAME);
317 #ifdef CONFIG_TOSHIBA_FPCIB0
318 static struct irqaction toshiba_rbtx4927_irq_isa_master =
319 TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/M");
320 static struct irqaction toshiba_rbtx4927_irq_isa_slave =
321 TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/S");
325 /**********************************************************************************/
326 /* Functions for ioc */
327 /**********************************************************************************/
330 static void __init toshiba_rbtx4927_irq_ioc_init(void)
334 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_INIT,
336 TOSHIBA_RBTX4927_IRQ_IOC_BEG,
337 TOSHIBA_RBTX4927_IRQ_IOC_END);
339 for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG;
340 i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++)
341 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
344 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC,
345 &toshiba_rbtx4927_irq_ioc_action);
348 static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
350 volatile unsigned char v;
352 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE,
355 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
356 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
357 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
358 "bad irq=%d\n", irq);
362 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
363 v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
364 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
368 static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
370 volatile unsigned char v;
372 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE,
375 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
376 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
377 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
378 "bad irq=%d\n", irq);
382 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
383 v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
384 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
388 /**********************************************************************************/
389 /* Functions for isa */
390 /**********************************************************************************/
393 #ifdef CONFIG_TOSHIBA_FPCIB0
394 static void __init toshiba_rbtx4927_irq_isa_init(void)
398 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_INIT,
400 TOSHIBA_RBTX4927_IRQ_ISA_BEG,
401 TOSHIBA_RBTX4927_IRQ_ISA_END);
403 for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG;
404 i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++)
405 set_irq_chip(i, &toshiba_rbtx4927_irq_isa_type);
407 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC,
408 &toshiba_rbtx4927_irq_isa_master);
409 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA,
410 &toshiba_rbtx4927_irq_isa_slave);
412 /* make sure we are looking at IRR (not ISR) */
419 #ifdef CONFIG_TOSHIBA_FPCIB0
420 static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq)
422 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENABLE,
425 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
426 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
427 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
428 "bad irq=%d\n", irq);
432 enable_8259A_irq(irq);
437 #ifdef CONFIG_TOSHIBA_FPCIB0
438 static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq)
440 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_DISABLE,
443 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
444 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
445 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
446 "bad irq=%d\n", irq);
450 disable_8259A_irq(irq);
455 #ifdef CONFIG_TOSHIBA_FPCIB0
456 static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq)
458 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_MASK,
461 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
462 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
463 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
464 "bad irq=%d\n", irq);
468 mask_and_ack_8259A(irq);
473 #ifdef CONFIG_TOSHIBA_FPCIB0
474 static void toshiba_rbtx4927_irq_isa_end(unsigned int irq)
476 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ,
479 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
480 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
481 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
482 "bad irq=%d\n", irq);
486 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
487 toshiba_rbtx4927_irq_isa_enable(irq);
493 void __init arch_init_irq(void)
495 extern void tx4927_irq_init(void);
498 toshiba_rbtx4927_irq_ioc_init();
499 #ifdef CONFIG_TOSHIBA_FPCIB0
501 if (tx4927_using_backplane) {
502 toshiba_rbtx4927_irq_isa_init();
510 void toshiba_rbtx4927_irq_dump(char *key)
512 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
515 for (i = 0; i < NR_IRQS; i++) {
516 if (strcmp(irq_desc[i].chip->typename, "none")
521 && (irq_desc[i - 1].chip->typename ==
522 irq_desc[i].chip->typename)) {
527 TOSHIBA_RBTX4927_IRQ_DPRINTK
528 (TOSHIBA_RBTX4927_IRQ_INFO,
529 "%s irq=0x%02x/%3d s=0x%08x h=0x%08x a=0x%08x ah=0x%08x d=%1d n=%s/%02d\n",
530 key, i, i, irq_desc[i].status,
531 (u32) irq_desc[i].chip,
532 (u32) irq_desc[i].action,
533 (u32) (irq_desc[i].action ? irq_desc[i].
534 action->handler : 0),
536 irq_desc[i].chip->typename, j);
542 void toshiba_rbtx4927_irq_dump_pics(char *s)
561 level0_m = (read_c0_status() & 0x0000ff00) >> 8;
562 level0_s = (read_c0_cause() & 0x0000ff00) >> 8;
565 level1_s = level0_s & 0x87;
567 level2 = TX4927_RD(0xff1ff6a0);
568 level2_p = (((level2 & 0x10000)) ? 0 : 1);
569 level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f));
571 level3_m = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f;
572 level3_s = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
574 level4_m = inb(0x21);
576 level4_s = inb(0x20);
578 level5_m = inb(0xa1);
580 level5_s = inb(0xa0);
582 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
584 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
585 "cp0:m=0x%02x/s=0x%02x ", level0_m,
587 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
588 "cp0:m=0x%02x/s=0x%02x ", level1_m,
590 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
591 "pic:e=0x%02x/s=0x%02x ", level2_p,
593 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
594 "ioc:m=0x%02x/s=0x%02x ", level3_m,
596 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
597 "sbm:m=0x%02x/s=0x%02x ", level4_m,
599 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
600 "sbs:m=0x%02x/s=0x%02x ", level5_m,
602 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n",