2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * A small micro-assembler. It is intentionally kept simple, does only
7 * support a subset of instructions, and does not try to hide pipeline
8 * effects like branch delay slots.
10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
11 * Copyright (C) 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/init.h>
48 #define IMM_MASK 0xffff
50 #define JIMM_MASK 0x3ffffff
52 #define FUNC_MASK 0x3f
56 #define SCIMM_MASK 0xfffff
61 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
62 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
63 insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
64 insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
65 insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret,
66 insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld,
67 insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori,
68 insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
69 insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp,
70 insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
71 insn_dins, insn_syscall, insn_bbit0, insn_bbit1
80 /* This macro sets the non-variable bits of an instruction. */
81 #define M(a, b, c, d, e, f) \
89 static struct insn insn_table[] __cpuinitdata = {
90 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
91 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
92 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
93 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
94 { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
95 { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
96 { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
97 { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
98 { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
99 { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
100 { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
101 { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
102 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
103 { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
104 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
105 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
106 { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
107 { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
108 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
109 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
110 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
111 { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
112 { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
113 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
114 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
115 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
116 { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM },
117 { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS },
118 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
119 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
120 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
121 { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
122 { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
123 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
124 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
125 { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD },
126 { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
127 { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
128 { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
129 { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
130 { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
131 { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
132 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
133 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE },
134 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE },
135 { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE },
136 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD },
137 { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
138 { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 },
139 { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 },
140 { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 },
141 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
142 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
143 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
144 { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
145 { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
146 { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
147 { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
148 { insn_invalid, 0, 0 }
153 static inline __cpuinit u32 build_rs(u32 arg)
156 printk(KERN_WARNING "Micro-assembler field overflow\n");
158 return (arg & RS_MASK) << RS_SH;
161 static inline __cpuinit u32 build_rt(u32 arg)
164 printk(KERN_WARNING "Micro-assembler field overflow\n");
166 return (arg & RT_MASK) << RT_SH;
169 static inline __cpuinit u32 build_rd(u32 arg)
172 printk(KERN_WARNING "Micro-assembler field overflow\n");
174 return (arg & RD_MASK) << RD_SH;
177 static inline __cpuinit u32 build_re(u32 arg)
180 printk(KERN_WARNING "Micro-assembler field overflow\n");
182 return (arg & RE_MASK) << RE_SH;
185 static inline __cpuinit u32 build_simm(s32 arg)
187 if (arg > 0x7fff || arg < -0x8000)
188 printk(KERN_WARNING "Micro-assembler field overflow\n");
193 static inline __cpuinit u32 build_uimm(u32 arg)
196 printk(KERN_WARNING "Micro-assembler field overflow\n");
198 return arg & IMM_MASK;
201 static inline __cpuinit u32 build_bimm(s32 arg)
203 if (arg > 0x1ffff || arg < -0x20000)
204 printk(KERN_WARNING "Micro-assembler field overflow\n");
207 printk(KERN_WARNING "Invalid micro-assembler branch target\n");
209 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
212 static inline __cpuinit u32 build_jimm(u32 arg)
214 if (arg & ~((JIMM_MASK) << 2))
215 printk(KERN_WARNING "Micro-assembler field overflow\n");
217 return (arg >> 2) & JIMM_MASK;
220 static inline __cpuinit u32 build_scimm(u32 arg)
222 if (arg & ~SCIMM_MASK)
223 printk(KERN_WARNING "Micro-assembler field overflow\n");
225 return (arg & SCIMM_MASK) << SCIMM_SH;
228 static inline __cpuinit u32 build_func(u32 arg)
230 if (arg & ~FUNC_MASK)
231 printk(KERN_WARNING "Micro-assembler field overflow\n");
233 return arg & FUNC_MASK;
236 static inline __cpuinit u32 build_set(u32 arg)
239 printk(KERN_WARNING "Micro-assembler field overflow\n");
241 return arg & SET_MASK;
245 * The order of opcode arguments is implicitly left to right,
246 * starting with RS and ending with FUNC or IMM.
248 static void __cpuinit build_insn(u32 **buf, enum opcode opc, ...)
250 struct insn *ip = NULL;
255 for (i = 0; insn_table[i].opcode != insn_invalid; i++)
256 if (insn_table[i].opcode == opc) {
261 if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
262 panic("Unsupported Micro-assembler instruction %d", opc);
267 op |= build_rs(va_arg(ap, u32));
269 op |= build_rt(va_arg(ap, u32));
271 op |= build_rd(va_arg(ap, u32));
273 op |= build_re(va_arg(ap, u32));
274 if (ip->fields & SIMM)
275 op |= build_simm(va_arg(ap, s32));
276 if (ip->fields & UIMM)
277 op |= build_uimm(va_arg(ap, u32));
278 if (ip->fields & BIMM)
279 op |= build_bimm(va_arg(ap, s32));
280 if (ip->fields & JIMM)
281 op |= build_jimm(va_arg(ap, u32));
282 if (ip->fields & FUNC)
283 op |= build_func(va_arg(ap, u32));
284 if (ip->fields & SET)
285 op |= build_set(va_arg(ap, u32));
286 if (ip->fields & SCIMM)
287 op |= build_scimm(va_arg(ap, u32));
294 #define I_u1u2u3(op) \
297 build_insn(buf, insn##op, a, b, c); \
300 #define I_u2u1u3(op) \
303 build_insn(buf, insn##op, b, a, c); \
306 #define I_u3u1u2(op) \
309 build_insn(buf, insn##op, b, c, a); \
312 #define I_u1u2s3(op) \
315 build_insn(buf, insn##op, a, b, c); \
318 #define I_u2s3u1(op) \
321 build_insn(buf, insn##op, c, a, b); \
324 #define I_u2u1s3(op) \
327 build_insn(buf, insn##op, b, a, c); \
330 #define I_u2u1msbu3(op) \
333 build_insn(buf, insn##op, b, a, c+d-1, c); \
339 build_insn(buf, insn##op, a, b); \
345 build_insn(buf, insn##op, a, b); \
351 build_insn(buf, insn##op, a); \
357 build_insn(buf, insn##op); \
420 void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
427 int __cpuinit uasm_in_compat_space_p(long addr)
429 /* Is this address in 32bit compat space? */
431 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
437 static int __cpuinit uasm_rel_highest(long val)
440 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
446 static int __cpuinit uasm_rel_higher(long val)
449 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
455 int __cpuinit uasm_rel_hi(long val)
457 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
460 int __cpuinit uasm_rel_lo(long val)
462 return ((val & 0xffff) ^ 0x8000) - 0x8000;
465 void __cpuinit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
467 if (!uasm_in_compat_space_p(addr)) {
468 uasm_i_lui(buf, rs, uasm_rel_highest(addr));
469 if (uasm_rel_higher(addr))
470 uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
471 if (uasm_rel_hi(addr)) {
472 uasm_i_dsll(buf, rs, rs, 16);
473 uasm_i_daddiu(buf, rs, rs, uasm_rel_hi(addr));
474 uasm_i_dsll(buf, rs, rs, 16);
476 uasm_i_dsll32(buf, rs, rs, 0);
478 uasm_i_lui(buf, rs, uasm_rel_hi(addr));
481 void __cpuinit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
483 UASM_i_LA_mostly(buf, rs, addr);
484 if (uasm_rel_lo(addr)) {
485 if (!uasm_in_compat_space_p(addr))
486 uasm_i_daddiu(buf, rs, rs, uasm_rel_lo(addr));
488 uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr));
492 /* Handle relocations. */
494 uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
497 (*rel)->type = R_MIPS_PC16;
502 static inline void __cpuinit
503 __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
505 long laddr = (long)lab->addr;
506 long raddr = (long)rel->addr;
510 *rel->addr |= build_bimm(laddr - (raddr + 4));
514 panic("Unsupported Micro-assembler relocation %d",
520 uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
522 struct uasm_label *l;
524 for (; rel->lab != UASM_LABEL_INVALID; rel++)
525 for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
526 if (rel->lab == l->lab)
527 __resolve_relocs(rel, l);
531 uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off)
533 for (; rel->lab != UASM_LABEL_INVALID; rel++)
534 if (rel->addr >= first && rel->addr < end)
539 uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off)
541 for (; lab->lab != UASM_LABEL_INVALID; lab++)
542 if (lab->addr >= first && lab->addr < end)
547 uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first,
548 u32 *end, u32 *target)
550 long off = (long)(target - first);
552 memcpy(target, first, (end - first) * sizeof(u32));
554 uasm_move_relocs(rel, first, end, off);
555 uasm_move_labels(lab, first, end, off);
558 int __cpuinit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
560 for (; rel->lab != UASM_LABEL_INVALID; rel++) {
561 if (rel->addr == addr
562 && (rel->type == R_MIPS_PC16
563 || rel->type == R_MIPS_26))
570 /* Convenience functions for labeled branches. */
572 uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
574 uasm_r_mips_pc16(r, *p, lid);
575 uasm_i_bltz(p, reg, 0);
579 uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
581 uasm_r_mips_pc16(r, *p, lid);
586 uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
588 uasm_r_mips_pc16(r, *p, lid);
589 uasm_i_beqz(p, reg, 0);
593 uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
595 uasm_r_mips_pc16(r, *p, lid);
596 uasm_i_beqzl(p, reg, 0);
600 uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
601 unsigned int reg2, int lid)
603 uasm_r_mips_pc16(r, *p, lid);
604 uasm_i_bne(p, reg1, reg2, 0);
608 uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
610 uasm_r_mips_pc16(r, *p, lid);
611 uasm_i_bnez(p, reg, 0);
615 uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
617 uasm_r_mips_pc16(r, *p, lid);
618 uasm_i_bgezl(p, reg, 0);
622 uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
624 uasm_r_mips_pc16(r, *p, lid);
625 uasm_i_bgez(p, reg, 0);
629 uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
630 unsigned int bit, int lid)
632 uasm_r_mips_pc16(r, *p, lid);
633 uasm_i_bbit0(p, reg, bit, 0);
637 uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
638 unsigned int bit, int lid)
640 uasm_r_mips_pc16(r, *p, lid);
641 uasm_i_bbit1(p, reg, bit, 0);