arch/mips/mips-boards/generic/time.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
   4  *
   5  *  This program is free software; you can distribute it and/or modify it
   6  *  under the terms of the GNU General Public License (Version 2) as
   7  *  published by the Free Software Foundation.
   8  *
   9  *  This program is distributed in the hope it will be useful, but WITHOUT
  10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  *  for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License along
  15  *  with this program; if not, write to the Free Software Foundation, Inc.,
  16  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17  *
  18  * Setting up the clock on the MIPS boards.
  19  */
  20
  21 #include <linux/types.h>
  22 #include <linux/init.h>
  23 #include <linux/kernel_stat.h>
  24 #include <linux/sched.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/time.h>
  28 #include <linux/timex.h>
  29 #include <linux/mc146818rtc.h>
  30
  31 #include <asm/mipsregs.h>
  32 #include <asm/mipsmtregs.h>
  33 #include <asm/hardirq.h>
  34 #include <asm/irq.h>
  35 #include <asm/div64.h>
  36 #include <asm/cpu.h>
  37 #include <asm/time.h>
  38 #include <asm/mc146818-time.h>
  39 #include <asm/msc01_ic.h>
  40
  41 #include <asm/mips-boards/generic.h>
  42 #include <asm/mips-boards/prom.h>
  43
  44 #ifdef CONFIG_MIPS_ATLAS
  45 #include <asm/mips-boards/atlasint.h>
  46 #endif
  47 #ifdef CONFIG_MIPS_MALTA
  48 #include <asm/mips-boards/maltaint.h>
  49 #endif
  50 #ifdef CONFIG_MIPS_SEAD
  51 #include <asm/mips-boards/seadint.h>
  52 #endif
  53
  54 unsigned long cpu_khz;
  55
  56 static int mips_cpu_timer_irq;
  57 extern int cp0_perfcount_irq;
  58
  59 static void mips_timer_dispatch(void)
  60 {
  61         do_IRQ(mips_cpu_timer_irq);
  62 }
  63
  64 static void mips_perf_dispatch(void)
  65 {
  66         do_IRQ(cp0_perfcount_irq);
  67 }
  68
  69 /*
  70  * Estimate CPU frequency.  Sets mips_hpt_frequency as a side-effect
  71  */
  72 static unsigned int __init estimate_cpu_frequency(void)
  73 {
  74         unsigned int prid = read_c0_prid() & 0xffff00;
  75         unsigned int count;
  76
  77 #if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_SIM)
  78         /*
  79          * The SEAD board doesn't have a real time clock, so we can't
  80          * really calculate the timer frequency
  81          * For now we hardwire the SEAD board frequency to 12MHz.
  82          */
  83
  84         if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
  85             (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
  86                 count = 12000000;
  87         else
  88                 count = 6000000;
  89 #endif
  90 #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
  91         unsigned long flags;
  92         unsigned int start;
  93
  94         local_irq_save(flags);
  95
  96         /* Start counter exactly on falling edge of update flag */
  97         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
  98         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
  99
 100         /* Start r4k counter. */
 101         start = read_c0_count();
 102
 103         /* Read counter exactly on falling edge of update flag */
 104         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 105         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 106
 107         count = read_c0_count() - start;
 108
 109         /* restore interrupts */
 110         local_irq_restore(flags);
 111 #endif
 112
 113         mips_hpt_frequency = count;
 114         if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
 115             (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
 116                 count *= 2;
 117
 118         count += 5000;    /* round */
 119         count -= count%10000;
 120
 121         return count;
 122 }
 123
 124 unsigned long read_persistent_clock(void)
 125 {
 126         return mc146818_get_cmos_time();
 127 }
 128
 129 void __init plat_time_init(void)
 130 {
 131         unsigned int est_freq;
 132
 133         /* Set Data mode - binary. */
 134         CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
 135
 136         est_freq = estimate_cpu_frequency ();
 137
 138         printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
 139                (est_freq%1000000)*100/1000000);
 140
 141         cpu_khz = est_freq / 1000;
 142
 143         mips_scroll_message();
 144 }
 145
 146 //static irqreturn_t mips_perf_interrupt(int irq, void *dev_id)
 147 //{
 148 //      return perf_irq();
 149 //}
 150
 151 //static struct irqaction perf_irqaction = {
 152 //      .handler = mips_perf_interrupt,
 153 //      .flags = IRQF_DISABLED | IRQF_PERCPU,
 154 //      .name = "performance",
 155 //};
 156
 157 void __init plat_perf_setup(void)
 158 {
 159 //      struct irqaction *irq = &perf_irqaction;
 160
 161         cp0_perfcount_irq = -1;
 162
 163 #ifdef MSC01E_INT_BASE
 164         if (cpu_has_veic) {
 165                 set_vi_handler (MSC01E_INT_PERFCTR, mips_perf_dispatch);
 166                 cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
 167         } else
 168 #endif
 169         if (cp0_perfcount_irq >= 0) {
 170                 if (cpu_has_vint)
 171                         set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
 172 #ifdef CONFIG_SMP
 173                 set_irq_handler(cp0_perfcount_irq, handle_percpu_irq);
 174 #endif
 175         }
 176 }
 177
 178 void __init plat_timer_setup(struct irqaction *irq)
 179 {
 180 #ifdef MSC01E_INT_BASE
 181         if (cpu_has_veic) {
 182                 set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch);
 183                 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
 184         }
 185         else
 186 #endif
 187         {
 188                 if (cpu_has_vint)
 189                         set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
 190                 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
 191         }
 192
 193 #ifdef CONFIG_MIPS_MT_SMTC
 194         setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << cp0_compare_irq);
 195 #else
 196         setup_irq(mips_cpu_timer_irq, irq);
 197 #endif /* CONFIG_MIPS_MT_SMTC */
 198 #ifdef CONFIG_SMP
 199         set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
 200 #endif
 201
 202         plat_perf_setup();
 203 }