arch/mips/kernel/irq-gic.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
   7  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
   8  */
   9 #include <linux/bitmap.h>
  10 #include <linux/init.h>
  11 #include <linux/smp.h>
  12 #include <linux/irq.h>
  13
  14 #include <asm/io.h>
  15 #include <asm/gic.h>
  16 #include <asm/setup.h>
  17 #include <asm/traps.h>
  18 #include <asm/gcmpregs.h>
  19 #include <linux/hardirq.h>
  20 #include <asm-generic/bitops/find.h>
  21
  22 unsigned int gic_present;
  23 unsigned long _gic_base;
  24 unsigned int gic_irq_base;
  25 unsigned int gic_irq_flags[GIC_NUM_INTRS];
  26
  27 /* The index into this array is the vector # of the interrupt. */
  28 struct gic_shared_intr_map gic_shared_intr_map[GIC_NUM_INTRS];
  29
  30 static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
  31 static struct gic_pending_regs pending_regs[NR_CPUS];
  32 static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
  33
  34 unsigned int gic_get_timer_pending(void)
  35 {
  36         unsigned int vpe_pending;
  37
  38         GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), 0);
  39         GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_PEND), vpe_pending);
  40         return (vpe_pending & GIC_VPE_PEND_TIMER_MSK);
  41 }
  42
  43 void gic_bind_eic_interrupt(int irq, int set)
  44 {
  45         /* Convert irq vector # to hw int # */
  46         irq -= GIC_PIN_TO_VEC_OFFSET;
  47
  48         /* Set irq to use shadow set */
  49         GICWRITE(GIC_REG_ADDR(VPE_LOCAL, GIC_VPE_EIC_SS(irq)), set);
  50 }
  51
  52 void gic_send_ipi(unsigned int intr)
  53 {
  54         GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
  55 }
  56
  57 static void gic_eic_irq_dispatch(void)
  58 {
  59         unsigned int cause = read_c0_cause();
  60         int irq;
  61
  62         irq = (cause & ST0_IM) >> STATUSB_IP2;
  63         if (irq == 0)
  64                 irq = -1;
  65
  66         if (irq >= 0)
  67                 do_IRQ(gic_irq_base + irq);
  68         else
  69                 spurious_interrupt();
  70 }
  71
  72 static void __init vpe_local_setup(unsigned int numvpes)
  73 {
  74         unsigned long timer_intr = GIC_INT_TMR;
  75         unsigned long perf_intr = GIC_INT_PERFCTR;
  76         unsigned int vpe_ctl;
  77         int i;
  78
  79         if (cpu_has_veic) {
  80                 /*
  81                  * GIC timer interrupt -> CPU HW Int X (vector X+2) ->
  82                  * map to pin X+2-1 (since GIC adds 1)
  83                  */
  84                 timer_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
  85                 /*
  86                  * GIC perfcnt interrupt -> CPU HW Int X (vector X+2) ->
  87                  * map to pin X+2-1 (since GIC adds 1)
  88                  */
  89                 perf_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
  90         }
  91
  92         /*
  93          * Setup the default performance counter timer interrupts
  94          * for all VPEs
  95          */
  96         for (i = 0; i < numvpes; i++) {
  97                 GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
  98
  99                 /* Are Interrupts locally routable? */
 100                 GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
 101                 if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
 102                         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
 103                                  GIC_MAP_TO_PIN_MSK | timer_intr);
 104                 if (cpu_has_veic) {
 105                         set_vi_handler(timer_intr + GIC_PIN_TO_VEC_OFFSET,
 106                                 gic_eic_irq_dispatch);
 107                         gic_shared_intr_map[timer_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_TIMER_MSK;
 108                 }
 109
 110                 if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
 111                         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
 112                                  GIC_MAP_TO_PIN_MSK | perf_intr);
 113                 if (cpu_has_veic) {
 114                         set_vi_handler(perf_intr + GIC_PIN_TO_VEC_OFFSET, gic_eic_irq_dispatch);
 115                         gic_shared_intr_map[perf_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_PERFCNT_MSK;
 116                 }
 117         }
 118 }
 119
 120 unsigned int gic_get_int(void)
 121 {
 122         unsigned int i;
 123         unsigned long *pending, *intrmask, *pcpu_mask;
 124         unsigned long *pending_abs, *intrmask_abs;
 125
 126         /* Get per-cpu bitmaps */
 127         pending = pending_regs[smp_processor_id()].pending;
 128         intrmask = intrmask_regs[smp_processor_id()].intrmask;
 129         pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
 130
 131         pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
 132                                                          GIC_SH_PEND_31_0_OFS);
 133         intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
 134                                                           GIC_SH_MASK_31_0_OFS);
 135
 136         for (i = 0; i < BITS_TO_LONGS(GIC_NUM_INTRS); i++) {
 137                 GICREAD(*pending_abs, pending[i]);
 138                 GICREAD(*intrmask_abs, intrmask[i]);
 139                 pending_abs++;
 140                 intrmask_abs++;
 141         }
 142
 143         bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
 144         bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);
 145
 146         return find_first_bit(pending, GIC_NUM_INTRS);
 147 }
 148
 149 static void gic_mask_irq(struct irq_data *d)
 150 {
 151         GIC_CLR_INTR_MASK(d->irq - gic_irq_base);
 152 }
 153
 154 static void gic_unmask_irq(struct irq_data *d)
 155 {
 156         GIC_SET_INTR_MASK(d->irq - gic_irq_base);
 157 }
 158
 159 #ifdef CONFIG_SMP
 160 static DEFINE_SPINLOCK(gic_lock);
 161
 162 static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
 163                             bool force)
 164 {
 165         unsigned int irq = (d->irq - gic_irq_base);
 166         cpumask_t       tmp = CPU_MASK_NONE;
 167         unsigned long   flags;
 168         int             i;
 169
 170         cpumask_and(&tmp, cpumask, cpu_online_mask);
 171         if (cpus_empty(tmp))
 172                 return -1;
 173
 174         /* Assumption : cpumask refers to a single CPU */
 175         spin_lock_irqsave(&gic_lock, flags);
 176         for (;;) {
 177                 /* Re-route this IRQ */
 178                 GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
 179
 180                 /* Update the pcpu_masks */
 181                 for (i = 0; i < NR_CPUS; i++)
 182                         clear_bit(irq, pcpu_masks[i].pcpu_mask);
 183                 set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
 184
 185         }
 186         cpumask_copy(d->affinity, cpumask);
 187         spin_unlock_irqrestore(&gic_lock, flags);
 188
 189         return IRQ_SET_MASK_OK_NOCOPY;
 190 }
 191 #endif
 192
 193 static struct irq_chip gic_irq_controller = {
 194         .name                   =       "MIPS GIC",
 195         .irq_ack                =       gic_irq_ack,
 196         .irq_mask               =       gic_mask_irq,
 197         .irq_mask_ack           =       gic_mask_irq,
 198         .irq_unmask             =       gic_unmask_irq,
 199         .irq_eoi                =       gic_finish_irq,
 200 #ifdef CONFIG_SMP
 201         .irq_set_affinity       =       gic_set_affinity,
 202 #endif
 203 };
 204
 205 static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
 206         unsigned int pin, unsigned int polarity, unsigned int trigtype,
 207         unsigned int flags)
 208 {
 209         struct gic_shared_intr_map *map_ptr;
 210
 211         /* Setup Intr to Pin mapping */
 212         if (pin & GIC_MAP_TO_NMI_MSK) {
 213                 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
 214                 /* FIXME: hack to route NMI to all cpu's */
 215                 for (cpu = 0; cpu < NR_CPUS; cpu += 32) {
 216                         GICWRITE(GIC_REG_ADDR(SHARED,
 217                                           GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)),
 218                                  0xffffffff);
 219                 }
 220         } else {
 221                 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
 222                          GIC_MAP_TO_PIN_MSK | pin);
 223                 /* Setup Intr to CPU mapping */
 224                 GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
 225                 if (cpu_has_veic) {
 226                         set_vi_handler(pin + GIC_PIN_TO_VEC_OFFSET,
 227                                 gic_eic_irq_dispatch);
 228                         map_ptr = &gic_shared_intr_map[pin + GIC_PIN_TO_VEC_OFFSET];
 229                         if (map_ptr->num_shared_intr >= GIC_MAX_SHARED_INTR)
 230                                 BUG();
 231                         map_ptr->intr_list[map_ptr->num_shared_intr++] = intr;
 232                 }
 233         }
 234
 235         /* Setup Intr Polarity */
 236         GIC_SET_POLARITY(intr, polarity);
 237
 238         /* Setup Intr Trigger Type */
 239         GIC_SET_TRIGGER(intr, trigtype);
 240
 241         /* Init Intr Masks */
 242         GIC_CLR_INTR_MASK(intr);
 243         /* Initialise per-cpu Interrupt software masks */
 244         if (flags & GIC_FLAG_IPI)
 245                 set_bit(intr, pcpu_masks[cpu].pcpu_mask);
 246         if ((flags & GIC_FLAG_TRANSPARENT) && (cpu_has_veic == 0))
 247                 GIC_SET_INTR_MASK(intr);
 248         if (trigtype == GIC_TRIG_EDGE)
 249                 gic_irq_flags[intr] |= GIC_TRIG_EDGE;
 250 }
 251
 252 static void __init gic_basic_init(int numintrs, int numvpes,
 253                         struct gic_intr_map *intrmap, int mapsize)
 254 {
 255         unsigned int i, cpu;
 256         unsigned int pin_offset = 0;
 257
 258         board_bind_eic_interrupt = &gic_bind_eic_interrupt;
 259
 260         /* Setup defaults */
 261         for (i = 0; i < numintrs; i++) {
 262                 GIC_SET_POLARITY(i, GIC_POL_POS);
 263                 GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
 264                 GIC_CLR_INTR_MASK(i);
 265                 if (i < GIC_NUM_INTRS) {
 266                         gic_irq_flags[i] = 0;
 267                         gic_shared_intr_map[i].num_shared_intr = 0;
 268                         gic_shared_intr_map[i].local_intr_mask = 0;
 269                 }
 270         }
 271
 272         /*
 273          * In EIC mode, the HW_INT# is offset by (2-1). Need to subtract
 274          * one because the GIC will add one (since 0=no intr).
 275          */
 276         if (cpu_has_veic)
 277                 pin_offset = (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
 278
 279         /* Setup specifics */
 280         for (i = 0; i < mapsize; i++) {
 281                 cpu = intrmap[i].cpunum;
 282                 if (cpu == GIC_UNUSED)
 283                         continue;
 284                 if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
 285                         continue;
 286                 gic_setup_intr(i,
 287                         intrmap[i].cpunum,
 288                         intrmap[i].pin + pin_offset,
 289                         intrmap[i].polarity,
 290                         intrmap[i].trigtype,
 291                         intrmap[i].flags);
 292         }
 293
 294         vpe_local_setup(numvpes);
 295 }
 296
 297 void __init gic_init(unsigned long gic_base_addr,
 298                      unsigned long gic_addrspace_size,
 299                      struct gic_intr_map *intr_map, unsigned int intr_map_size,
 300                      unsigned int irqbase)
 301 {
 302         unsigned int gicconfig;
 303         int numvpes, numintrs;
 304
 305         _gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
 306                                                     gic_addrspace_size);
 307         gic_irq_base = irqbase;
 308
 309         GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
 310         numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
 311                    GIC_SH_CONFIG_NUMINTRS_SHF;
 312         numintrs = ((numintrs + 1) * 8);
 313
 314         numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
 315                   GIC_SH_CONFIG_NUMVPES_SHF;
 316         numvpes = numvpes + 1;
 317
 318         gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);
 319
 320         gic_platform_init(numintrs, &gic_irq_controller);
 321 }