2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
7 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
14 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
16 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
22 * Copyright 2001 MontaVista Software Inc.
23 * Author: MontaVista Software, Inc.
24 * ahennessy@mvista.com
26 * Copyright (C) 2000-2001 Toshiba Corporation
27 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
30 #include <linux/clockchips.h>
31 #include <linux/init.h>
32 #include <linux/kernel.h>
33 #include <linux/kdev_t.h>
34 #include <linux/types.h>
35 #include <linux/sched.h>
36 #include <linux/pci.h>
37 #include <linux/ide.h>
38 #include <linux/irq.h>
39 #include <linux/ioport.h>
40 #include <linux/param.h> /* for HZ */
41 #include <linux/delay.h>
43 #include <linux/platform_device.h>
44 #ifdef CONFIG_SERIAL_TXX9
45 #include <linux/tty.h>
46 #include <linux/serial.h>
47 #include <linux/serial_core.h>
50 #include <asm/addrspace.h>
52 #include <asm/reboot.h>
53 #include <asm/jmr3927/jmr3927.h>
54 #include <asm/mipsregs.h>
56 extern void puts(const char *cp);
58 /* Tick Timer divider */
59 #define JMR3927_TIMER_CCD 0 /* 1/2 */
60 #define JMR3927_TIMER_CLK (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
62 /* don't enable - see errata */
63 static int jmr3927_ccfg_toeon;
65 static inline void do_reset(void)
67 #if 1 /* Resetting PCI bus */
68 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
69 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
70 (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */
72 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
74 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
77 static void jmr3927_machine_restart(char *command)
84 static void jmr3927_machine_halt(void)
86 puts("JMR-TX3927 halted.\n");
90 static void jmr3927_machine_power_off(void)
92 puts("JMR-TX3927 halted. Please turn off the power.\n");
96 static cycle_t jmr3927_hpt_read(void)
98 /* We assume this function is called xtime_lock held. */
99 return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr;
102 static void jmr3927_set_mode(enum clock_event_mode mode,
103 struct clock_event_device *evt)
105 /* Nothing to do here */
108 struct clock_event_device jmr3927_clock_event_device = {
110 .features = CLOCK_EVT_FEAT_PERIODIC,
113 .cpumask = CPU_MASK_CPU0,
114 .irq = JMR3927_IRQ_TICK,
115 .set_mode = jmr3927_set_mode,
118 static irqreturn_t jmr3927_timer_interrupt(int irq, void *dev_id)
120 struct clock_event_device *cd = &jmr3927_clock_event_device;
122 jmr3927_tmrptr->tisr = 0; /* ack interrupt */
124 cd->event_handler(cd);
129 static struct irqaction jmr3927_timer_irqaction = {
130 .handler = jmr3927_timer_interrupt,
131 .flags = IRQF_DISABLED | IRQF_PERCPU,
132 .name = "jmr3927-timer",
135 void __init plat_time_init(void)
137 struct clock_event_device *cd;
139 clocksource_mips.read = jmr3927_hpt_read;
140 mips_hpt_frequency = JMR3927_TIMER_CLK;
142 jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
143 jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
144 jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
145 jmr3927_tmrptr->tcr =
146 TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
148 cd = &jmr3927_clock_event_device;
149 /* Calculate the min / max delta */
150 cd->mult = div_sc((unsigned long) JMR3927_IMCLK, NSEC_PER_SEC, 32);
151 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
152 cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
153 clockevents_register_device(cd);
155 setup_irq(JMR3927_IRQ_TICK, &jmr3927_timer_irqaction);
158 #define DO_WRITE_THROUGH
159 #define DO_ENABLE_CACHE
161 extern char * __init prom_getcmdline(void);
162 static void jmr3927_board_init(void);
163 extern struct resource pci_io_resource;
164 extern struct resource pci_mem_resource;
166 void __init plat_mem_setup(void)
170 set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
172 _machine_restart = jmr3927_machine_restart;
173 _machine_halt = jmr3927_machine_halt;
174 pm_power_off = jmr3927_machine_power_off;
179 ioport_resource.start = pci_io_resource.start;
180 ioport_resource.end = pci_io_resource.end;
181 iomem_resource.start = 0;
182 iomem_resource.end = 0xffffffff;
184 /* Reboot on panic */
190 #ifdef DO_ENABLE_CACHE
191 int mips_ic_disable = 0, mips_dc_disable = 0;
193 int mips_ic_disable = 1, mips_dc_disable = 1;
195 #ifdef DO_WRITE_THROUGH
196 int mips_config_cwfon = 0;
197 int mips_config_wbon = 0;
199 int mips_config_cwfon = 1;
200 int mips_config_wbon = 1;
203 conf = read_c0_conf();
204 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
205 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
206 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
207 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
208 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
214 /* initialize board */
215 jmr3927_board_init();
217 argptr = prom_getcmdline();
219 if ((argptr = strstr(argptr, "toeon")) != NULL)
220 jmr3927_ccfg_toeon = 1;
221 argptr = prom_getcmdline();
222 if ((argptr = strstr(argptr, "ip=")) == NULL) {
223 argptr = prom_getcmdline();
224 strcat(argptr, " ip=bootp");
227 #ifdef CONFIG_SERIAL_TXX9
229 extern int early_serial_txx9_setup(struct uart_port *port);
231 struct uart_port req;
232 for(i = 0; i < 2; i++) {
233 memset(&req, 0, sizeof(req));
235 req.iotype = UPIO_MEM;
236 req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i);
237 req.mapbase = TX3927_SIO_REG(i);
239 JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
241 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
242 req.uartclk = JMR3927_IMCLK;
243 early_serial_txx9_setup(&req);
246 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
247 argptr = prom_getcmdline();
248 if ((argptr = strstr(argptr, "console=")) == NULL) {
249 argptr = prom_getcmdline();
250 strcat(argptr, " console=ttyS1,115200");
256 static void tx3927_setup(void);
258 static void __init jmr3927_board_init(void)
263 jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
267 printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
268 jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
269 jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
270 jmr3927_dipsw1(), jmr3927_dipsw2(),
271 jmr3927_dipsw3(), jmr3927_dipsw4());
274 static void __init tx3927_setup(void)
278 unsigned long mips_pci_io_base = JMR3927_PCIIO;
279 unsigned long mips_pci_io_size = JMR3927_PCIIO_SIZE;
280 unsigned long mips_pci_mem_base = JMR3927_PCIMEM;
281 unsigned long mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
282 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
283 unsigned long mips_pci_io_pciaddr = 0;
286 /* SDRAMC are configured by PROM */
289 tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
290 tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
291 tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
292 tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
295 /* enable Timeout BusError */
296 if (jmr3927_ccfg_toeon)
297 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
299 /* clear BusErrorOnWrite flag */
300 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
301 /* Disable PCI snoop */
302 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
304 #ifdef DO_WRITE_THROUGH
305 /* Enable PCI SNOOP - with write through only */
306 tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
310 tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
311 tx3927_ccfgptr->pcfg |=
312 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
313 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
315 printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
316 tx3927_ccfgptr->crir,
317 tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
320 /* disable all timers */
321 for (i = 0; i < TX3927_NR_TMR; i++) {
322 tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
323 tx3927_tmrptr(i)->tisr = 0;
324 tx3927_tmrptr(i)->cpra = 0xffffffff;
325 tx3927_tmrptr(i)->itmr = 0;
326 tx3927_tmrptr(i)->ccdr = 0;
327 tx3927_tmrptr(i)->pgmr = 0;
331 tx3927_dmaptr->mcr = 0;
332 for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) {
334 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
335 tx3927_dmaptr->ch[i].ccr = 0;
339 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
341 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
346 printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
347 tx3927_pcicptr->did, tx3927_pcicptr->vid,
348 tx3927_pcicptr->rid);
349 if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
350 printk("External\n");
353 printk("Internal\n");
356 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
358 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
359 JMR3927_IOC_RESET_ADDR);
361 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
364 /* Disable External PCI Config. Access */
365 tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
367 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
368 TX3927_PCIC_LBC_TIBSE |
369 TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
371 /* LB->PCI mappings */
372 tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1);
373 tx3927_pcicptr->ilbioma = mips_pci_io_base;
374 tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr;
375 tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1);
376 tx3927_pcicptr->ilbmma = mips_pci_mem_base;
377 tx3927_pcicptr->ipbmma = mips_pci_mem_base;
378 /* PCI->LB mappings */
379 tx3927_pcicptr->iobas = 0xffffffff;
380 tx3927_pcicptr->ioba = 0;
381 tx3927_pcicptr->tlbioma = 0;
382 tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
383 tx3927_pcicptr->mba = 0;
384 tx3927_pcicptr->tlbmma = 0;
385 /* Enable Direct mapping Address Space Decoder */
386 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
388 /* Clear All Local Bus Status */
389 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
390 /* Enable All Local Bus Interrupts */
391 tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
392 /* Clear All PCI Status Error */
393 tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
394 /* Enable All PCI Status Error Interrupts */
395 tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
397 /* PCIC Int => IRC IRQ10 */
398 tx3927_pcicptr->il = TX3927_IR_PCI;
399 /* Target Control (per errata) */
400 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
402 /* Enable Bus Arbiter */
403 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
405 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
408 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
410 #endif /* CONFIG_PCI */
413 /* PIO[15:12] connected to LEDs */
414 tx3927_pioptr->dir = 0x0000f000;
415 tx3927_pioptr->maskcpu = 0;
416 tx3927_pioptr->maskext = 0;
420 conf = read_c0_conf();
421 if (!(conf & TX39_CONF_ICE))
422 printk("TX3927 I-Cache disabled.\n");
423 if (!(conf & TX39_CONF_DCE))
424 printk("TX3927 D-Cache disabled.\n");
425 else if (!(conf & TX39_CONF_WBON))
426 printk("TX3927 D-Cache WriteThrough.\n");
427 else if (!(conf & TX39_CONF_CWFON))
428 printk("TX3927 D-Cache WriteBack.\n");
430 printk("TX3927 D-Cache WriteBack (CWF) .\n");
434 /* This trick makes rtc-ds1742 driver usable as is. */
435 unsigned long __swizzle_addr_b(unsigned long port)
437 if ((port & 0xffff0000) != JMR3927_IOC_NVRAMB_ADDR)
439 port = (port & 0xffff0000) | (port & 0x7fff << 1);
446 EXPORT_SYMBOL(__swizzle_addr_b);
448 static int __init jmr3927_rtc_init(void)
450 static struct resource __initdata res = {
451 .start = JMR3927_IOC_NVRAMB_ADDR - IO_BASE,
452 .end = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1,
453 .flags = IORESOURCE_MEM,
455 struct platform_device *dev;
456 dev = platform_device_register_simple("rtc-ds1742", -1, &res, 1);
457 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
459 device_initcall(jmr3927_rtc_init);