2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2004-2008 Cavium Networks
8 #ifndef __ASM_OCTEON_OCTEON_H
9 #define __ASM_OCTEON_OCTEON_H
13 extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size,
18 extern void *octeon_bootmem_alloc(uint64_t size, uint64_t alignment,
20 extern void *octeon_bootmem_alloc_range(uint64_t size, uint64_t alignment,
21 uint64_t min_addr, uint64_t max_addr,
23 extern void *octeon_bootmem_alloc_named(uint64_t size, uint64_t alignment,
25 extern void *octeon_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
26 uint64_t max_addr, uint64_t align,
28 extern void *octeon_bootmem_alloc_named_address(uint64_t size, uint64_t address,
30 extern int octeon_bootmem_free_named(char *name);
31 extern void octeon_bootmem_lock(void);
32 extern void octeon_bootmem_unlock(void);
34 extern int octeon_is_simulation(void);
35 extern int octeon_is_pci_host(void);
36 extern int octeon_usb_is_ref_clk(void);
37 extern uint64_t octeon_get_clock_rate(void);
38 extern const char *octeon_board_type_string(void);
39 extern const char *octeon_get_pci_interrupts(void);
40 extern int octeon_get_southbridge_interrupt(void);
41 extern int octeon_get_boot_coremask(void);
42 extern int octeon_get_boot_num_arguments(void);
43 extern const char *octeon_get_boot_argument(int arg);
44 extern void octeon_hal_setup_reserved32(void);
45 extern void octeon_user_io_init(void);
46 struct octeon_cop2_state;
47 extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
48 extern void octeon_crypto_disable(struct octeon_cop2_state *state,
50 extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
52 extern void octeon_init_cvmcount(void);
54 #define OCTEON_ARGV_MAX_ARGS 64
55 #define OCTOEN_SERIAL_LEN 20
57 struct octeon_boot_descriptor {
58 /* Start of block referenced by assembly code - do not change! */
59 uint32_t desc_version;
64 /* Only used by bootloader */
67 /* End of This block referenced by assembly code - do not change! */
68 uint32_t exception_base_addr;
71 /* Argc count for application. */
73 uint32_t argv[OCTEON_ARGV_MAX_ARGS];
75 #define BOOT_FLAG_INIT_CORE (1 << 0)
76 #define OCTEON_BL_FLAG_DEBUG (1 << 1)
77 #define OCTEON_BL_FLAG_NO_MAGIC (1 << 2)
78 /* If set, use uart1 for console */
79 #define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3)
80 /* If set, use PCI console */
81 #define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4)
82 /* Call exit on break on serial port */
83 #define OCTEON_BL_FLAG_BREAK (1 << 5)
87 /* DRAM size in megabyes. */
89 /* physical address of free memory descriptor block. */
90 uint32_t phy_mem_desc_addr;
91 /* used to pass flags from app to debugger. */
92 uint32_t debugger_flags_base_addr;
93 /* CPU clock speed, in hz. */
95 /* DRAM clock speed, in hz. */
97 /* SPI4 clock in hz. */
98 uint32_t spi_clock_hz;
100 uint8_t board_rev_major;
101 uint8_t board_rev_minor;
103 uint8_t chip_rev_major;
104 uint8_t chip_rev_minor;
105 char board_serial_number[OCTOEN_SERIAL_LEN];
106 uint8_t mac_addr_base[6];
107 uint8_t mac_addr_count;
108 uint64_t cvmx_desc_vaddr;
111 union octeon_cvmemctl {
114 /* RO 1 = BIST fail, 0 = BIST pass */
116 /* RO 1 = BIST fail, 0 = BIST pass */
118 /* RO 1 = BIST fail, 0 = BIST pass */
120 /* RO 1 = BIST fail, 0 = BIST pass */
122 /* RO 1 = BIST fail, 0 = BIST pass */
124 /* RO 1 = BIST fail, 0 = BIST pass */
127 uint64_t reserved:22;
128 /* R/W If set, marked write-buffer entries time out
129 * the same as as other entries; if clear, marked
130 * write-buffer entries use the maximum timeout. */
131 uint64_t dismarkwblongto:1;
132 /* R/W If set, a merged store does not clear the
133 * write-buffer entry timeout state. */
134 uint64_t dismrgclrwbto:1;
135 /* R/W Two bits that are the MSBs of the resultant
136 * CVMSEG LM word location for an IOBDMA. The other 8
137 * bits come from the SCRADDR field of the IOBDMA. */
138 uint64_t iobdmascrmsb:2;
139 /* R/W If set, SYNCWS and SYNCS only order marked
140 * stores; if clear, SYNCWS and SYNCS only order
141 * unmarked stores. SYNCWSMARKED has no effect when
142 * DISSYNCWS is set. */
143 uint64_t syncwsmarked:1;
144 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as
146 uint64_t dissyncws:1;
147 /* R/W If set, no stall happens on write buffer
150 /* R/W If set (and SX set), supervisor-level
151 * loads/stores can use XKPHYS addresses with
153 uint64_t xkmemenas:1;
154 /* R/W If set (and UX set), user-level loads/stores
155 * can use XKPHYS addresses with VA<48>==0 */
156 uint64_t xkmemenau:1;
157 /* R/W If set (and SX set), supervisor-level
158 * loads/stores can use XKPHYS addresses with
161 /* R/W If set (and UX set), user-level loads/stores
162 * can use XKPHYS addresses with VA<48>==1 */
164 /* R/W If set, all stores act as SYNCW (NOMERGE must
165 * be set when this is set) RW, reset to 0. */
167 /* R/W If set, no stores merge, and all stores reach
168 * the coherent bus in order. */
170 /* R/W Selects the bit in the counter used for DID
171 * time-outs 0 = 231, 1 = 230, 2 = 229, 3 =
172 * 214. Actual time-out is between 1x and 2x this
173 * interval. For example, with DIDTTO=3, expiration
174 * interval is between 16K and 32K. */
176 /* R/W If set, the (mem) CSR clock never turns off. */
177 uint64_t csrckalwys:1;
178 /* R/W If set, mclk never turns off. */
179 uint64_t mclkalwys:1;
180 /* R/W Selects the bit in the counter used for write
181 * buffer flush time-outs (WBFLT+11) is the bit
182 * position in an internal counter used to determine
183 * expiration. The write buffer expires between 1x and
184 * 2x this interval. For example, with WBFLT = 0, a
185 * write buffer expires between 2K and 4K cycles after
186 * the write buffer entry is allocated. */
188 /* R/W If set, do not put Istream in the L2 cache. */
190 /* R/W The write buffer threshold. */
193 uint64_t reserved2:2;
194 /* R/W If set, CVMSEG is available for loads/stores in
195 * kernel/debug mode. */
196 uint64_t cvmsegenak:1;
197 /* R/W If set, CVMSEG is available for loads/stores in
198 * supervisor mode. */
199 uint64_t cvmsegenas:1;
200 /* R/W If set, CVMSEG is available for loads/stores in
202 uint64_t cvmsegenau:1;
203 /* R/W Size of local memory in cache blocks, 54 (6912
204 * bytes) is max legal value. */
209 struct octeon_cf_data {
210 unsigned long base_region_bias;
211 unsigned int base_region; /* The chip select region used by CF */
212 int is16bit; /* 0 - 8bit, !0 - 16bit */
213 int dma_engine; /* -1 for no DMA */
216 extern void octeon_write_lcd(const char *s);
217 extern void octeon_check_cpu_bist(void);
218 extern int octeon_get_boot_debug_flag(void);
219 extern int octeon_get_boot_uart(void);
222 extern unsigned int octeon_serial_in(struct uart_port *, int);
223 extern void octeon_serial_out(struct uart_port *, int, int);
226 * Write a 32bit value to the Octeon NPI register space
228 * @address: Address to write to
229 * @val: Value to write
231 static inline void octeon_npi_write32(uint64_t address, uint32_t val)
233 cvmx_write64_uint32(address ^ 4, val);
234 cvmx_read64_uint32(address ^ 4);
239 * Read a 32bit value from the Octeon NPI register space
241 * @address: Address to read
244 static inline uint32_t octeon_npi_read32(uint64_t address)
246 return cvmx_read64_uint32(address ^ 4);
249 extern struct cvmx_bootinfo *octeon_bootinfo;
251 #endif /* __ASM_OCTEON_OCTEON_H */