2 * AMD Alchemy Pb1200 Referrence Board
3 * Board Registers defines.
5 * ########################################################################
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 * ########################################################################
24 #ifndef __ASM_PB1200_H
25 #define __ASM_PB1200_H
27 #include <linux/types.h>
28 #include <asm/mach-au1x00/au1xxx_psc.h>
30 #define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
31 #define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
32 #define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
33 #define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
36 * SPI and SMB are muxed on the Pb1200 board.
37 * Refer to board documentation.
39 #define SPI_PSC_BASE PSC0_BASE_ADDR
40 #define SMBUS_PSC_BASE PSC0_BASE_ADDR
42 * AC97 and I2S are muxed on the Pb1200 board.
43 * Refer to board documentation.
45 #define AC97_PSC_BASE PSC1_BASE_ADDR
46 #define I2S_PSC_BASE PSC1_BASE_ADDR
49 #define BCSR_SYSTEM_VDDI 0x001F
50 #define BCSR_SYSTEM_POWEROFF 0x4000
51 #define BCSR_SYSTEM_RESET 0x8000
53 /* Bit positions for the different interrupt sources */
54 #define BCSR_INT_IDE 0x0001
55 #define BCSR_INT_ETH 0x0002
56 #define BCSR_INT_PC0 0x0004
57 #define BCSR_INT_PC0STSCHG 0x0008
58 #define BCSR_INT_PC1 0x0010
59 #define BCSR_INT_PC1STSCHG 0x0020
60 #define BCSR_INT_DC 0x0040
61 #define BCSR_INT_FLASHBUSY 0x0080
62 #define BCSR_INT_PC0INSERT 0x0100
63 #define BCSR_INT_PC0EJECT 0x0200
64 #define BCSR_INT_PC1INSERT 0x0400
65 #define BCSR_INT_PC1EJECT 0x0800
66 #define BCSR_INT_SD0INSERT 0x1000
67 #define BCSR_INT_SD0EJECT 0x2000
68 #define BCSR_INT_SD1INSERT 0x4000
69 #define BCSR_INT_SD1EJECT 0x8000
71 #define SMC91C111_PHYS_ADDR 0x0D000300
72 #define SMC91C111_INT PB1200_ETH_INT
74 #define IDE_PHYS_ADDR 0x0C800000
75 #define IDE_REG_SHIFT 5
76 #define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
77 #define IDE_INT PB1200_IDE_INT
78 #define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
79 #define IDE_RQSIZE 128
81 #define NAND_PHYS_ADDR 0x1C000000
84 * Timing values as described in databook, * ns value stripped of
86 * These defines are here rather than an Au1200 generic file because
87 * the parts chosen on another board may be different and may require
90 #define NAND_T_H (18 >> 2)
91 #define NAND_T_PUL (30 >> 2)
92 #define NAND_T_SU (30 >> 2)
93 #define NAND_T_WH (30 >> 2)
95 /* Bitfield shift amounts */
96 #define NAND_T_H_SHIFT 0
97 #define NAND_T_PUL_SHIFT 4
98 #define NAND_T_SU_SHIFT 8
99 #define NAND_T_WH_SHIFT 12
101 #define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
102 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
103 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
104 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
107 * External Interrupts for Pb1200 as of 8/6/2004.
108 * Bit positions in the CPLD registers can be calculated by taking
109 * the interrupt define and subtracting the PB1200_INT_BEGIN value.
111 * Example: IDE bis pos is = 64 - 64
112 * ETH bit pos is = 65 - 64
114 enum external_pb1200_ints {
115 PB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
117 PB1200_IDE_INT = PB1200_INT_BEGIN,
120 PB1200_PC0_STSCHG_INT,
122 PB1200_PC1_STSCHG_INT,
124 PB1200_FLASHBUSY_INT,
125 PB1200_PC0_INSERT_INT,
126 PB1200_PC0_EJECT_INT,
127 PB1200_PC1_INSERT_INT,
128 PB1200_PC1_EJECT_INT,
129 PB1200_SD0_INSERT_INT,
130 PB1200_SD0_EJECT_INT,
131 PB1200_SD1_INSERT_INT,
132 PB1200_SD1_EJECT_INT,
134 PB1200_INT_END = PB1200_INT_BEGIN + 15
138 * Pb1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
140 #define PCMCIA_MAX_SOCK 1
141 #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
144 #define SET_VCC_VPP(VCC, VPP, SLOT) \
145 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
147 #define BOARD_PC0_INT PB1200_PC0_INT
148 #define BOARD_PC1_INT PB1200_PC1_INT
149 #define BOARD_CARD_INSERTED(SOCKET) (bcsr_read(BCSR_SIGSTAT & (1 << (8 + (2 * SOCKET))))
151 /* NAND chip select */
154 #endif /* __ASM_PB1200_H */