2 * AMD Alchemy DBAu1200 Reference Board
3 * Board register defines.
5 * ########################################################################
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 * ########################################################################
24 #ifndef __ASM_DB1200_H
25 #define __ASM_DB1200_H
27 #include <linux/types.h>
28 #include <asm/mach-au1x00/au1xxx_psc.h>
30 #define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
31 #define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
32 #define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
33 #define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
36 * SPI and SMB are muxed on the DBAu1200 board.
37 * Refer to board documentation.
39 #define SPI_PSC_BASE PSC0_BASE_ADDR
40 #define SMBUS_PSC_BASE PSC0_BASE_ADDR
42 * AC'97 and I2S are muxed on the DBAu1200 board.
43 * Refer to board documentation.
45 #define AC97_PSC_BASE PSC1_BASE_ADDR
46 #define I2S_PSC_BASE PSC1_BASE_ADDR
48 /* Bit positions for the different interrupt sources */
49 #define BCSR_INT_IDE 0x0001
50 #define BCSR_INT_ETH 0x0002
51 #define BCSR_INT_PC0 0x0004
52 #define BCSR_INT_PC0STSCHG 0x0008
53 #define BCSR_INT_PC1 0x0010
54 #define BCSR_INT_PC1STSCHG 0x0020
55 #define BCSR_INT_DC 0x0040
56 #define BCSR_INT_FLASHBUSY 0x0080
57 #define BCSR_INT_PC0INSERT 0x0100
58 #define BCSR_INT_PC0EJECT 0x0200
59 #define BCSR_INT_PC1INSERT 0x0400
60 #define BCSR_INT_PC1EJECT 0x0800
61 #define BCSR_INT_SD0INSERT 0x1000
62 #define BCSR_INT_SD0EJECT 0x2000
64 #define SMC91C111_PHYS_ADDR 0x19000300
65 #define SMC91C111_INT DB1200_ETH_INT
67 #define IDE_PHYS_ADDR 0x18800000
68 #define IDE_REG_SHIFT 5
69 #define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
70 #define IDE_INT DB1200_IDE_INT
71 #define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
72 #define IDE_RQSIZE 128
74 #define NAND_PHYS_ADDR 0x20000000
77 * External Interrupts for DBAu1200 as of 8/6/2004.
78 * Bit positions in the CPLD registers can be calculated by taking
79 * the interrupt define and subtracting the DB1200_INT_BEGIN value.
81 * Example: IDE bis pos is = 64 - 64
82 * ETH bit pos is = 65 - 64
84 enum external_pb1200_ints {
85 DB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
87 DB1200_IDE_INT = DB1200_INT_BEGIN,
90 DB1200_PC0_STSCHG_INT,
92 DB1200_PC1_STSCHG_INT,
95 DB1200_PC0_INSERT_INT,
97 DB1200_PC1_INSERT_INT,
99 DB1200_SD0_INSERT_INT,
100 DB1200_SD0_EJECT_INT,
102 DB1200_INT_END = DB1200_INT_BEGIN + 15,
107 * DBAu1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
109 #define PCMCIA_MAX_SOCK 1
110 #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
113 #define SET_VCC_VPP(VCC, VPP, SLOT) \
114 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
116 #define BOARD_PC0_INT DB1200_PC0_INT
117 #define BOARD_PC1_INT DB1200_PC1_INT
118 #define BOARD_CARD_INSERTED(SOCKET) (bcsr_read(BCSR_SIGSTAT) & (1 << (8 + (2 * SOCKET))))
120 /* NAND chip select */
123 #endif /* __ASM_DB1200_H */