2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2004-2007 Cavium Networks
7 * Copyright (C) 2008 Wind River Systems
9 #include <linux/init.h>
10 #include <linux/console.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
14 #include <linux/serial.h>
15 #include <linux/smp.h>
16 #include <linux/types.h>
17 #include <linux/string.h> /* for memset */
18 #include <linux/tty.h>
19 #include <linux/time.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial_8250.h>
24 #include <asm/processor.h>
25 #include <asm/reboot.h>
26 #include <asm/smp-ops.h>
27 #include <asm/system.h>
28 #include <asm/irq_cpu.h>
29 #include <asm/mipsregs.h>
30 #include <asm/bootinfo.h>
31 #include <asm/sections.h>
34 #include <asm/octeon/octeon.h>
35 #include <asm/octeon/pci-octeon.h>
36 #include <asm/octeon/cvmx-mio-defs.h>
38 #ifdef CONFIG_CAVIUM_DECODE_RSL
39 extern void cvmx_interrupt_rsl_decode(void);
40 extern int __cvmx_interrupt_ecc_report_single_bit_errors;
41 extern void cvmx_interrupt_rsl_enable(void);
44 extern struct plat_smp_ops octeon_smp_ops;
47 extern void pci_console_init(const char *arg);
50 static unsigned long long MAX_MEMORY = 512ull << 20;
52 struct octeon_boot_descriptor *octeon_boot_desc_ptr;
54 struct cvmx_bootinfo *octeon_bootinfo;
55 EXPORT_SYMBOL(octeon_bootinfo);
57 #ifdef CONFIG_CAVIUM_RESERVE32
58 uint64_t octeon_reserve32_memory;
59 EXPORT_SYMBOL(octeon_reserve32_memory);
62 static int octeon_uart;
64 extern asmlinkage void handle_int(void);
65 extern asmlinkage void plat_irq_dispatch(void);
68 * Return non zero if we are currently running in the Octeon simulator
72 int octeon_is_simulation(void)
74 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM;
76 EXPORT_SYMBOL(octeon_is_simulation);
79 * Return true if Octeon is in PCI Host mode. This means
80 * Linux can control the PCI bus.
82 * Returns Non zero if Octeon in host mode.
84 int octeon_is_pci_host(void)
87 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST;
94 * Get the clock rate of Octeon
96 * Returns Clock rate in HZ
98 uint64_t octeon_get_clock_rate(void)
100 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
102 return sysinfo->cpu_clock_hz;
104 EXPORT_SYMBOL(octeon_get_clock_rate);
106 static u64 octeon_io_clock_rate;
108 u64 octeon_get_io_clock_rate(void)
110 return octeon_io_clock_rate;
112 EXPORT_SYMBOL(octeon_get_io_clock_rate);
116 * Write to the LCD display connected to the bootbus. This display
117 * exists on most Cavium evaluation boards. If it doesn't exist, then
118 * this function doesn't do anything.
120 * @s: String to write
122 void octeon_write_lcd(const char *s)
124 if (octeon_bootinfo->led_display_base_addr) {
125 void __iomem *lcd_address =
126 ioremap_nocache(octeon_bootinfo->led_display_base_addr,
129 for (i = 0; i < 8; i++, s++) {
131 iowrite8(*s, lcd_address + i);
133 iowrite8(' ', lcd_address + i);
135 iounmap(lcd_address);
140 * Return the console uart passed by the bootloader
142 * Returns uart (0 or 1)
144 int octeon_get_boot_uart(void)
147 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
150 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ?
157 * Get the coremask Linux was booted on.
161 int octeon_get_boot_coremask(void)
163 return octeon_boot_desc_ptr->core_mask;
167 * Check the hardware BIST results for a CPU
169 void octeon_check_cpu_bist(void)
171 const int coreid = cvmx_get_core_num();
172 unsigned long long mask;
173 unsigned long long bist_val;
175 /* Check BIST results for COP0 registers */
176 mask = 0x1f00000000ull;
177 bist_val = read_octeon_c0_icacheerr();
179 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n",
182 bist_val = read_octeon_c0_dcacheerr();
184 pr_err("Core%d L1 Dcache parity error: "
185 "CacheErr(dcache) = 0x%llx\n",
188 mask = 0xfc00000000000000ull;
189 bist_val = read_c0_cvmmemctl();
191 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n",
194 write_octeon_c0_dcacheerr(0);
200 * @command: Command to pass to the bootloader. Currently ignored.
202 static void octeon_restart(char *command)
204 /* Disable all watchdogs before soft reset. They don't get cleared */
207 for_each_online_cpu(cpu)
208 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
210 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
215 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
220 * Permanently stop a core.
224 static void octeon_kill_core(void *arg)
227 if (octeon_is_simulation()) {
228 /* The simulator needs the watchdog to stop for dead cores */
229 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
230 /* A break instruction causes the simulator stop a core */
231 asm volatile ("sync\nbreak");
239 static void octeon_halt(void)
241 smp_call_function(octeon_kill_core, NULL, 0);
243 switch (octeon_bootinfo->board_type) {
244 case CVMX_BOARD_TYPE_NAO38:
245 /* Driving a 1 to GPIO 12 shuts off this board */
246 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1);
247 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000);
250 octeon_write_lcd("PowerOff");
254 octeon_kill_core(NULL);
258 * Handle all the error condition interrupts that might occur.
261 #ifdef CONFIG_CAVIUM_DECODE_RSL
262 static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id)
264 cvmx_interrupt_rsl_decode();
270 * Return a string representing the system type
274 const char *octeon_board_type_string(void)
276 static char name[80];
277 sprintf(name, "%s (%s)",
278 cvmx_board_type_to_string(octeon_bootinfo->board_type),
279 octeon_model_get_string(read_c0_prid()));
283 const char *get_system_type(void)
284 __attribute__ ((alias("octeon_board_type_string")));
286 void octeon_user_io_init(void)
288 union octeon_cvmemctl cvmmemctl;
289 union cvmx_iob_fau_timeout fau_timeout;
290 union cvmx_pow_nw_tim nm_tim;
293 /* Get the current settings for CP0_CVMMEMCTL_REG */
294 cvmmemctl.u64 = read_c0_cvmmemctl();
295 /* R/W If set, marked write-buffer entries time out the same
296 * as as other entries; if clear, marked write-buffer entries
297 * use the maximum timeout. */
298 cvmmemctl.s.dismarkwblongto = 1;
299 /* R/W If set, a merged store does not clear the write-buffer
300 * entry timeout state. */
301 cvmmemctl.s.dismrgclrwbto = 0;
302 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM
303 * word location for an IOBDMA. The other 8 bits come from the
304 * SCRADDR field of the IOBDMA. */
305 cvmmemctl.s.iobdmascrmsb = 0;
306 /* R/W If set, SYNCWS and SYNCS only order marked stores; if
307 * clear, SYNCWS and SYNCS only order unmarked
308 * stores. SYNCWSMARKED has no effect when DISSYNCWS is
310 cvmmemctl.s.syncwsmarked = 0;
311 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */
312 cvmmemctl.s.dissyncws = 0;
313 /* R/W If set, no stall happens on write buffer full. */
314 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
315 cvmmemctl.s.diswbfst = 1;
317 cvmmemctl.s.diswbfst = 0;
318 /* R/W If set (and SX set), supervisor-level loads/stores can
319 * use XKPHYS addresses with <48>==0 */
320 cvmmemctl.s.xkmemenas = 0;
322 /* R/W If set (and UX set), user-level loads/stores can use
323 * XKPHYS addresses with VA<48>==0 */
324 cvmmemctl.s.xkmemenau = 0;
326 /* R/W If set (and SX set), supervisor-level loads/stores can
327 * use XKPHYS addresses with VA<48>==1 */
328 cvmmemctl.s.xkioenas = 0;
330 /* R/W If set (and UX set), user-level loads/stores can use
331 * XKPHYS addresses with VA<48>==1 */
332 cvmmemctl.s.xkioenau = 0;
334 /* R/W If set, all stores act as SYNCW (NOMERGE must be set
335 * when this is set) RW, reset to 0. */
336 cvmmemctl.s.allsyncw = 0;
338 /* R/W If set, no stores merge, and all stores reach the
339 * coherent bus in order. */
340 cvmmemctl.s.nomerge = 0;
341 /* R/W Selects the bit in the counter used for DID time-outs 0
342 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is
343 * between 1x and 2x this interval. For example, with
344 * DIDTTO=3, expiration interval is between 16K and 32K. */
345 cvmmemctl.s.didtto = 0;
346 /* R/W If set, the (mem) CSR clock never turns off. */
347 cvmmemctl.s.csrckalwys = 0;
348 /* R/W If set, mclk never turns off. */
349 cvmmemctl.s.mclkalwys = 0;
350 /* R/W Selects the bit in the counter used for write buffer
351 * flush time-outs (WBFLT+11) is the bit position in an
352 * internal counter used to determine expiration. The write
353 * buffer expires between 1x and 2x this interval. For
354 * example, with WBFLT = 0, a write buffer expires between 2K
355 * and 4K cycles after the write buffer entry is allocated. */
356 cvmmemctl.s.wbfltime = 0;
357 /* R/W If set, do not put Istream in the L2 cache. */
358 cvmmemctl.s.istrnol2 = 0;
359 /* R/W The write buffer threshold. */
360 cvmmemctl.s.wbthresh = 10;
361 /* R/W If set, CVMSEG is available for loads/stores in
362 * kernel/debug mode. */
363 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
364 cvmmemctl.s.cvmsegenak = 1;
366 cvmmemctl.s.cvmsegenak = 0;
368 /* R/W If set, CVMSEG is available for loads/stores in
369 * supervisor mode. */
370 cvmmemctl.s.cvmsegenas = 0;
371 /* R/W If set, CVMSEG is available for loads/stores in user
373 cvmmemctl.s.cvmsegenau = 0;
374 /* R/W Size of local memory in cache blocks, 54 (6912 bytes)
375 * is max legal value. */
376 cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE;
379 if (smp_processor_id() == 0)
380 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
381 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
382 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
384 write_c0_cvmmemctl(cvmmemctl.u64);
386 /* Move the performance counter interrupts to IRQ 6 */
387 cvmctl = read_c0_cvmctl();
390 write_c0_cvmctl(cvmctl);
392 /* Set a default for the hardware timeouts */
394 fau_timeout.s.tout_val = 0xfff;
395 /* Disable tagwait FAU timeout */
396 fau_timeout.s.tout_enb = 0;
397 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64);
402 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64);
404 write_octeon_c0_icacheerr(0);
405 write_c0_derraddr1(0);
409 * Early entry point for arch setup
411 void __init prom_init(void)
413 struct cvmx_sysinfo *sysinfo;
414 const int coreid = cvmx_get_core_num();
417 #ifdef CONFIG_CAVIUM_RESERVE32
421 * The bootloader passes a pointer to the boot descriptor in
422 * $a3, this is available as fw_arg3.
424 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3;
426 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
427 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr));
429 sysinfo = cvmx_sysinfo_get();
430 memset(sysinfo, 0, sizeof(*sysinfo));
431 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
432 sysinfo->phy_mem_desc_ptr =
433 cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr);
434 sysinfo->core_mask = octeon_bootinfo->core_mask;
435 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
436 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
437 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
438 sysinfo->board_type = octeon_bootinfo->board_type;
439 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
440 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
441 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
442 sizeof(sysinfo->mac_addr_base));
443 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
444 memcpy(sysinfo->board_serial_number,
445 octeon_bootinfo->board_serial_number,
446 sizeof(sysinfo->board_serial_number));
447 sysinfo->compact_flash_common_base_addr =
448 octeon_bootinfo->compact_flash_common_base_addr;
449 sysinfo->compact_flash_attribute_base_addr =
450 octeon_bootinfo->compact_flash_attribute_base_addr;
451 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
452 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
453 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
455 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
456 /* I/O clock runs at a different rate than the CPU. */
457 union cvmx_mio_rst_boot rst_boot;
458 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
459 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
461 octeon_io_clock_rate = sysinfo->cpu_clock_hz;
465 * Only enable the LED controller if we're running on a CN38XX, CN58XX,
466 * or CN56XX. The CN30XX and CN31XX don't have an LED controller.
468 if (!octeon_is_simulation() &&
469 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) {
470 cvmx_write_csr(CVMX_LED_EN, 0);
471 cvmx_write_csr(CVMX_LED_PRT, 0);
472 cvmx_write_csr(CVMX_LED_DBG, 0);
473 cvmx_write_csr(CVMX_LED_PRT_FMT, 0);
474 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32);
475 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32);
476 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0);
477 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0);
478 cvmx_write_csr(CVMX_LED_EN, 1);
480 #ifdef CONFIG_CAVIUM_RESERVE32
482 * We need to temporarily allocate all memory in the reserve32
483 * region. This makes sure the kernel doesn't allocate this
484 * memory when it is getting memory from the
485 * bootloader. Later, after the memory allocations are
486 * complete, the reserve32 will be freed.
488 * Allocate memory for RESERVED32 aligned on 2MB boundary. This
489 * is in case we later use hugetlb entries with it.
491 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20,
493 "CAVIUM_RESERVE32", 0);
495 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n");
497 octeon_reserve32_memory = addr;
500 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
501 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
502 pr_info("Skipping L2 locking due to reduced L2 cache size\n");
504 uint32_t ebase = read_c0_ebase() & 0x3ffff000;
505 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
507 cvmx_l2c_lock_mem_region(ebase, 0x100);
509 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION
510 /* General exception */
511 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80);
513 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
514 /* Interrupt handler */
515 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80);
517 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT
518 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100);
519 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80);
521 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY
522 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480);
527 octeon_check_cpu_bist();
529 octeon_uart = octeon_get_boot_uart();
532 * Disable All CIU Interrupts. The ones we need will be
533 * enabled later. Read the SUM register so we know the write
536 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0);
537 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
538 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
539 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
540 cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2)));
543 octeon_write_lcd("LinuxSMP");
545 octeon_write_lcd("Linux");
548 #ifdef CONFIG_CAVIUM_GDB
550 * When debugging the linux kernel, force the cores to enter
551 * the debug exception handler to break in.
553 if (octeon_get_boot_debug_flag()) {
554 cvmx_write_csr(CVMX_CIU_DINT, 1 << cvmx_get_core_num());
555 cvmx_read_csr(CVMX_CIU_DINT);
560 * BIST should always be enabled when doing a soft reset. L2
561 * Cache locking for instance is not cleared unless BIST is
562 * enabled. Unfortunately due to a chip errata G-200 for
563 * Cn38XX and CN31XX, BIST msut be disabled on these parts.
565 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
566 OCTEON_IS_MODEL(OCTEON_CN31XX))
567 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0);
569 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1);
571 /* Default to 64MB in the simulator to speed things up */
572 if (octeon_is_simulation())
573 MAX_MEMORY = 64ull << 20;
576 argc = octeon_boot_desc_ptr->argc;
577 for (i = 0; i < argc; i++) {
579 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
580 if ((strncmp(arg, "MEM=", 4) == 0) ||
581 (strncmp(arg, "mem=", 4) == 0)) {
582 sscanf(arg + 4, "%llu", &MAX_MEMORY);
585 MAX_MEMORY = 32ull << 30;
586 } else if (strcmp(arg, "ecc_verbose") == 0) {
587 #ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC
588 __cvmx_interrupt_ecc_report_single_bit_errors = 1;
589 pr_notice("Reporting of single bit ECC errors is "
592 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 <
593 sizeof(arcs_cmdline) - 1) {
594 strcat(arcs_cmdline, " ");
595 strcat(arcs_cmdline, arg);
599 if (strstr(arcs_cmdline, "console=") == NULL) {
600 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
601 strcat(arcs_cmdline, " console=ttyS0,115200");
603 if (octeon_uart == 1)
604 strcat(arcs_cmdline, " console=ttyS1,115200");
606 strcat(arcs_cmdline, " console=ttyS0,115200");
610 if (octeon_is_simulation()) {
612 * The simulator uses a mtdram device pre filled with
613 * the filesystem. Also specify the calibration delay
614 * to avoid calculating it every time.
616 strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824");
619 mips_hpt_frequency = octeon_get_clock_rate();
621 octeon_init_cvmcount();
622 octeon_setup_delays();
624 _machine_restart = octeon_restart;
625 _machine_halt = octeon_halt;
627 octeon_user_io_init();
628 register_smp_ops(&octeon_smp_ops);
631 /* Exclude a single page from the regions obtained in plat_mem_setup. */
632 static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
634 if (addr > *mem && addr < *mem + *size) {
635 u64 inc = addr - *mem;
636 add_memory_region(*mem, inc, BOOT_MEM_RAM);
641 if (addr == *mem && *size > PAGE_SIZE) {
647 void __init plat_mem_setup(void)
649 uint64_t mem_alloc_size;
655 /* First add the init memory we will be returning. */
656 memory = __pa_symbol(&__init_begin) & PAGE_MASK;
657 mem_alloc_size = (__pa_symbol(&__init_end) & PAGE_MASK) - memory;
658 if (mem_alloc_size > 0) {
659 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
660 total += mem_alloc_size;
664 * The Mips memory init uses the first memory location for
665 * some memory vectors. When SPARSEMEM is in use, it doesn't
666 * verify that the size is big enough for the final
667 * vectors. Making the smallest chuck 4MB seems to be enough
668 * to consistantly work.
670 mem_alloc_size = 4 << 20;
671 if (mem_alloc_size > MAX_MEMORY)
672 mem_alloc_size = MAX_MEMORY;
675 * When allocating memory, we want incrementing addresses from
676 * bootmem_alloc so the code in add_memory_region can merge
677 * regions next to each other.
680 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX)
681 && (total < MAX_MEMORY)) {
682 #if defined(CONFIG_64BIT) || defined(CONFIG_64BIT_PHYS_ADDR)
683 memory = cvmx_bootmem_phy_alloc(mem_alloc_size,
684 __pa_symbol(&__init_end), -1,
686 CVMX_BOOTMEM_FLAG_NO_LOCKING);
687 #elif defined(CONFIG_HIGHMEM)
688 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 1ull << 31,
690 CVMX_BOOTMEM_FLAG_NO_LOCKING);
692 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 512 << 20,
694 CVMX_BOOTMEM_FLAG_NO_LOCKING);
697 u64 size = mem_alloc_size;
700 * exclude a page at the beginning and end of
701 * the 256MB PCIe 'hole' so the kernel will not
702 * try to allocate multi-page buffers that
703 * span the discontinuity.
705 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE,
707 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE +
708 CVMX_PCIE_BAR1_PHYS_SIZE,
712 * This function automatically merges address
713 * regions next to each other if they are
714 * received in incrementing order.
717 add_memory_region(memory, size, BOOT_MEM_RAM);
718 total += mem_alloc_size;
723 cvmx_bootmem_unlock();
725 #ifdef CONFIG_CAVIUM_RESERVE32
727 * Now that we've allocated the kernel memory it is safe to
728 * free the reserved region. We free it here so that builtin
729 * drivers can use the memory.
731 if (octeon_reserve32_memory)
732 cvmx_bootmem_free_named("CAVIUM_RESERVE32");
733 #endif /* CONFIG_CAVIUM_RESERVE32 */
736 panic("Unable to allocate memory from "
737 "cvmx_bootmem_phy_alloc\n");
741 * Emit one character to the boot UART. Exported for use by the
744 int prom_putchar(char c)
748 /* Spin until there is room */
750 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart));
751 } while ((lsrval & 0x20) == 0);
754 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);
757 EXPORT_SYMBOL(prom_putchar);
759 void prom_free_prom_memory(void)
761 #ifdef CONFIG_CAVIUM_DECODE_RSL
762 cvmx_interrupt_rsl_enable();
764 /* Add an interrupt handler for general failures. */
765 if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED,
766 "RML/RSL", octeon_rlm_interrupt)) {
767 panic("Unable to request_irq(OCTEON_IRQ_RML)\n");