arch/mips/au1000/common/irq.c

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  *      Au1000 interrupt routines.
   4  *
   5  * Copyright 2001 MontaVista Software Inc.
   6  * Author: MontaVista Software, Inc.
   7  *              ppopov@mvista.com or source@mvista.com
   8  *
   9  *  This program is free software; you can redistribute  it and/or modify it
  10  *  under  the terms of  the GNU General  Public License as published by the
  11  *  Free Software Foundation;  either version 2 of the  License, or (at your
  12  *  option) any later version.
  13  *
  14  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  15  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  16  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  17  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  18  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  20  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  21  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  22  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24  *
  25  *  You should have received a copy of the  GNU General Public License along
  26  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  27  *  675 Mass Ave, Cambridge, MA 02139, USA.
  28  */
  29 #include <linux/config.h>
  30 #include <linux/errno.h>
  31 #include <linux/init.h>
  32 #include <linux/irq.h>
  33 #include <linux/kernel_stat.h>
  34 #include <linux/module.h>
  35 #include <linux/signal.h>
  36 #include <linux/sched.h>
  37 #include <linux/types.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/ioport.h>
  40 #include <linux/timex.h>
  41 #include <linux/slab.h>
  42 #include <linux/random.h>
  43 #include <linux/delay.h>
  44 #include <linux/bitops.h>
  45
  46 #include <asm/bootinfo.h>
  47 #include <asm/io.h>
  48 #include <asm/mipsregs.h>
  49 #include <asm/system.h>
  50 #include <asm/mach-au1x00/au1000.h>
  51 #ifdef CONFIG_MIPS_PB1000
  52 #include <asm/mach-pb1x00/pb1000.h>
  53 #endif
  54
  55 #undef DEBUG_IRQ
  56 #ifdef DEBUG_IRQ
  57 /* note: prints function name for you */
  58 #define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
  59 #else
  60 #define DPRINTK(fmt, args...)
  61 #endif
  62
  63 #define EXT_INTC0_REQ0 2 /* IP 2 */
  64 #define EXT_INTC0_REQ1 3 /* IP 3 */
  65 #define EXT_INTC1_REQ0 4 /* IP 4 */
  66 #define EXT_INTC1_REQ1 5 /* IP 5 */
  67 #define MIPS_TIMER_IP  7 /* IP 7 */
  68
  69 extern asmlinkage void au1000_IRQ(void);
  70 extern void set_debug_traps(void);
  71 extern irq_cpustat_t irq_stat [NR_CPUS];
  72
  73 static void setup_local_irq(unsigned int irq, int type, int int_req);
  74 static unsigned int startup_irq(unsigned int irq);
  75 static void end_irq(unsigned int irq_nr);
  76 static inline void mask_and_ack_level_irq(unsigned int irq_nr);
  77 static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr);
  78 static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr);
  79 static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr);
  80 inline void local_enable_irq(unsigned int irq_nr);
  81 inline void local_disable_irq(unsigned int irq_nr);
  82
  83 void    (*board_init_irq)(void);
  84
  85 #ifdef CONFIG_PM
  86 extern void counter0_irq(int irq, void *dev_id, struct pt_regs *regs);
  87 #endif
  88
  89 static DEFINE_SPINLOCK(irq_lock);
  90
  91
  92 static unsigned int startup_irq(unsigned int irq_nr)
  93 {
  94         local_enable_irq(irq_nr);
  95         return 0;
  96 }
  97
  98
  99 static void shutdown_irq(unsigned int irq_nr)
 100 {
 101         local_disable_irq(irq_nr);
 102         return;
 103 }
 104
 105
 106 inline void local_enable_irq(unsigned int irq_nr)
 107 {
 108         if (irq_nr > AU1000_LAST_INTC0_INT) {
 109                 au_writel(1<<(irq_nr-32), IC1_MASKSET);
 110                 au_writel(1<<(irq_nr-32), IC1_WAKESET);
 111         }
 112         else {
 113                 au_writel(1<<irq_nr, IC0_MASKSET);
 114                 au_writel(1<<irq_nr, IC0_WAKESET);
 115         }
 116         au_sync();
 117 }
 118
 119
 120 inline void local_disable_irq(unsigned int irq_nr)
 121 {
 122         if (irq_nr > AU1000_LAST_INTC0_INT) {
 123                 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
 124                 au_writel(1<<(irq_nr-32), IC1_WAKECLR);
 125         }
 126         else {
 127                 au_writel(1<<irq_nr, IC0_MASKCLR);
 128                 au_writel(1<<irq_nr, IC0_WAKECLR);
 129         }
 130         au_sync();
 131 }
 132
 133
 134 static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
 135 {
 136         if (irq_nr > AU1000_LAST_INTC0_INT) {
 137                 au_writel(1<<(irq_nr-32), IC1_RISINGCLR);
 138                 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
 139         }
 140         else {
 141                 au_writel(1<<irq_nr, IC0_RISINGCLR);
 142                 au_writel(1<<irq_nr, IC0_MASKCLR);
 143         }
 144         au_sync();
 145 }
 146
 147
 148 static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
 149 {
 150         if (irq_nr > AU1000_LAST_INTC0_INT) {
 151                 au_writel(1<<(irq_nr-32), IC1_FALLINGCLR);
 152                 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
 153         }
 154         else {
 155                 au_writel(1<<irq_nr, IC0_FALLINGCLR);
 156                 au_writel(1<<irq_nr, IC0_MASKCLR);
 157         }
 158         au_sync();
 159 }
 160
 161
 162 static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
 163 {
 164         /* This may assume that we don't get interrupts from
 165          * both edges at once, or if we do, that we don't care.
 166          */
 167         if (irq_nr > AU1000_LAST_INTC0_INT) {
 168                 au_writel(1<<(irq_nr-32), IC1_FALLINGCLR);
 169                 au_writel(1<<(irq_nr-32), IC1_RISINGCLR);
 170                 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
 171         }
 172         else {
 173                 au_writel(1<<irq_nr, IC0_FALLINGCLR);
 174                 au_writel(1<<irq_nr, IC0_RISINGCLR);
 175                 au_writel(1<<irq_nr, IC0_MASKCLR);
 176         }
 177         au_sync();
 178 }
 179
 180
 181 static inline void mask_and_ack_level_irq(unsigned int irq_nr)
 182 {
 183
 184         local_disable_irq(irq_nr);
 185         au_sync();
 186 #if defined(CONFIG_MIPS_PB1000)
 187         if (irq_nr == AU1000_GPIO_15) {
 188                 au_writel(0x8000, PB1000_MDR); /* ack int */
 189                 au_sync();
 190         }
 191 #endif
 192         return;
 193 }
 194
 195
 196 static void end_irq(unsigned int irq_nr)
 197 {
 198         if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
 199                 local_enable_irq(irq_nr);
 200         }
 201 #if defined(CONFIG_MIPS_PB1000)
 202         if (irq_nr == AU1000_GPIO_15) {
 203                 au_writel(0x4000, PB1000_MDR); /* enable int */
 204                 au_sync();
 205         }
 206 #endif
 207 }
 208
 209 unsigned long save_local_and_disable(int controller)
 210 {
 211         int i;
 212         unsigned long flags, mask;
 213
 214         spin_lock_irqsave(&irq_lock, flags);
 215         if (controller) {
 216                 mask = au_readl(IC1_MASKSET);
 217                 for (i=32; i<64; i++) {
 218                         local_disable_irq(i);
 219                 }
 220         }
 221         else {
 222                 mask = au_readl(IC0_MASKSET);
 223                 for (i=0; i<32; i++) {
 224                         local_disable_irq(i);
 225                 }
 226         }
 227         spin_unlock_irqrestore(&irq_lock, flags);
 228
 229         return mask;
 230 }
 231
 232 void restore_local_and_enable(int controller, unsigned long mask)
 233 {
 234         int i;
 235         unsigned long flags, new_mask;
 236
 237         spin_lock_irqsave(&irq_lock, flags);
 238         for (i=0; i<32; i++) {
 239                 if (mask & (1<<i)) {
 240                         if (controller)
 241                                 local_enable_irq(i+32);
 242                         else
 243                                 local_enable_irq(i);
 244                 }
 245         }
 246         if (controller)
 247                 new_mask = au_readl(IC1_MASKSET);
 248         else
 249                 new_mask = au_readl(IC0_MASKSET);
 250
 251         spin_unlock_irqrestore(&irq_lock, flags);
 252 }
 253
 254
 255 static struct hw_interrupt_type rise_edge_irq_type = {
 256         .typename = "Au1000 Rise Edge",
 257         .startup = startup_irq,
 258         .shutdown = shutdown_irq,
 259         .enable = local_enable_irq,
 260         .disable = local_disable_irq,
 261         .ack = mask_and_ack_rise_edge_irq,
 262         .end = end_irq,
 263 };
 264
 265 static struct hw_interrupt_type fall_edge_irq_type = {
 266         .typename = "Au1000 Fall Edge",
 267         .startup = startup_irq,
 268         .shutdown = shutdown_irq,
 269         .enable = local_enable_irq,
 270         .disable = local_disable_irq,
 271         .ack = mask_and_ack_fall_edge_irq,
 272         .end = end_irq,
 273 };
 274
 275 static struct hw_interrupt_type either_edge_irq_type = {
 276         .typename = "Au1000 Rise or Fall Edge",
 277         .startup = startup_irq,
 278         .shutdown = shutdown_irq,
 279         .enable = local_enable_irq,
 280         .disable = local_disable_irq,
 281         .ack = mask_and_ack_either_edge_irq,
 282         .end = end_irq,
 283 };
 284
 285 static struct hw_interrupt_type level_irq_type = {
 286         .typename = "Au1000 Level",
 287         .startup = startup_irq,
 288         .shutdown = shutdown_irq,
 289         .enable = local_enable_irq,
 290         .disable = local_disable_irq,
 291         .ack = mask_and_ack_level_irq,
 292         .end = end_irq,
 293 };
 294
 295 #ifdef CONFIG_PM
 296 void startup_match20_interrupt(void)
 297 {
 298         local_enable_irq(AU1000_TOY_MATCH2_INT);
 299 }
 300 #endif
 301
 302 static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
 303 {
 304         if (irq_nr > AU1000_MAX_INTR) return;
 305         /* Config2[n], Config1[n], Config0[n] */
 306         if (irq_nr > AU1000_LAST_INTC0_INT) {
 307                 switch (type) {
 308                         case INTC_INT_RISE_EDGE: /* 0:0:1 */
 309                                 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
 310                                 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
 311                                 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
 312                                 irq_desc[irq_nr].handler = &rise_edge_irq_type;
 313                                 break;
 314                         case INTC_INT_FALL_EDGE: /* 0:1:0 */
 315                                 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
 316                                 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
 317                                 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
 318                                 irq_desc[irq_nr].handler = &fall_edge_irq_type;
 319                                 break;
 320                         case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
 321                                 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
 322                                 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
 323                                 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
 324                                 irq_desc[irq_nr].handler = &either_edge_irq_type;
 325                                 break;
 326                         case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
 327                                 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
 328                                 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
 329                                 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
 330                                 irq_desc[irq_nr].handler = &level_irq_type;
 331                                 break;
 332                         case INTC_INT_LOW_LEVEL: /* 1:1:0 */
 333                                 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
 334                                 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
 335                                 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
 336                                 irq_desc[irq_nr].handler = &level_irq_type;
 337                                 break;
 338                         case INTC_INT_DISABLED: /* 0:0:0 */
 339                                 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
 340                                 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
 341                                 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
 342                                 break;
 343                         default: /* disable the interrupt */
 344                                 printk("unexpected int type %d (irq %d)\n", type, irq_nr);
 345                                 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
 346                                 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
 347                                 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
 348                                 return;
 349                 }
 350                 if (int_req) /* assign to interrupt request 1 */
 351                         au_writel(1<<(irq_nr-32), IC1_ASSIGNCLR);
 352                 else         /* assign to interrupt request 0 */
 353                         au_writel(1<<(irq_nr-32), IC1_ASSIGNSET);
 354                 au_writel(1<<(irq_nr-32), IC1_SRCSET);
 355                 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
 356                 au_writel(1<<(irq_nr-32), IC1_WAKECLR);
 357         }
 358         else {
 359                 switch (type) {
 360                         case INTC_INT_RISE_EDGE: /* 0:0:1 */
 361                                 au_writel(1<<irq_nr, IC0_CFG2CLR);
 362                                 au_writel(1<<irq_nr, IC0_CFG1CLR);
 363                                 au_writel(1<<irq_nr, IC0_CFG0SET);
 364                                 irq_desc[irq_nr].handler = &rise_edge_irq_type;
 365                                 break;
 366                         case INTC_INT_FALL_EDGE: /* 0:1:0 */
 367                                 au_writel(1<<irq_nr, IC0_CFG2CLR);
 368                                 au_writel(1<<irq_nr, IC0_CFG1SET);
 369                                 au_writel(1<<irq_nr, IC0_CFG0CLR);
 370                                 irq_desc[irq_nr].handler = &fall_edge_irq_type;
 371                                 break;
 372                         case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
 373                                 au_writel(1<<irq_nr, IC0_CFG2CLR);
 374                                 au_writel(1<<irq_nr, IC0_CFG1SET);
 375                                 au_writel(1<<irq_nr, IC0_CFG0SET);
 376                                 irq_desc[irq_nr].handler = &either_edge_irq_type;
 377                                 break;
 378                         case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
 379                                 au_writel(1<<irq_nr, IC0_CFG2SET);
 380                                 au_writel(1<<irq_nr, IC0_CFG1CLR);
 381                                 au_writel(1<<irq_nr, IC0_CFG0SET);
 382                                 irq_desc[irq_nr].handler = &level_irq_type;
 383                                 break;
 384                         case INTC_INT_LOW_LEVEL: /* 1:1:0 */
 385                                 au_writel(1<<irq_nr, IC0_CFG2SET);
 386                                 au_writel(1<<irq_nr, IC0_CFG1SET);
 387                                 au_writel(1<<irq_nr, IC0_CFG0CLR);
 388                                 irq_desc[irq_nr].handler = &level_irq_type;
 389                                 break;
 390                         case INTC_INT_DISABLED: /* 0:0:0 */
 391                                 au_writel(1<<irq_nr, IC0_CFG0CLR);
 392                                 au_writel(1<<irq_nr, IC0_CFG1CLR);
 393                                 au_writel(1<<irq_nr, IC0_CFG2CLR);
 394                                 break;
 395                         default: /* disable the interrupt */
 396                                 printk("unexpected int type %d (irq %d)\n", type, irq_nr);
 397                                 au_writel(1<<irq_nr, IC0_CFG0CLR);
 398                                 au_writel(1<<irq_nr, IC0_CFG1CLR);
 399                                 au_writel(1<<irq_nr, IC0_CFG2CLR);
 400                                 return;
 401                 }
 402                 if (int_req) /* assign to interrupt request 1 */
 403                         au_writel(1<<irq_nr, IC0_ASSIGNCLR);
 404                 else         /* assign to interrupt request 0 */
 405                         au_writel(1<<irq_nr, IC0_ASSIGNSET);
 406                 au_writel(1<<irq_nr, IC0_SRCSET);
 407                 au_writel(1<<irq_nr, IC0_MASKCLR);
 408                 au_writel(1<<irq_nr, IC0_WAKECLR);
 409         }
 410         au_sync();
 411 }
 412
 413
 414 void __init arch_init_irq(void)
 415 {
 416         int i;
 417         unsigned long cp0_status;
 418         au1xxx_irq_map_t *imp;
 419         extern au1xxx_irq_map_t au1xxx_irq_map[];
 420         extern au1xxx_irq_map_t au1xxx_ic0_map[];
 421         extern int au1xxx_nr_irqs;
 422         extern int au1xxx_ic0_nr_irqs;
 423
 424         cp0_status = read_c0_status();
 425         memset(irq_desc, 0, sizeof(irq_desc));
 426         set_except_vector(0, au1000_IRQ);
 427
 428         /* Initialize interrupt controllers to a safe state.
 429         */
 430         au_writel(0xffffffff, IC0_CFG0CLR);
 431         au_writel(0xffffffff, IC0_CFG1CLR);
 432         au_writel(0xffffffff, IC0_CFG2CLR);
 433         au_writel(0xffffffff, IC0_MASKCLR);
 434         au_writel(0xffffffff, IC0_ASSIGNSET);
 435         au_writel(0xffffffff, IC0_WAKECLR);
 436         au_writel(0xffffffff, IC0_SRCSET);
 437         au_writel(0xffffffff, IC0_FALLINGCLR);
 438         au_writel(0xffffffff, IC0_RISINGCLR);
 439         au_writel(0x00000000, IC0_TESTBIT);
 440
 441         au_writel(0xffffffff, IC1_CFG0CLR);
 442         au_writel(0xffffffff, IC1_CFG1CLR);
 443         au_writel(0xffffffff, IC1_CFG2CLR);
 444         au_writel(0xffffffff, IC1_MASKCLR);
 445         au_writel(0xffffffff, IC1_ASSIGNSET);
 446         au_writel(0xffffffff, IC1_WAKECLR);
 447         au_writel(0xffffffff, IC1_SRCSET);
 448         au_writel(0xffffffff, IC1_FALLINGCLR);
 449         au_writel(0xffffffff, IC1_RISINGCLR);
 450         au_writel(0x00000000, IC1_TESTBIT);
 451
 452         /* Initialize IC0, which is fixed per processor.
 453         */
 454         imp = au1xxx_ic0_map;
 455         for (i=0; i<au1xxx_ic0_nr_irqs; i++) {
 456                 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
 457                 imp++;
 458         }
 459
 460         /* Now set up the irq mapping for the board.
 461         */
 462         imp = au1xxx_irq_map;
 463         for (i=0; i<au1xxx_nr_irqs; i++) {
 464                 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
 465                 imp++;
 466         }
 467
 468         set_c0_status(ALLINTS);
 469
 470         /* Board specific IRQ initialization.
 471         */
 472         if (board_init_irq)
 473                 (*board_init_irq)();
 474 }
 475
 476
 477 /*
 478  * Interrupts are nested. Even if an interrupt handler is registered
 479  * as "fast", we might get another interrupt before we return from
 480  * intcX_reqX_irqdispatch().
 481  */
 482
 483 void intc0_req0_irqdispatch(struct pt_regs *regs)
 484 {
 485         int irq = 0;
 486         static unsigned long intc0_req0 = 0;
 487
 488         intc0_req0 |= au_readl(IC0_REQ0INT);
 489
 490         if (!intc0_req0) return;
 491
 492         /*
 493          * Because of the tight timing of SETUP token to reply
 494          * transactions, the USB devices-side packet complete
 495          * interrupt needs the highest priority.
 496          */
 497         if ((intc0_req0 & (1<<AU1000_USB_DEV_REQ_INT))) {
 498                 intc0_req0 &= ~(1<<AU1000_USB_DEV_REQ_INT);
 499                 do_IRQ(AU1000_USB_DEV_REQ_INT, regs);
 500                 return;
 501         }
 502
 503         irq = au_ffs(intc0_req0) - 1;
 504         intc0_req0 &= ~(1<<irq);
 505         do_IRQ(irq, regs);
 506 }
 507
 508
 509 void intc0_req1_irqdispatch(struct pt_regs *regs)
 510 {
 511         int irq = 0;
 512         static unsigned long intc0_req1 = 0;
 513
 514         intc0_req1 |= au_readl(IC0_REQ1INT);
 515
 516         if (!intc0_req1) return;
 517
 518         irq = au_ffs(intc0_req1) - 1;
 519         intc0_req1 &= ~(1<<irq);
 520 #ifdef CONFIG_PM
 521         if (irq == AU1000_TOY_MATCH2_INT) {
 522                 mask_and_ack_rise_edge_irq(irq);
 523                 counter0_irq(irq, NULL, regs);
 524                 local_enable_irq(irq);
 525         }
 526         else
 527 #endif
 528         {
 529                 do_IRQ(irq, regs);
 530         }
 531 }
 532
 533
 534 /*
 535  * Interrupt Controller 1:
 536  * interrupts 32 - 63
 537  */
 538 void intc1_req0_irqdispatch(struct pt_regs *regs)
 539 {
 540         int irq = 0;
 541         static unsigned long intc1_req0 = 0;
 542
 543         intc1_req0 |= au_readl(IC1_REQ0INT);
 544
 545         if (!intc1_req0) return;
 546
 547         irq = au_ffs(intc1_req0) - 1;
 548         intc1_req0 &= ~(1<<irq);
 549         irq += 32;
 550         do_IRQ(irq, regs);
 551 }
 552
 553
 554 void intc1_req1_irqdispatch(struct pt_regs *regs)
 555 {
 556         int irq = 0;
 557         static unsigned long intc1_req1 = 0;
 558
 559         intc1_req1 |= au_readl(IC1_REQ1INT);
 560
 561         if (!intc1_req1) return;
 562
 563         irq = au_ffs(intc1_req1) - 1;
 564         intc1_req1 &= ~(1<<irq);
 565         irq += 32;
 566         do_IRQ(irq, regs);
 567 }
 568
 569 #ifdef CONFIG_PM
 570
 571 /* Save/restore the interrupt controller state.
 572  * Called from the save/restore core registers as part of the
 573  * au_sleep function in power.c.....maybe I should just pm_register()
 574  * them instead?
 575  */
 576 static uint     sleep_intctl_config0[2];
 577 static uint     sleep_intctl_config1[2];
 578 static uint     sleep_intctl_config2[2];
 579 static uint     sleep_intctl_src[2];
 580 static uint     sleep_intctl_assign[2];
 581 static uint     sleep_intctl_wake[2];
 582 static uint     sleep_intctl_mask[2];
 583
 584 void
 585 save_au1xxx_intctl(void)
 586 {
 587         sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);
 588         sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);
 589         sleep_intctl_config2[0] = au_readl(IC0_CFG2RD);
 590         sleep_intctl_src[0] = au_readl(IC0_SRCRD);
 591         sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD);
 592         sleep_intctl_wake[0] = au_readl(IC0_WAKERD);
 593         sleep_intctl_mask[0] = au_readl(IC0_MASKRD);
 594
 595         sleep_intctl_config0[1] = au_readl(IC1_CFG0RD);
 596         sleep_intctl_config1[1] = au_readl(IC1_CFG1RD);
 597         sleep_intctl_config2[1] = au_readl(IC1_CFG2RD);
 598         sleep_intctl_src[1] = au_readl(IC1_SRCRD);
 599         sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD);
 600         sleep_intctl_wake[1] = au_readl(IC1_WAKERD);
 601         sleep_intctl_mask[1] = au_readl(IC1_MASKRD);
 602 }
 603
 604 /* For most restore operations, we clear the entire register and
 605  * then set the bits we found during the save.
 606  */
 607 void
 608 restore_au1xxx_intctl(void)
 609 {
 610         au_writel(0xffffffff, IC0_MASKCLR); au_sync();
 611
 612         au_writel(0xffffffff, IC0_CFG0CLR); au_sync();
 613         au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync();
 614         au_writel(0xffffffff, IC0_CFG1CLR); au_sync();
 615         au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync();
 616         au_writel(0xffffffff, IC0_CFG2CLR); au_sync();
 617         au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync();
 618         au_writel(0xffffffff, IC0_SRCCLR); au_sync();
 619         au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync();
 620         au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync();
 621         au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync();
 622         au_writel(0xffffffff, IC0_WAKECLR); au_sync();
 623         au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync();
 624         au_writel(0xffffffff, IC0_RISINGCLR); au_sync();
 625         au_writel(0xffffffff, IC0_FALLINGCLR); au_sync();
 626         au_writel(0x00000000, IC0_TESTBIT); au_sync();
 627
 628         au_writel(0xffffffff, IC1_MASKCLR); au_sync();
 629
 630         au_writel(0xffffffff, IC1_CFG0CLR); au_sync();
 631         au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync();
 632         au_writel(0xffffffff, IC1_CFG1CLR); au_sync();
 633         au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync();
 634         au_writel(0xffffffff, IC1_CFG2CLR); au_sync();
 635         au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync();
 636         au_writel(0xffffffff, IC1_SRCCLR); au_sync();
 637         au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync();
 638         au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync();
 639         au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync();
 640         au_writel(0xffffffff, IC1_WAKECLR); au_sync();
 641         au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync();
 642         au_writel(0xffffffff, IC1_RISINGCLR); au_sync();
 643         au_writel(0xffffffff, IC1_FALLINGCLR); au_sync();
 644         au_writel(0x00000000, IC1_TESTBIT); au_sync();
 645
 646         au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync();
 647
 648         au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync();
 649 }
 650 #endif /* CONFIG_PM */