arch/mips/ath79/irq.c

   1 /*
   2  *  Atheros AR71xx/AR724x/AR913x specific interrupt handling
   3  *
   4  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/irq.h>
  18
  19 #include <asm/irq_cpu.h>
  20 #include <asm/mipsregs.h>
  21
  22 #include <asm/mach-ath79/ath79.h>
  23 #include <asm/mach-ath79/ar71xx_regs.h>
  24 #include "common.h"
  25
  26 static unsigned int ath79_ip2_flush_reg;
  27 static unsigned int ath79_ip3_flush_reg;
  28
  29 static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
  30 {
  31         void __iomem *base = ath79_reset_base;
  32         u32 pending;
  33
  34         pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
  35                   __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
  36
  37         if (pending & MISC_INT_UART)
  38                 generic_handle_irq(ATH79_MISC_IRQ_UART);
  39
  40         else if (pending & MISC_INT_DMA)
  41                 generic_handle_irq(ATH79_MISC_IRQ_DMA);
  42
  43         else if (pending & MISC_INT_PERFC)
  44                 generic_handle_irq(ATH79_MISC_IRQ_PERFC);
  45
  46         else if (pending & MISC_INT_TIMER)
  47                 generic_handle_irq(ATH79_MISC_IRQ_TIMER);
  48
  49         else if (pending & MISC_INT_OHCI)
  50                 generic_handle_irq(ATH79_MISC_IRQ_OHCI);
  51
  52         else if (pending & MISC_INT_ERROR)
  53                 generic_handle_irq(ATH79_MISC_IRQ_ERROR);
  54
  55         else if (pending & MISC_INT_GPIO)
  56                 generic_handle_irq(ATH79_MISC_IRQ_GPIO);
  57
  58         else if (pending & MISC_INT_WDOG)
  59                 generic_handle_irq(ATH79_MISC_IRQ_WDOG);
  60
  61         else
  62                 spurious_interrupt();
  63 }
  64
  65 static void ar71xx_misc_irq_unmask(struct irq_data *d)
  66 {
  67         unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
  68         void __iomem *base = ath79_reset_base;
  69         u32 t;
  70
  71         t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
  72         __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
  73
  74         /* flush write */
  75         __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
  76 }
  77
  78 static void ar71xx_misc_irq_mask(struct irq_data *d)
  79 {
  80         unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
  81         void __iomem *base = ath79_reset_base;
  82         u32 t;
  83
  84         t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
  85         __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
  86
  87         /* flush write */
  88         __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
  89 }
  90
  91 static void ar724x_misc_irq_ack(struct irq_data *d)
  92 {
  93         unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
  94         void __iomem *base = ath79_reset_base;
  95         u32 t;
  96
  97         t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
  98         __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
  99
 100         /* flush write */
 101         __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
 102 }
 103
 104 static struct irq_chip ath79_misc_irq_chip = {
 105         .name           = "MISC",
 106         .irq_unmask     = ar71xx_misc_irq_unmask,
 107         .irq_mask       = ar71xx_misc_irq_mask,
 108 };
 109
 110 static void __init ath79_misc_irq_init(void)
 111 {
 112         void __iomem *base = ath79_reset_base;
 113         int i;
 114
 115         __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
 116         __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
 117
 118         if (soc_is_ar71xx() || soc_is_ar913x())
 119                 ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
 120         else if (soc_is_ar724x())
 121                 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
 122         else
 123                 BUG();
 124
 125         for (i = ATH79_MISC_IRQ_BASE;
 126              i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) {
 127                 irq_set_chip_and_handler(i, &ath79_misc_irq_chip,
 128                                          handle_level_irq);
 129         }
 130
 131         irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
 132 }
 133
 134 asmlinkage void plat_irq_dispatch(void)
 135 {
 136         unsigned long pending;
 137
 138         pending = read_c0_status() & read_c0_cause() & ST0_IM;
 139
 140         if (pending & STATUSF_IP7)
 141                 do_IRQ(ATH79_CPU_IRQ_TIMER);
 142
 143         else if (pending & STATUSF_IP2) {
 144                 ath79_ddr_wb_flush(ath79_ip2_flush_reg);
 145                 do_IRQ(ATH79_CPU_IRQ_IP2);
 146         }
 147
 148         else if (pending & STATUSF_IP4)
 149                 do_IRQ(ATH79_CPU_IRQ_GE0);
 150
 151         else if (pending & STATUSF_IP5)
 152                 do_IRQ(ATH79_CPU_IRQ_GE1);
 153
 154         else if (pending & STATUSF_IP3) {
 155                 ath79_ddr_wb_flush(ath79_ip3_flush_reg);
 156                 do_IRQ(ATH79_CPU_IRQ_USB);
 157         }
 158
 159         else if (pending & STATUSF_IP6)
 160                 do_IRQ(ATH79_CPU_IRQ_MISC);
 161
 162         else
 163                 spurious_interrupt();
 164 }
 165
 166 void __init arch_init_irq(void)
 167 {
 168         if (soc_is_ar71xx()) {
 169                 ath79_ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI;
 170                 ath79_ip3_flush_reg = AR71XX_DDR_REG_FLUSH_USB;
 171         } else if (soc_is_ar724x()) {
 172                 ath79_ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE;
 173                 ath79_ip3_flush_reg = AR724X_DDR_REG_FLUSH_USB;
 174         } else if (soc_is_ar913x()) {
 175                 ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC;
 176                 ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB;
 177         } else
 178                 BUG();
 179
 180         cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC;
 181         mips_cpu_irq_init();
 182         ath79_misc_irq_init();
 183 }