3 * BRIEF MODULE DESCRIPTION
4 * Alchemy Db1x00 board setup.
6 * Copyright 2000, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 #include <linux/gpio.h>
31 #include <linux/init.h>
32 #include <linux/interrupt.h>
35 #include <asm/mach-au1x00/au1000.h>
36 #include <asm/mach-au1x00/au1xxx_eth.h>
37 #include <asm/mach-db1x00/db1x00.h>
38 #include <asm/mach-db1x00/bcsr.h>
39 #include <asm/reboot.h>
43 #ifdef CONFIG_MIPS_BOSPORUS
44 char irq_tab_alchemy[][5] __initdata = {
45 [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */
46 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - SN1741 */
47 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
51 * Micrel/Kendin 5 port switch attached to MAC0,
52 * MAC0 is associated with PHY address 5 (== WAN port)
53 * MAC1 is not associated with any PHY, since it's connected directly
55 * no interrupts are used
57 static struct au1000_eth_platform_data eth0_pdata = {
58 .phy_static_config = 1,
62 static void bosporus_power_off(void)
65 asm volatile (".set mips3 ; wait ; .set mips0");
68 const char *get_system_type(void)
70 return "Alchemy Bosporus Gateway Reference";
75 #ifdef CONFIG_MIPS_MIRAGE
76 static void mirage_power_off(void)
78 alchemy_gpio_direction_output(210, 1);
81 const char *get_system_type(void)
83 return "Alchemy Mirage";
88 #if defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE)
89 static void mips_softreset(void)
91 asm volatile ("jr\t%0" : : "r"(0xbfc00000));
96 const char *get_system_type(void)
98 return "Alchemy Db1x00";
103 void __init board_setup(void)
105 unsigned long bcsr1, bcsr2;
107 bcsr1 = DB1000_BCSR_PHYS_ADDR;
108 bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS;
110 #ifdef CONFIG_MIPS_DB1000
111 printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");
113 #ifdef CONFIG_MIPS_DB1500
114 printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
116 #ifdef CONFIG_MIPS_DB1100
117 printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
119 #ifdef CONFIG_MIPS_BOSPORUS
120 au1xxx_override_eth_cfg(0, ð0_pdata);
122 printk(KERN_INFO "AMD Alchemy Bosporus Board\n");
124 #ifdef CONFIG_MIPS_MIRAGE
125 printk(KERN_INFO "AMD Alchemy Mirage Board\n");
127 #ifdef CONFIG_MIPS_DB1550
128 printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n");
130 bcsr1 = DB1550_BCSR_PHYS_ADDR;
131 bcsr2 = DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS;
134 /* initialize board register space */
135 bcsr_init(bcsr1, bcsr2);
137 #if defined(CONFIG_IRDA) && defined(CONFIG_AU1000_FIR)
141 /* Set IRFIRSEL instead of GPIO15 */
142 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF;
143 au_writel(pin_func, SYS_PINFUNC);
144 /* Power off until the driver is in use */
145 bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK,
146 BCSR_RESETS_IRDA_MODE_OFF);
149 bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */
151 /* Enable GPIO[31:0] inputs */
152 alchemy_gpio1_input_enable();
154 #ifdef CONFIG_MIPS_MIRAGE
158 /* GPIO[20] is output */
159 alchemy_gpio_direction_output(20, 0);
161 /* Set GPIO[210:208] instead of SSI_0 */
162 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0;
164 /* Set GPIO[215:211] for LEDs */
167 /* Set GPIO[214:213] for more LEDs */
170 /* Set GPIO[207:200] instead of PCMCIA/LCD */
171 pin_func |= SYS_PF_LCD | SYS_PF_PC;
172 au_writel(pin_func, SYS_PINFUNC);
175 * Enable speaker amplifier. This should
176 * be part of the audio driver.
178 alchemy_gpio_direction_output(209, 1);
180 pm_power_off = mirage_power_off;
181 _machine_halt = mirage_power_off;
182 _machine_restart = (void(*)(char *))mips_softreset;
186 #ifdef CONFIG_MIPS_BOSPORUS
187 pm_power_off = bosporus_power_off;
188 _machine_halt = bosporus_power_off;
189 _machine_restart = (void(*)(char *))mips_softreset;
194 static int __init db1x00_init_irq(void)
196 #if defined(CONFIG_MIPS_MIRAGE)
197 irq_set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
198 #elif defined(CONFIG_MIPS_DB1550)
199 irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
200 irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */
201 irq_set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */
202 irq_set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
203 irq_set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
204 irq_set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
205 #elif defined(CONFIG_MIPS_DB1500)
206 irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
207 irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
208 irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
209 irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
210 irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
211 irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
212 #elif defined(CONFIG_MIPS_DB1100)
213 irq_set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
214 irq_set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
215 irq_set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
216 irq_set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
217 irq_set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
218 irq_set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
219 #elif defined(CONFIG_MIPS_DB1000)
220 irq_set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
221 irq_set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
222 irq_set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
223 irq_set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
224 irq_set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
225 irq_set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
229 arch_initcall(db1x00_init_irq);