arch/mips/alchemy/common/irq.c

   1 /*
   2  * Copyright 2001, 2007-2008 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc. <source@mvista.com>
   4  *
   5  * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
   6  *
   7  *  This program is free software; you can redistribute  it and/or modify it
   8  *  under  the terms of  the GNU General  Public License as published by the
   9  *  Free Software Foundation;  either version 2 of the  License, or (at your
  10  *  option) any later version.
  11  *
  12  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  13  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  14  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  15  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  16  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  17  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  18  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  19  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  20  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  21  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  22  *
  23  *  You should have received a copy of the  GNU General Public License along
  24  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  25  *  675 Mass Ave, Cambridge, MA 02139, USA.
  26  */
  27
  28 #include <linux/bitops.h>
  29 #include <linux/init.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/irq.h>
  32
  33 #include <asm/irq_cpu.h>
  34 #include <asm/mipsregs.h>
  35 #include <asm/mach-au1x00/au1000.h>
  36 #ifdef CONFIG_MIPS_PB1000
  37 #include <asm/mach-pb1x00/pb1000.h>
  38 #endif
  39
  40 static int au1x_ic_settype(unsigned int irq, unsigned int flow_type);
  41
  42 /* NOTE on interrupt priorities: The original writers of this code said:
  43  *
  44  * Because of the tight timing of SETUP token to reply transactions,
  45  * the USB devices-side packet complete interrupt (USB_DEV_REQ_INT)
  46  * needs the highest priority.
  47  */
  48
  49 /* per-processor fixed function irqs */
  50 struct au1xxx_irqmap {
  51         int im_irq;
  52         int im_type;
  53         int im_request;         /* set 1 to get higher priority */
  54 };
  55
  56 struct au1xxx_irqmap au1000_irqmap[] __initdata = {
  57         { AU1000_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
  58         { AU1000_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
  59         { AU1000_UART2_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
  60         { AU1000_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
  61         { AU1000_SSI0_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
  62         { AU1000_SSI1_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
  63         { AU1000_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  0 },
  64         { AU1000_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  0 },
  65         { AU1000_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  0 },
  66         { AU1000_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  0 },
  67         { AU1000_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  0 },
  68         { AU1000_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  0 },
  69         { AU1000_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  0 },
  70         { AU1000_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  0 },
  71         { AU1000_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
  72         { AU1000_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
  73         { AU1000_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
  74         { AU1000_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
  75         { AU1000_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
  76         { AU1000_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
  77         { AU1000_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
  78         { AU1000_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
  79         { AU1000_IRDA_TX_INT,     IRQ_TYPE_LEVEL_HIGH,  0 },
  80         { AU1000_IRDA_RX_INT,     IRQ_TYPE_LEVEL_HIGH,  0 },
  81         { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },
  82         { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
  83         { AU1000_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   0 },
  84         { AU1000_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 0 },
  85         { AU1000_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
  86         { AU1000_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
  87         { AU1000_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 0 },
  88         { -1, },
  89 };
  90
  91 struct au1xxx_irqmap au1500_irqmap[] __initdata = {
  92         { AU1500_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
  93         { AU1500_PCI_INTA,        IRQ_TYPE_LEVEL_LOW,   0 },
  94         { AU1500_PCI_INTB,        IRQ_TYPE_LEVEL_LOW,   0 },
  95         { AU1500_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
  96         { AU1500_PCI_INTC,        IRQ_TYPE_LEVEL_LOW,   0 },
  97         { AU1500_PCI_INTD,        IRQ_TYPE_LEVEL_LOW,   0 },
  98         { AU1500_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  0 },
  99         { AU1500_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  0 },
 100         { AU1500_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  0 },
 101         { AU1500_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  0 },
 102         { AU1500_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  0 },
 103         { AU1500_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  0 },
 104         { AU1500_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  0 },
 105         { AU1500_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  0 },
 106         { AU1500_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 107         { AU1500_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 108         { AU1500_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 109         { AU1500_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 110         { AU1500_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 111         { AU1500_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 112         { AU1500_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 113         { AU1500_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
 114         { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },
 115         { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
 116         { AU1500_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   0 },
 117         { AU1500_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 0 },
 118         { AU1500_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
 119         { AU1500_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
 120         { AU1500_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 0 },
 121         { -1, },
 122 };
 123
 124 struct au1xxx_irqmap au1100_irqmap[] __initdata = {
 125         { AU1100_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 126         { AU1100_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 127         { AU1100_SD_INT,          IRQ_TYPE_LEVEL_HIGH,  0 },
 128         { AU1100_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 129         { AU1100_SSI0_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 130         { AU1100_SSI1_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 131         { AU1100_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  0 },
 132         { AU1100_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  0 },
 133         { AU1100_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  0 },
 134         { AU1100_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  0 },
 135         { AU1100_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  0 },
 136         { AU1100_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  0 },
 137         { AU1100_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  0 },
 138         { AU1100_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  0 },
 139         { AU1100_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 140         { AU1100_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 141         { AU1100_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 142         { AU1100_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 143         { AU1100_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 144         { AU1100_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 145         { AU1100_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 146         { AU1100_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
 147         { AU1100_IRDA_TX_INT,     IRQ_TYPE_LEVEL_HIGH,  0 },
 148         { AU1100_IRDA_RX_INT,     IRQ_TYPE_LEVEL_HIGH,  0 },
 149         { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },
 150         { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
 151         { AU1100_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   0 },
 152         { AU1100_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 0 },
 153         { AU1100_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
 154         { AU1100_LCD_INT,         IRQ_TYPE_LEVEL_HIGH,  0 },
 155         { AU1100_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 0 },
 156         { -1, },
 157 };
 158
 159 struct au1xxx_irqmap au1550_irqmap[] __initdata = {
 160         { AU1550_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 161         { AU1550_PCI_INTA,        IRQ_TYPE_LEVEL_LOW,   0 },
 162         { AU1550_PCI_INTB,        IRQ_TYPE_LEVEL_LOW,   0 },
 163         { AU1550_DDMA_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 164         { AU1550_CRYPTO_INT,      IRQ_TYPE_LEVEL_HIGH,  0 },
 165         { AU1550_PCI_INTC,        IRQ_TYPE_LEVEL_LOW,   0 },
 166         { AU1550_PCI_INTD,        IRQ_TYPE_LEVEL_LOW,   0 },
 167         { AU1550_PCI_RST_INT,     IRQ_TYPE_LEVEL_LOW,   0 },
 168         { AU1550_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 169         { AU1550_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 170         { AU1550_PSC0_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 171         { AU1550_PSC1_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 172         { AU1550_PSC2_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 173         { AU1550_PSC3_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 174         { AU1550_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 175         { AU1550_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 176         { AU1550_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 177         { AU1550_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 178         { AU1550_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 179         { AU1550_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 180         { AU1550_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 181         { AU1550_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
 182         { AU1550_NAND_INT,        IRQ_TYPE_EDGE_RISING, 0 },
 183         { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },
 184         { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
 185         { AU1550_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   0 },
 186         { AU1550_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
 187         { AU1550_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
 188         { -1, },
 189 };
 190
 191 struct au1xxx_irqmap au1200_irqmap[] __initdata = {
 192         { AU1200_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 193         { AU1200_SWT_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 194         { AU1200_SD_INT,          IRQ_TYPE_LEVEL_HIGH,  0 },
 195         { AU1200_DDMA_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 196         { AU1200_MAE_BE_INT,      IRQ_TYPE_LEVEL_HIGH,  0 },
 197         { AU1200_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 198         { AU1200_MAE_FE_INT,      IRQ_TYPE_LEVEL_HIGH,  0 },
 199         { AU1200_PSC0_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 200         { AU1200_PSC1_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 201         { AU1200_AES_INT,         IRQ_TYPE_LEVEL_HIGH,  0 },
 202         { AU1200_CAMERA_INT,      IRQ_TYPE_LEVEL_HIGH,  0 },
 203         { AU1200_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 204         { AU1200_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 205         { AU1200_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 206         { AU1200_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 207         { AU1200_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 208         { AU1200_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 209         { AU1200_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 210         { AU1200_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
 211         { AU1200_NAND_INT,        IRQ_TYPE_EDGE_RISING, 0 },
 212         { AU1200_USB_INT,         IRQ_TYPE_LEVEL_HIGH,  0 },
 213         { AU1200_LCD_INT,         IRQ_TYPE_LEVEL_HIGH,  0 },
 214         { AU1200_MAE_BOTH_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
 215         { -1, },
 216 };
 217
 218
 219 #ifdef CONFIG_PM
 220
 221 /*
 222  * Save/restore the interrupt controller state.
 223  * Called from the save/restore core registers as part of the
 224  * au_sleep function in power.c.....maybe I should just pm_register()
 225  * them instead?
 226  */
 227 static unsigned int     sleep_intctl_config0[2];
 228 static unsigned int     sleep_intctl_config1[2];
 229 static unsigned int     sleep_intctl_config2[2];
 230 static unsigned int     sleep_intctl_src[2];
 231 static unsigned int     sleep_intctl_assign[2];
 232 static unsigned int     sleep_intctl_wake[2];
 233 static unsigned int     sleep_intctl_mask[2];
 234
 235 void save_au1xxx_intctl(void)
 236 {
 237         sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);
 238         sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);
 239         sleep_intctl_config2[0] = au_readl(IC0_CFG2RD);
 240         sleep_intctl_src[0] = au_readl(IC0_SRCRD);
 241         sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD);
 242         sleep_intctl_wake[0] = au_readl(IC0_WAKERD);
 243         sleep_intctl_mask[0] = au_readl(IC0_MASKRD);
 244
 245         sleep_intctl_config0[1] = au_readl(IC1_CFG0RD);
 246         sleep_intctl_config1[1] = au_readl(IC1_CFG1RD);
 247         sleep_intctl_config2[1] = au_readl(IC1_CFG2RD);
 248         sleep_intctl_src[1] = au_readl(IC1_SRCRD);
 249         sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD);
 250         sleep_intctl_wake[1] = au_readl(IC1_WAKERD);
 251         sleep_intctl_mask[1] = au_readl(IC1_MASKRD);
 252 }
 253
 254 /*
 255  * For most restore operations, we clear the entire register and
 256  * then set the bits we found during the save.
 257  */
 258 void restore_au1xxx_intctl(void)
 259 {
 260         au_writel(0xffffffff, IC0_MASKCLR); au_sync();
 261
 262         au_writel(0xffffffff, IC0_CFG0CLR); au_sync();
 263         au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync();
 264         au_writel(0xffffffff, IC0_CFG1CLR); au_sync();
 265         au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync();
 266         au_writel(0xffffffff, IC0_CFG2CLR); au_sync();
 267         au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync();
 268         au_writel(0xffffffff, IC0_SRCCLR); au_sync();
 269         au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync();
 270         au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync();
 271         au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync();
 272         au_writel(0xffffffff, IC0_WAKECLR); au_sync();
 273         au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync();
 274         au_writel(0xffffffff, IC0_RISINGCLR); au_sync();
 275         au_writel(0xffffffff, IC0_FALLINGCLR); au_sync();
 276         au_writel(0x00000000, IC0_TESTBIT); au_sync();
 277
 278         au_writel(0xffffffff, IC1_MASKCLR); au_sync();
 279
 280         au_writel(0xffffffff, IC1_CFG0CLR); au_sync();
 281         au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync();
 282         au_writel(0xffffffff, IC1_CFG1CLR); au_sync();
 283         au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync();
 284         au_writel(0xffffffff, IC1_CFG2CLR); au_sync();
 285         au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync();
 286         au_writel(0xffffffff, IC1_SRCCLR); au_sync();
 287         au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync();
 288         au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync();
 289         au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync();
 290         au_writel(0xffffffff, IC1_WAKECLR); au_sync();
 291         au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync();
 292         au_writel(0xffffffff, IC1_RISINGCLR); au_sync();
 293         au_writel(0xffffffff, IC1_FALLINGCLR); au_sync();
 294         au_writel(0x00000000, IC1_TESTBIT); au_sync();
 295
 296         au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync();
 297
 298         au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync();
 299 }
 300 #endif /* CONFIG_PM */
 301
 302
 303 static void au1x_ic0_unmask(unsigned int irq_nr)
 304 {
 305         unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
 306         au_writel(1 << bit, IC0_MASKSET);
 307         au_writel(1 << bit, IC0_WAKESET);
 308         au_sync();
 309 }
 310
 311 static void au1x_ic1_unmask(unsigned int irq_nr)
 312 {
 313         unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
 314         au_writel(1 << bit, IC1_MASKSET);
 315         au_writel(1 << bit, IC1_WAKESET);
 316
 317 /* very hacky. does the pb1000 cpld auto-disable this int?
 318  * nowhere in the current kernel sources is it disabled.        --mlau
 319  */
 320 #if defined(CONFIG_MIPS_PB1000)
 321         if (irq_nr == AU1000_GPIO15_INT)
 322                 au_writel(0x4000, PB1000_MDR); /* enable int */
 323 #endif
 324         au_sync();
 325 }
 326
 327 static void au1x_ic0_mask(unsigned int irq_nr)
 328 {
 329         unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
 330         au_writel(1 << bit, IC0_MASKCLR);
 331         au_writel(1 << bit, IC0_WAKECLR);
 332         au_sync();
 333 }
 334
 335 static void au1x_ic1_mask(unsigned int irq_nr)
 336 {
 337         unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
 338         au_writel(1 << bit, IC1_MASKCLR);
 339         au_writel(1 << bit, IC1_WAKECLR);
 340         au_sync();
 341 }
 342
 343 static void au1x_ic0_ack(unsigned int irq_nr)
 344 {
 345         unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
 346
 347         /*
 348          * This may assume that we don't get interrupts from
 349          * both edges at once, or if we do, that we don't care.
 350          */
 351         au_writel(1 << bit, IC0_FALLINGCLR);
 352         au_writel(1 << bit, IC0_RISINGCLR);
 353         au_sync();
 354 }
 355
 356 static void au1x_ic1_ack(unsigned int irq_nr)
 357 {
 358         unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
 359
 360         /*
 361          * This may assume that we don't get interrupts from
 362          * both edges at once, or if we do, that we don't care.
 363          */
 364         au_writel(1 << bit, IC1_FALLINGCLR);
 365         au_writel(1 << bit, IC1_RISINGCLR);
 366         au_sync();
 367 }
 368
 369 static void au1x_ic0_maskack(unsigned int irq_nr)
 370 {
 371         unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
 372
 373         au_writel(1 << bit, IC0_WAKECLR);
 374         au_writel(1 << bit, IC0_MASKCLR);
 375         au_writel(1 << bit, IC0_RISINGCLR);
 376         au_writel(1 << bit, IC0_FALLINGCLR);
 377         au_sync();
 378 }
 379
 380 static void au1x_ic1_maskack(unsigned int irq_nr)
 381 {
 382         unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
 383
 384         au_writel(1 << bit, IC1_WAKECLR);
 385         au_writel(1 << bit, IC1_MASKCLR);
 386         au_writel(1 << bit, IC1_RISINGCLR);
 387         au_writel(1 << bit, IC1_FALLINGCLR);
 388         au_sync();
 389 }
 390
 391 static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
 392 {
 393         int bit = irq - AU1000_INTC1_INT_BASE;
 394         unsigned long wakemsk, flags;
 395
 396         /* only GPIO 0-7 can act as wakeup source.  Fortunately these
 397          * are wired up identically on all supported variants.
 398          */
 399         if ((bit < 0) || (bit > 7))
 400                 return -EINVAL;
 401
 402         local_irq_save(flags);
 403         wakemsk = au_readl(SYS_WAKEMSK);
 404         if (on)
 405                 wakemsk |= 1 << bit;
 406         else
 407                 wakemsk &= ~(1 << bit);
 408         au_writel(wakemsk, SYS_WAKEMSK);
 409         au_sync();
 410         local_irq_restore(flags);
 411
 412         return 0;
 413 }
 414
 415 /*
 416  * irq_chips for both ICs; this way the mask handlers can be
 417  * as short as possible.
 418  */
 419 static struct irq_chip au1x_ic0_chip = {
 420         .name           = "Alchemy-IC0",
 421         .ack            = au1x_ic0_ack,
 422         .mask           = au1x_ic0_mask,
 423         .mask_ack       = au1x_ic0_maskack,
 424         .unmask         = au1x_ic0_unmask,
 425         .set_type       = au1x_ic_settype,
 426 };
 427
 428 static struct irq_chip au1x_ic1_chip = {
 429         .name           = "Alchemy-IC1",
 430         .ack            = au1x_ic1_ack,
 431         .mask           = au1x_ic1_mask,
 432         .mask_ack       = au1x_ic1_maskack,
 433         .unmask         = au1x_ic1_unmask,
 434         .set_type       = au1x_ic_settype,
 435         .set_wake       = au1x_ic1_setwake,
 436 };
 437
 438 static int au1x_ic_settype(unsigned int irq, unsigned int flow_type)
 439 {
 440         struct irq_chip *chip;
 441         unsigned long icr[6];
 442         unsigned int bit, ic;
 443         int ret;
 444
 445         if (irq >= AU1000_INTC1_INT_BASE) {
 446                 bit = irq - AU1000_INTC1_INT_BASE;
 447                 chip = &au1x_ic1_chip;
 448                 ic = 1;
 449         } else {
 450                 bit = irq - AU1000_INTC0_INT_BASE;
 451                 chip = &au1x_ic0_chip;
 452                 ic = 0;
 453         }
 454
 455         if (bit > 31)
 456                 return -EINVAL;
 457
 458         icr[0] = ic ? IC1_CFG0SET : IC0_CFG0SET;
 459         icr[1] = ic ? IC1_CFG1SET : IC0_CFG1SET;
 460         icr[2] = ic ? IC1_CFG2SET : IC0_CFG2SET;
 461         icr[3] = ic ? IC1_CFG0CLR : IC0_CFG0CLR;
 462         icr[4] = ic ? IC1_CFG1CLR : IC0_CFG1CLR;
 463         icr[5] = ic ? IC1_CFG2CLR : IC0_CFG2CLR;
 464
 465         ret = 0;
 466
 467         switch (flow_type) {    /* cfgregs 2:1:0 */
 468         case IRQ_TYPE_EDGE_RISING:      /* 0:0:1 */
 469                 au_writel(1 << bit, icr[5]);
 470                 au_writel(1 << bit, icr[4]);
 471                 au_writel(1 << bit, icr[0]);
 472                 set_irq_chip_and_handler_name(irq, chip,
 473                                 handle_edge_irq, "riseedge");
 474                 break;
 475         case IRQ_TYPE_EDGE_FALLING:     /* 0:1:0 */
 476                 au_writel(1 << bit, icr[5]);
 477                 au_writel(1 << bit, icr[1]);
 478                 au_writel(1 << bit, icr[3]);
 479                 set_irq_chip_and_handler_name(irq, chip,
 480                                 handle_edge_irq, "falledge");
 481                 break;
 482         case IRQ_TYPE_EDGE_BOTH:        /* 0:1:1 */
 483                 au_writel(1 << bit, icr[5]);
 484                 au_writel(1 << bit, icr[1]);
 485                 au_writel(1 << bit, icr[0]);
 486                 set_irq_chip_and_handler_name(irq, chip,
 487                                 handle_edge_irq, "bothedge");
 488                 break;
 489         case IRQ_TYPE_LEVEL_HIGH:       /* 1:0:1 */
 490                 au_writel(1 << bit, icr[2]);
 491                 au_writel(1 << bit, icr[4]);
 492                 au_writel(1 << bit, icr[0]);
 493                 set_irq_chip_and_handler_name(irq, chip,
 494                                 handle_level_irq, "hilevel");
 495                 break;
 496         case IRQ_TYPE_LEVEL_LOW:        /* 1:1:0 */
 497                 au_writel(1 << bit, icr[2]);
 498                 au_writel(1 << bit, icr[1]);
 499                 au_writel(1 << bit, icr[3]);
 500                 set_irq_chip_and_handler_name(irq, chip,
 501                                 handle_level_irq, "lowlevel");
 502                 break;
 503         case IRQ_TYPE_NONE:             /* 0:0:0 */
 504                 au_writel(1 << bit, icr[5]);
 505                 au_writel(1 << bit, icr[4]);
 506                 au_writel(1 << bit, icr[3]);
 507                 /* set at least chip so we can call set_irq_type() on it */
 508                 set_irq_chip(irq, chip);
 509                 break;
 510         default:
 511                 ret = -EINVAL;
 512         }
 513         au_sync();
 514
 515         return ret;
 516 }
 517
 518 asmlinkage void plat_irq_dispatch(void)
 519 {
 520         unsigned int pending = read_c0_status() & read_c0_cause();
 521         unsigned long s, off;
 522
 523         if (pending & CAUSEF_IP7) {
 524                 off = MIPS_CPU_IRQ_BASE + 7;
 525                 goto handle;
 526         } else if (pending & CAUSEF_IP2) {
 527                 s = IC0_REQ0INT;
 528                 off = AU1000_INTC0_INT_BASE;
 529         } else if (pending & CAUSEF_IP3) {
 530                 s = IC0_REQ1INT;
 531                 off = AU1000_INTC0_INT_BASE;
 532         } else if (pending & CAUSEF_IP4) {
 533                 s = IC1_REQ0INT;
 534                 off = AU1000_INTC1_INT_BASE;
 535         } else if (pending & CAUSEF_IP5) {
 536                 s = IC1_REQ1INT;
 537                 off = AU1000_INTC1_INT_BASE;
 538         } else
 539                 goto spurious;
 540
 541         s = au_readl(s);
 542         if (unlikely(!s)) {
 543 spurious:
 544                 spurious_interrupt();
 545                 return;
 546         }
 547         off += __ffs(s);
 548 handle:
 549         do_IRQ(off);
 550 }
 551
 552 static void __init au1000_init_irq(struct au1xxx_irqmap *map)
 553 {
 554         unsigned int bit, irq_nr;
 555         int i;
 556
 557         /*
 558          * Initialize interrupt controllers to a safe state.
 559          */
 560         au_writel(0xffffffff, IC0_CFG0CLR);
 561         au_writel(0xffffffff, IC0_CFG1CLR);
 562         au_writel(0xffffffff, IC0_CFG2CLR);
 563         au_writel(0xffffffff, IC0_MASKCLR);
 564         au_writel(0xffffffff, IC0_ASSIGNCLR);
 565         au_writel(0xffffffff, IC0_WAKECLR);
 566         au_writel(0xffffffff, IC0_SRCSET);
 567         au_writel(0xffffffff, IC0_FALLINGCLR);
 568         au_writel(0xffffffff, IC0_RISINGCLR);
 569         au_writel(0x00000000, IC0_TESTBIT);
 570
 571         au_writel(0xffffffff, IC1_CFG0CLR);
 572         au_writel(0xffffffff, IC1_CFG1CLR);
 573         au_writel(0xffffffff, IC1_CFG2CLR);
 574         au_writel(0xffffffff, IC1_MASKCLR);
 575         au_writel(0xffffffff, IC1_ASSIGNCLR);
 576         au_writel(0xffffffff, IC1_WAKECLR);
 577         au_writel(0xffffffff, IC1_SRCSET);
 578         au_writel(0xffffffff, IC1_FALLINGCLR);
 579         au_writel(0xffffffff, IC1_RISINGCLR);
 580         au_writel(0x00000000, IC1_TESTBIT);
 581
 582         mips_cpu_irq_init();
 583
 584         /* register all 64 possible IC0+IC1 irq sources as type "none".
 585          * Use set_irq_type() to set edge/level behaviour at runtime.
 586          */
 587         for (i = AU1000_INTC0_INT_BASE;
 588              (i < AU1000_INTC0_INT_BASE + 32); i++)
 589                 au1x_ic_settype(i, IRQ_TYPE_NONE);
 590
 591         for (i = AU1000_INTC1_INT_BASE;
 592              (i < AU1000_INTC1_INT_BASE + 32); i++)
 593                 au1x_ic_settype(i, IRQ_TYPE_NONE);
 594
 595         /*
 596          * Initialize IC0, which is fixed per processor.
 597          */
 598         while (map->im_irq != -1) {
 599                 irq_nr = map->im_irq;
 600
 601                 if (irq_nr >= AU1000_INTC1_INT_BASE) {
 602                         bit = irq_nr - AU1000_INTC1_INT_BASE;
 603                         if (map->im_request)
 604                                 au_writel(1 << bit, IC1_ASSIGNSET);
 605                 } else {
 606                         bit = irq_nr - AU1000_INTC0_INT_BASE;
 607                         if (map->im_request)
 608                                 au_writel(1 << bit, IC0_ASSIGNSET);
 609                 }
 610
 611                 au1x_ic_settype(irq_nr, map->im_type);
 612                 ++map;
 613         }
 614
 615         set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3);
 616 }
 617
 618 void __init arch_init_irq(void)
 619 {
 620         switch (alchemy_get_cputype()) {
 621         case ALCHEMY_CPU_AU1000:
 622                 au1000_init_irq(au1000_irqmap);
 623                 break;
 624         case ALCHEMY_CPU_AU1500:
 625                 au1000_init_irq(au1500_irqmap);
 626                 break;
 627         case ALCHEMY_CPU_AU1100:
 628                 au1000_init_irq(au1100_irqmap);
 629                 break;
 630         case ALCHEMY_CPU_AU1550:
 631                 au1000_init_irq(au1550_irqmap);
 632                 break;
 633         case ALCHEMY_CPU_AU1200:
 634                 au1000_init_irq(au1200_irqmap);
 635                 break;
 636         }
 637 }