2 * m54xxsim.h -- ColdFire 547x/548x System Integration Unit support.
8 #define CPU_NAME "COLDFIRE(m54xx)"
9 #define CPU_INSTR_PER_JIFFY 2
11 #include <asm/m54xxacr.h>
13 #define MCFINT_VECBASE 64
16 * Interrupt Controller Registers
18 #define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */
20 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
21 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
22 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
23 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
24 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
25 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
26 #define MCFINTC_IRLR 0x18 /* */
27 #define MCFINTC_IACKL 0x19 /* */
28 #define MCFINTC_ICR0 0x40 /* Base ICR register */
33 #define MCFUART_BASE1 0x8600 /* Base address of UART1 */
34 #define MCFUART_BASE2 0x8700 /* Base address of UART2 */
35 #define MCFUART_BASE3 0x8800 /* Base address of UART3 */
36 #define MCFUART_BASE4 0x8900 /* Base address of UART4 */
39 * Define system peripheral IRQ usage.
41 #define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */
42 #define MCF_IRQ_PROFILER (64 + 53) /* Slice Timer 1 */
45 * Generic GPIO support
47 #define MCFGPIO_PIN_MAX 0 /* I am too lazy to count */
48 #define MCFGPIO_IRQ_MAX -1
49 #define MCFGPIO_IRQ_VECBASE -1
52 * Some PSC related definitions
54 #define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3))
55 #define MCF_PAR_SDA (0x0008)
56 #define MCF_PAR_SCL (0x0004)
57 #define MCF_PAR_PSC_TXD (0x04)
58 #define MCF_PAR_PSC_RXD (0x08)
59 #define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4)
60 #define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6)
61 #define MCF_PAR_PSC_CTS_GPIO (0x00)
62 #define MCF_PAR_PSC_CTS_BCLK (0x80)
63 #define MCF_PAR_PSC_CTS_CTS (0xC0)
64 #define MCF_PAR_PSC_RTS_GPIO (0x00)
65 #define MCF_PAR_PSC_RTS_FSYNC (0x20)
66 #define MCF_PAR_PSC_RTS_RTS (0x30)
67 #define MCF_PAR_PSC_CANRX (0x40)
69 #endif /* m54xxsim_h */