2 * linux/arch/m32r/platforms/m32700ut/setup.c
4 * Setup routines for Renesas M32700UT Board
6 * Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata,
7 * Hitoshi Yamamoto, Takeo Takahashi
9 * This file is subject to the terms and conditions of the GNU General
10 * Public License. See the file "COPYING" in the main directory of this
11 * archive for more details.
14 #include <linux/irq.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/platform_device.h>
19 #include <asm/system.h>
24 * M32700 Interrupt Control Unit (Level 1)
26 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
28 icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
30 static void disable_m32700ut_irq(unsigned int irq)
32 unsigned long port, data;
35 data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
39 static void enable_m32700ut_irq(unsigned int irq)
41 unsigned long port, data;
44 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
48 static void mask_m32700ut(struct irq_data *data)
50 disable_m32700ut_irq(data->irq);
53 static void unmask_m32700ut(struct irq_data *data)
55 enable_m32700ut_irq(data->irq);
58 static void shutdown_m32700ut(struct irq_data *data)
62 port = irq2port(data->irq);
63 outl(M32R_ICUCR_ILEVEL7, port);
66 static struct irq_chip m32700ut_irq_type =
68 .name = "M32700UT-IRQ",
69 .irq_shutdown = shutdown_m32700ut,
70 .irq_mask = mask_m32700ut,
71 .irq_unmask = unmask_m32700ut
75 * Interrupt Control Unit of PLD on M32700UT (Level 2)
77 #define irq2pldirq(x) ((x) - M32700UT_PLD_IRQ_BASE)
78 #define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
79 (((x) - 1) * sizeof(unsigned short)))
82 unsigned short icucr; /* ICU Control Register */
85 static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
87 static void disable_m32700ut_pld_irq(unsigned int irq)
89 unsigned long port, data;
92 pldirq = irq2pldirq(irq);
93 // disable_m32700ut_irq(M32R_IRQ_INT1);
94 port = pldirq2port(pldirq);
95 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
99 static void enable_m32700ut_pld_irq(unsigned int irq)
101 unsigned long port, data;
104 pldirq = irq2pldirq(irq);
105 // enable_m32700ut_irq(M32R_IRQ_INT1);
106 port = pldirq2port(pldirq);
107 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
111 static void mask_and_ack_m32700ut_pld(unsigned int irq)
113 disable_m32700ut_pld_irq(irq);
114 // mask_and_ack_m32700ut(M32R_IRQ_INT1);
117 static void end_m32700ut_pld_irq(unsigned int irq)
119 enable_m32700ut_pld_irq(irq);
120 enable_m32700ut_irq(M32R_IRQ_INT1);
123 static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
125 enable_m32700ut_pld_irq(irq);
129 static void shutdown_m32700ut_pld_irq(unsigned int irq)
134 pldirq = irq2pldirq(irq);
135 // shutdown_m32700ut_irq(M32R_IRQ_INT1);
136 port = pldirq2port(pldirq);
137 outw(PLD_ICUCR_ILEVEL7, port);
140 static struct irq_chip m32700ut_pld_irq_type =
142 .name = "M32700UT-PLD-IRQ",
143 .startup = startup_m32700ut_pld_irq,
144 .shutdown = shutdown_m32700ut_pld_irq,
145 .enable = enable_m32700ut_pld_irq,
146 .disable = disable_m32700ut_pld_irq,
147 .ack = mask_and_ack_m32700ut_pld,
148 .end = end_m32700ut_pld_irq
152 * Interrupt Control Unit of PLD on M32700UT-LAN (Level 2)
154 #define irq2lanpldirq(x) ((x) - M32700UT_LAN_PLD_IRQ_BASE)
155 #define lanpldirq2port(x) (unsigned long)((int)M32700UT_LAN_ICUCR1 + \
156 (((x) - 1) * sizeof(unsigned short)))
158 static pld_icu_data_t lanpld_icu_data[M32700UT_NUM_LAN_PLD_IRQ];
160 static void disable_m32700ut_lanpld_irq(unsigned int irq)
162 unsigned long port, data;
165 pldirq = irq2lanpldirq(irq);
166 port = lanpldirq2port(pldirq);
167 data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
171 static void enable_m32700ut_lanpld_irq(unsigned int irq)
173 unsigned long port, data;
176 pldirq = irq2lanpldirq(irq);
177 port = lanpldirq2port(pldirq);
178 data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
182 static void mask_and_ack_m32700ut_lanpld(unsigned int irq)
184 disable_m32700ut_lanpld_irq(irq);
187 static void end_m32700ut_lanpld_irq(unsigned int irq)
189 enable_m32700ut_lanpld_irq(irq);
190 enable_m32700ut_irq(M32R_IRQ_INT0);
193 static unsigned int startup_m32700ut_lanpld_irq(unsigned int irq)
195 enable_m32700ut_lanpld_irq(irq);
199 static void shutdown_m32700ut_lanpld_irq(unsigned int irq)
204 pldirq = irq2lanpldirq(irq);
205 port = lanpldirq2port(pldirq);
206 outw(PLD_ICUCR_ILEVEL7, port);
209 static struct irq_chip m32700ut_lanpld_irq_type =
211 .name = "M32700UT-PLD-LAN-IRQ",
212 .startup = startup_m32700ut_lanpld_irq,
213 .shutdown = shutdown_m32700ut_lanpld_irq,
214 .enable = enable_m32700ut_lanpld_irq,
215 .disable = disable_m32700ut_lanpld_irq,
216 .ack = mask_and_ack_m32700ut_lanpld,
217 .end = end_m32700ut_lanpld_irq
221 * Interrupt Control Unit of PLD on M32700UT-LCD (Level 2)
223 #define irq2lcdpldirq(x) ((x) - M32700UT_LCD_PLD_IRQ_BASE)
224 #define lcdpldirq2port(x) (unsigned long)((int)M32700UT_LCD_ICUCR1 + \
225 (((x) - 1) * sizeof(unsigned short)))
227 static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ];
229 static void disable_m32700ut_lcdpld_irq(unsigned int irq)
231 unsigned long port, data;
234 pldirq = irq2lcdpldirq(irq);
235 port = lcdpldirq2port(pldirq);
236 data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
240 static void enable_m32700ut_lcdpld_irq(unsigned int irq)
242 unsigned long port, data;
245 pldirq = irq2lcdpldirq(irq);
246 port = lcdpldirq2port(pldirq);
247 data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
251 static void mask_and_ack_m32700ut_lcdpld(unsigned int irq)
253 disable_m32700ut_lcdpld_irq(irq);
256 static void end_m32700ut_lcdpld_irq(unsigned int irq)
258 enable_m32700ut_lcdpld_irq(irq);
259 enable_m32700ut_irq(M32R_IRQ_INT2);
262 static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq)
264 enable_m32700ut_lcdpld_irq(irq);
268 static void shutdown_m32700ut_lcdpld_irq(unsigned int irq)
273 pldirq = irq2lcdpldirq(irq);
274 port = lcdpldirq2port(pldirq);
275 outw(PLD_ICUCR_ILEVEL7, port);
278 static struct irq_chip m32700ut_lcdpld_irq_type =
280 .name = "M32700UT-PLD-LCD-IRQ",
281 .startup = startup_m32700ut_lcdpld_irq,
282 .shutdown = shutdown_m32700ut_lcdpld_irq,
283 .enable = enable_m32700ut_lcdpld_irq,
284 .disable = disable_m32700ut_lcdpld_irq,
285 .ack = mask_and_ack_m32700ut_lcdpld,
286 .end = end_m32700ut_lcdpld_irq
289 void __init init_IRQ(void)
291 #if defined(CONFIG_SMC91X)
292 /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
293 set_irq_chip(M32700UT_LAN_IRQ_LAN, &m32700ut_lanpld_irq_type);
294 lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
295 disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
296 #endif /* CONFIG_SMC91X */
298 /* MFT2 : system timer */
299 set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type,
301 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
302 disable_m32700ut_irq(M32R_IRQ_MFT2);
305 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type,
307 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
308 disable_m32700ut_irq(M32R_IRQ_SIO0_R);
311 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type,
313 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
314 disable_m32700ut_irq(M32R_IRQ_SIO0_S);
317 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type,
319 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
320 disable_m32700ut_irq(M32R_IRQ_SIO1_R);
323 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type,
325 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
326 disable_m32700ut_irq(M32R_IRQ_SIO1_S);
329 set_irq_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type,
331 icu_data[M32R_IRQ_DMA1].icucr = 0;
332 disable_m32700ut_irq(M32R_IRQ_DMA1);
334 #ifdef CONFIG_SERIAL_M32R_PLDSIO
335 /* INT#1: SIO0 Receive on PLD */
336 set_irq_chip(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type);
337 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
338 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
340 /* INT#1: SIO0 Send on PLD */
341 set_irq_chip(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type);
342 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
343 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
344 #endif /* CONFIG_SERIAL_M32R_PLDSIO */
346 /* INT#1: CFC IREQ on PLD */
347 set_irq_chip(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type);
348 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
349 disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
351 /* INT#1: CFC Insert on PLD */
352 set_irq_chip(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type);
353 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
354 disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
356 /* INT#1: CFC Eject on PLD */
357 set_irq_chip(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type);
358 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
359 disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
362 * INT0# is used for LAN, DIO
365 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
366 enable_m32700ut_irq(M32R_IRQ_INT0);
369 * INT1# is used for UART, MMC, CF Controller in FPGA.
372 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
373 enable_m32700ut_irq(M32R_IRQ_INT1);
375 #if defined(CONFIG_USB)
376 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
377 set_irq_chip(M32700UT_LCD_IRQ_USB_INT1, &m32700ut_lcdpld_irq_type);
379 lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
380 disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
383 * INT2# is used for BAT, USB, AUDIO
386 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
387 enable_m32700ut_irq(M32R_IRQ_INT2);
389 #if defined(CONFIG_VIDEO_M32R_AR)
391 * INT3# is used for AR
393 set_irq_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type,
395 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
396 disable_m32700ut_irq(M32R_IRQ_INT3);
397 #endif /* CONFIG_VIDEO_M32R_AR */
400 #if defined(CONFIG_SMC91X)
402 #define LAN_IOSTART 0x300
403 #define LAN_IOEND 0x320
404 static struct resource smc91x_resources[] = {
406 .start = (LAN_IOSTART),
408 .flags = IORESOURCE_MEM,
411 .start = M32700UT_LAN_IRQ_LAN,
412 .end = M32700UT_LAN_IRQ_LAN,
413 .flags = IORESOURCE_IRQ,
417 static struct platform_device smc91x_device = {
420 .num_resources = ARRAY_SIZE(smc91x_resources),
421 .resource = smc91x_resources,
425 #if defined(CONFIG_FB_S1D13XXX)
427 #include <video/s1d13xxxfb.h>
428 #include <asm/s1d13806.h>
430 static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
431 .initregs = s1d13xxxfb_initregs,
432 .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
433 .platform_init_video = NULL,
435 .platform_suspend_video = NULL,
436 .platform_resume_video = NULL,
440 static struct resource s1d13xxxfb_resources[] = {
442 .start = 0x10600000UL,
444 .flags = IORESOURCE_MEM,
447 .start = 0x10400000UL,
449 .flags = IORESOURCE_MEM,
453 static struct platform_device s1d13xxxfb_device = {
454 .name = S1D_DEVICENAME,
457 .platform_data = &s1d13xxxfb_data,
459 .num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
460 .resource = s1d13xxxfb_resources,
464 static int __init platform_init(void)
466 #if defined(CONFIG_SMC91X)
467 platform_device_register(&smc91x_device);
469 #if defined(CONFIG_FB_S1D13XXX)
470 platform_device_register(&s1d13xxxfb_device);
474 arch_initcall(platform_init);