arch/ia64/sn/pci/pcibr/pcibr_provider.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2001-2004 Silicon Graphics, Inc. All rights reserved.
   7  */
   8
   9 #include <linux/interrupt.h>
  10 #include <linux/types.h>
  11 #include <linux/pci.h>
  12 #include <asm/sn/addrs.h>
  13 #include <asm/sn/geo.h>
  14 #include <asm/sn/pcibr_provider.h>
  15 #include <asm/sn/pcibus_provider_defs.h>
  16 #include <asm/sn/pcidev.h>
  17 #include <asm/sn/sn_sal.h>
  18 #include <asm/sn/sn2/sn_hwperf.h>
  19 #include "xtalk/xwidgetdev.h"
  20 #include "xtalk/hubdev.h"
  21
  22 int
  23 sal_pcibr_slot_enable(struct pcibus_info *soft, int device, void *resp)
  24 {
  25         struct ia64_sal_retval ret_stuff;
  26         u64 busnum;
  27         u64 segment;
  28
  29         ret_stuff.status = 0;
  30         ret_stuff.v0 = 0;
  31
  32         segment = soft->pbi_buscommon.bs_persist_segment;
  33         busnum = soft->pbi_buscommon.bs_persist_busnum;
  34         SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_SLOT_ENABLE, segment,
  35                         busnum, (u64) device, (u64) resp, 0, 0, 0);
  36
  37         return (int)ret_stuff.v0;
  38 }
  39
  40 int
  41 sal_pcibr_slot_disable(struct pcibus_info *soft, int device, int action,
  42                        void *resp)
  43 {
  44         struct ia64_sal_retval ret_stuff;
  45         u64 busnum;
  46         u64 segment;
  47
  48         ret_stuff.status = 0;
  49         ret_stuff.v0 = 0;
  50
  51         segment = soft->pbi_buscommon.bs_persist_segment;
  52         busnum = soft->pbi_buscommon.bs_persist_busnum;
  53         SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_SLOT_DISABLE,
  54                         segment, busnum, (u64) device, (u64) action,
  55                         (u64) resp, 0, 0);
  56
  57         return (int)ret_stuff.v0;
  58 }
  59
  60 static int sal_pcibr_error_interrupt(struct pcibus_info *soft)
  61 {
  62         struct ia64_sal_retval ret_stuff;
  63         u64 busnum;
  64         int segment;
  65         ret_stuff.status = 0;
  66         ret_stuff.v0 = 0;
  67
  68         segment = soft->pbi_buscommon.bs_persist_segment;
  69         busnum = soft->pbi_buscommon.bs_persist_busnum;
  70         SAL_CALL_NOLOCK(ret_stuff,
  71                         (u64) SN_SAL_IOIF_ERROR_INTERRUPT,
  72                         (u64) segment, (u64) busnum, 0, 0, 0, 0, 0);
  73
  74         return (int)ret_stuff.v0;
  75 }
  76
  77 /*
  78  * PCI Bridge Error interrupt handler.  Gets invoked whenever a PCI
  79  * bridge sends an error interrupt.
  80  */
  81 static irqreturn_t
  82 pcibr_error_intr_handler(int irq, void *arg, struct pt_regs *regs)
  83 {
  84         struct pcibus_info *soft = (struct pcibus_info *)arg;
  85
  86         if (sal_pcibr_error_interrupt(soft) < 0) {
  87                 panic("pcibr_error_intr_handler(): Fatal Bridge Error");
  88         }
  89         return IRQ_HANDLED;
  90 }
  91
  92 void *
  93 pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller)
  94 {
  95         int nasid, cnode, j;
  96         cnodeid_t near_cnode;
  97         struct hubdev_info *hubdev_info;
  98         struct pcibus_info *soft;
  99         struct sn_flush_device_kernel *sn_flush_device_kernel;
 100         struct sn_flush_device_common *common;
 101
 102         if (! IS_PCI_BRIDGE_ASIC(prom_bussoft->bs_asic_type)) {
 103                 return NULL;
 104         }
 105
 106         /*
 107          * Allocate kernel bus soft and copy from prom.
 108          */
 109
 110         soft = kmalloc(sizeof(struct pcibus_info), GFP_KERNEL);
 111         if (!soft) {
 112                 return NULL;
 113         }
 114
 115         memcpy(soft, prom_bussoft, sizeof(struct pcibus_info));
 116         soft->pbi_buscommon.bs_base =
 117             (((u64) soft->pbi_buscommon.
 118               bs_base << 4) >> 4) | __IA64_UNCACHED_OFFSET;
 119
 120         spin_lock_init(&soft->pbi_lock);
 121
 122         /*
 123          * register the bridge's error interrupt handler
 124          */
 125         if (request_irq(SGI_PCIASIC_ERROR, (void *)pcibr_error_intr_handler,
 126                         SA_SHIRQ, "PCIBR error", (void *)(soft))) {
 127                 printk(KERN_WARNING
 128                        "pcibr cannot allocate interrupt for error handler\n");
 129         }
 130
 131         /*
 132          * Update the Bridge with the "kernel" pagesize
 133          */
 134         if (PAGE_SIZE < 16384) {
 135                 pcireg_control_bit_clr(soft, PCIBR_CTRL_PAGE_SIZE);
 136         } else {
 137                 pcireg_control_bit_set(soft, PCIBR_CTRL_PAGE_SIZE);
 138         }
 139
 140         nasid = NASID_GET(soft->pbi_buscommon.bs_base);
 141         cnode = nasid_to_cnodeid(nasid);
 142         hubdev_info = (struct hubdev_info *)(NODEPDA(cnode)->pdinfo);
 143
 144         if (hubdev_info->hdi_flush_nasid_list.widget_p) {
 145                 sn_flush_device_kernel = hubdev_info->hdi_flush_nasid_list.
 146                     widget_p[(int)soft->pbi_buscommon.bs_xid];
 147                 if (sn_flush_device_kernel) {
 148                         for (j = 0; j < DEV_PER_WIDGET;
 149                              j++, sn_flush_device_kernel++) {
 150                                 common = sn_flush_device_kernel->common;
 151                                 if (common->sfdl_slot == -1)
 152                                         continue;
 153                                 if ((common->sfdl_persistent_segment ==
 154                                      soft->pbi_buscommon.bs_persist_segment) &&
 155                                      (common->sfdl_persistent_busnum ==
 156                                      soft->pbi_buscommon.bs_persist_busnum))
 157                                         common->sfdl_pcibus_info =
 158                                             soft;
 159                         }
 160                 }
 161         }
 162
 163         /* Setup the PMU ATE map */
 164         soft->pbi_int_ate_resource.lowest_free_index = 0;
 165         soft->pbi_int_ate_resource.ate =
 166             kmalloc(soft->pbi_int_ate_size * sizeof(u64), GFP_KERNEL);
 167         memset(soft->pbi_int_ate_resource.ate, 0,
 168                (soft->pbi_int_ate_size * sizeof(u64)));
 169
 170         if (prom_bussoft->bs_asic_type == PCIIO_ASIC_TYPE_TIOCP) {
 171                 /* TIO PCI Bridge: find nearest node with CPUs */
 172                 int e = sn_hwperf_get_nearest_node(cnode, NULL, &near_cnode);
 173
 174                 if (e < 0) {
 175                         near_cnode = (cnodeid_t)-1; /* use any node */
 176                         printk(KERN_WARNING "pcibr_bus_fixup: failed to find "
 177                                 "near node with CPUs to TIO node %d, err=%d\n",
 178                                 cnode, e);
 179                 }
 180                 controller->node = near_cnode;
 181         }
 182         else
 183                 controller->node = cnode;
 184         return soft;
 185 }
 186
 187 void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info)
 188 {
 189         struct pcidev_info *pcidev_info;
 190         struct pcibus_info *pcibus_info;
 191         int bit = sn_irq_info->irq_int_bit;
 192
 193         if (! sn_irq_info->irq_bridge)
 194                 return;
 195
 196         pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
 197         if (pcidev_info) {
 198                 pcibus_info =
 199                     (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
 200                     pdi_pcibus_info;
 201                 pcireg_force_intr_set(pcibus_info, bit);
 202         }
 203 }
 204
 205 void pcibr_target_interrupt(struct sn_irq_info *sn_irq_info)
 206 {
 207         struct pcidev_info *pcidev_info;
 208         struct pcibus_info *pcibus_info;
 209         int bit = sn_irq_info->irq_int_bit;
 210         u64 xtalk_addr = sn_irq_info->irq_xtalkaddr;
 211
 212         pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
 213         if (pcidev_info) {
 214                 pcibus_info =
 215                     (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
 216                     pdi_pcibus_info;
 217
 218                 /* Disable the device's IRQ   */
 219                 pcireg_intr_enable_bit_clr(pcibus_info, (1 << bit));
 220
 221                 /* Change the device's IRQ    */
 222                 pcireg_intr_addr_addr_set(pcibus_info, bit, xtalk_addr);
 223
 224                 /* Re-enable the device's IRQ */
 225                 pcireg_intr_enable_bit_set(pcibus_info, (1 << bit));
 226
 227                 pcibr_force_interrupt(sn_irq_info);
 228         }
 229 }
 230
 231 /*
 232  * Provider entries for PIC/CP
 233  */
 234
 235 struct sn_pcibus_provider pcibr_provider = {
 236         .dma_map = pcibr_dma_map,
 237         .dma_map_consistent = pcibr_dma_map_consistent,
 238         .dma_unmap = pcibr_dma_unmap,
 239         .bus_fixup = pcibr_bus_fixup,
 240         .force_interrupt = pcibr_force_interrupt,
 241         .target_interrupt = pcibr_target_interrupt
 242 };
 243
 244 int
 245 pcibr_init_provider(void)
 246 {
 247         sn_pci_provider[PCIIO_ASIC_TYPE_PIC] = &pcibr_provider;
 248         sn_pci_provider[PCIIO_ASIC_TYPE_TIOCP] = &pcibr_provider;
 249
 250         return 0;
 251 }
 252
 253 EXPORT_SYMBOL_GPL(sal_pcibr_slot_enable);
 254 EXPORT_SYMBOL_GPL(sal_pcibr_slot_disable);