arch/ia64/kernel/mca.c

   1 /*
   2  * File:        mca.c
   3  * Purpose:     Generic MCA handling layer
   4  *
   5  * Updated for latest kernel
   6  * Copyright (C) 2003 Hewlett-Packard Co
   7  *      David Mosberger-Tang <davidm@hpl.hp.com>
   8  *
   9  * Copyright (C) 2002 Dell Inc.
  10  * Copyright (C) Matt Domsch (Matt_Domsch@dell.com)
  11  *
  12  * Copyright (C) 2002 Intel
  13  * Copyright (C) Jenna Hall (jenna.s.hall@intel.com)
  14  *
  15  * Copyright (C) 2001 Intel
  16  * Copyright (C) Fred Lewis (frederick.v.lewis@intel.com)
  17  *
  18  * Copyright (C) 2000 Intel
  19  * Copyright (C) Chuck Fleckenstein (cfleck@co.intel.com)
  20  *
  21  * Copyright (C) 1999, 2004 Silicon Graphics, Inc.
  22  * Copyright (C) Vijay Chander(vijay@engr.sgi.com)
  23  *
  24  * 03/04/15 D. Mosberger Added INIT backtrace support.
  25  * 02/03/25 M. Domsch   GUID cleanups
  26  *
  27  * 02/01/04 J. Hall     Aligned MCA stack to 16 bytes, added platform vs. CPU
  28  *                      error flag, set SAL default return values, changed
  29  *                      error record structure to linked list, added init call
  30  *                      to sal_get_state_info_size().
  31  *
  32  * 01/01/03 F. Lewis    Added setup of CMCI and CPEI IRQs, logging of corrected
  33  *                      platform errors, completed code for logging of
  34  *                      corrected & uncorrected machine check errors, and
  35  *                      updated for conformance with Nov. 2000 revision of the
  36  *                      SAL 3.0 spec.
  37  * 00/03/29 C. Fleckenstein  Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
  38  *                           added min save state dump, added INIT handler.
  39  *
  40  * 2003-12-08 Keith Owens <kaos@sgi.com>
  41  *            smp_call_function() must not be called from interrupt context (can
  42  *            deadlock on tasklist_lock).  Use keventd to call smp_call_function().
  43  *
  44  * 2004-02-01 Keith Owens <kaos@sgi.com>
  45  *            Avoid deadlock when using printk() for MCA and INIT records.
  46  *            Delete all record printing code, moved to salinfo_decode in user space.
  47  *            Mark variables and functions static where possible.
  48  *            Delete dead variables and functions.
  49  *            Reorder to remove the need for forward declarations and to consolidate
  50  *            related code.
  51  *
  52  * 2005-08-12 Keith Owens <kaos@sgi.com>
  53  *            Convert MCA/INIT handlers to use per event stacks and SAL/OS state.
  54  *
  55  * 2005-10-07 Keith Owens <kaos@sgi.com>
  56  *            Add notify_die() hooks.
  57  */
  58 #include <linux/config.h>
  59 #include <linux/types.h>
  60 #include <linux/init.h>
  61 #include <linux/sched.h>
  62 #include <linux/interrupt.h>
  63 #include <linux/irq.h>
  64 #include <linux/smp_lock.h>
  65 #include <linux/bootmem.h>
  66 #include <linux/acpi.h>
  67 #include <linux/timer.h>
  68 #include <linux/module.h>
  69 #include <linux/kernel.h>
  70 #include <linux/smp.h>
  71 #include <linux/workqueue.h>
  72 #include <linux/cpumask.h>
  73
  74 #include <asm/delay.h>
  75 #include <asm/kdebug.h>
  76 #include <asm/machvec.h>
  77 #include <asm/meminit.h>
  78 #include <asm/page.h>
  79 #include <asm/ptrace.h>
  80 #include <asm/system.h>
  81 #include <asm/sal.h>
  82 #include <asm/mca.h>
  83
  84 #include <asm/irq.h>
  85 #include <asm/hw_irq.h>
  86
  87 #include "mca_drv.h"
  88 #include "entry.h"
  89
  90 #if defined(IA64_MCA_DEBUG_INFO)
  91 # define IA64_MCA_DEBUG(fmt...) printk(fmt)
  92 #else
  93 # define IA64_MCA_DEBUG(fmt...)
  94 #endif
  95
  96 /* Used by mca_asm.S */
  97 u32                             ia64_mca_serialize;
  98 DEFINE_PER_CPU(u64, ia64_mca_data); /* == __per_cpu_mca[smp_processor_id()] */
  99 DEFINE_PER_CPU(u64, ia64_mca_per_cpu_pte); /* PTE to map per-CPU area */
 100 DEFINE_PER_CPU(u64, ia64_mca_pal_pte);      /* PTE to map PAL code */
 101 DEFINE_PER_CPU(u64, ia64_mca_pal_base);    /* vaddr PAL code granule */
 102
 103 unsigned long __per_cpu_mca[NR_CPUS];
 104
 105 /* In mca_asm.S */
 106 extern void                     ia64_os_init_dispatch_monarch (void);
 107 extern void                     ia64_os_init_dispatch_slave (void);
 108
 109 static int monarch_cpu = -1;
 110
 111 static ia64_mc_info_t           ia64_mc_info;
 112
 113 #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */
 114 #define MIN_CPE_POLL_INTERVAL (2*60*HZ)  /* 2 minutes */
 115 #define CMC_POLL_INTERVAL     (1*60*HZ)  /* 1 minute */
 116 #define CPE_HISTORY_LENGTH    5
 117 #define CMC_HISTORY_LENGTH    5
 118
 119 static struct timer_list cpe_poll_timer;
 120 static struct timer_list cmc_poll_timer;
 121 /*
 122  * This variable tells whether we are currently in polling mode.
 123  * Start with this in the wrong state so we won't play w/ timers
 124  * before the system is ready.
 125  */
 126 static int cmc_polling_enabled = 1;
 127
 128 /*
 129  * Clearing this variable prevents CPE polling from getting activated
 130  * in mca_late_init.  Use it if your system doesn't provide a CPEI,
 131  * but encounters problems retrieving CPE logs.  This should only be
 132  * necessary for debugging.
 133  */
 134 static int cpe_poll_enabled = 1;
 135
 136 extern void salinfo_log_wakeup(int type, u8 *buffer, u64 size, int irqsafe);
 137
 138 static int mca_init __initdata;
 139
 140
 141 static void inline
 142 ia64_mca_spin(const char *func)
 143 {
 144         printk(KERN_EMERG "%s: spinning here, not returning to SAL\n", func);
 145         while (1)
 146                 cpu_relax();
 147 }
 148 /*
 149  * IA64_MCA log support
 150  */
 151 #define IA64_MAX_LOGS           2       /* Double-buffering for nested MCAs */
 152 #define IA64_MAX_LOG_TYPES      4   /* MCA, INIT, CMC, CPE */
 153
 154 typedef struct ia64_state_log_s
 155 {
 156         spinlock_t      isl_lock;
 157         int             isl_index;
 158         unsigned long   isl_count;
 159         ia64_err_rec_t  *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
 160 } ia64_state_log_t;
 161
 162 static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES];
 163
 164 #define IA64_LOG_ALLOCATE(it, size) \
 165         {ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
 166                 (ia64_err_rec_t *)alloc_bootmem(size); \
 167         ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
 168                 (ia64_err_rec_t *)alloc_bootmem(size);}
 169 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
 170 #define IA64_LOG_LOCK(it)      spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
 171 #define IA64_LOG_UNLOCK(it)    spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
 172 #define IA64_LOG_NEXT_INDEX(it)    ia64_state_log[it].isl_index
 173 #define IA64_LOG_CURR_INDEX(it)    1 - ia64_state_log[it].isl_index
 174 #define IA64_LOG_INDEX_INC(it) \
 175     {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \
 176     ia64_state_log[it].isl_count++;}
 177 #define IA64_LOG_INDEX_DEC(it) \
 178     ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
 179 #define IA64_LOG_NEXT_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
 180 #define IA64_LOG_CURR_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
 181 #define IA64_LOG_COUNT(it)         ia64_state_log[it].isl_count
 182
 183 /*
 184  * ia64_log_init
 185  *      Reset the OS ia64 log buffer
 186  * Inputs   :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
 187  * Outputs      :       None
 188  */
 189 static void __init
 190 ia64_log_init(int sal_info_type)
 191 {
 192         u64     max_size = 0;
 193
 194         IA64_LOG_NEXT_INDEX(sal_info_type) = 0;
 195         IA64_LOG_LOCK_INIT(sal_info_type);
 196
 197         // SAL will tell us the maximum size of any error record of this type
 198         max_size = ia64_sal_get_state_info_size(sal_info_type);
 199         if (!max_size)
 200                 /* alloc_bootmem() doesn't like zero-sized allocations! */
 201                 return;
 202
 203         // set up OS data structures to hold error info
 204         IA64_LOG_ALLOCATE(sal_info_type, max_size);
 205         memset(IA64_LOG_CURR_BUFFER(sal_info_type), 0, max_size);
 206         memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, max_size);
 207 }
 208
 209 /*
 210  * ia64_log_get
 211  *
 212  *      Get the current MCA log from SAL and copy it into the OS log buffer.
 213  *
 214  *  Inputs  :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
 215  *              irq_safe    whether you can use printk at this point
 216  *  Outputs :   size        (total record length)
 217  *              *buffer     (ptr to error record)
 218  *
 219  */
 220 static u64
 221 ia64_log_get(int sal_info_type, u8 **buffer, int irq_safe)
 222 {
 223         sal_log_record_header_t     *log_buffer;
 224         u64                         total_len = 0;
 225         int                         s;
 226
 227         IA64_LOG_LOCK(sal_info_type);
 228
 229         /* Get the process state information */
 230         log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type);
 231
 232         total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer);
 233
 234         if (total_len) {
 235                 IA64_LOG_INDEX_INC(sal_info_type);
 236                 IA64_LOG_UNLOCK(sal_info_type);
 237                 if (irq_safe) {
 238                         IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. "
 239                                        "Record length = %ld\n", __FUNCTION__, sal_info_type, total_len);
 240                 }
 241                 *buffer = (u8 *) log_buffer;
 242                 return total_len;
 243         } else {
 244                 IA64_LOG_UNLOCK(sal_info_type);
 245                 return 0;
 246         }
 247 }
 248
 249 /*
 250  *  ia64_mca_log_sal_error_record
 251  *
 252  *  This function retrieves a specified error record type from SAL
 253  *  and wakes up any processes waiting for error records.
 254  *
 255  *  Inputs  :   sal_info_type   (Type of error record MCA/CMC/CPE)
 256  *              FIXME: remove MCA and irq_safe.
 257  */
 258 static void
 259 ia64_mca_log_sal_error_record(int sal_info_type)
 260 {
 261         u8 *buffer;
 262         sal_log_record_header_t *rh;
 263         u64 size;
 264         int irq_safe = sal_info_type != SAL_INFO_TYPE_MCA;
 265 #ifdef IA64_MCA_DEBUG_INFO
 266         static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" };
 267 #endif
 268
 269         size = ia64_log_get(sal_info_type, &buffer, irq_safe);
 270         if (!size)
 271                 return;
 272
 273         salinfo_log_wakeup(sal_info_type, buffer, size, irq_safe);
 274
 275         if (irq_safe)
 276                 IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n",
 277                         smp_processor_id(),
 278                         sal_info_type < ARRAY_SIZE(rec_name) ? rec_name[sal_info_type] : "UNKNOWN");
 279
 280         /* Clear logs from corrected errors in case there's no user-level logger */
 281         rh = (sal_log_record_header_t *)buffer;
 282         if (rh->severity == sal_log_severity_corrected)
 283                 ia64_sal_clear_state_info(sal_info_type);
 284 }
 285
 286 /*
 287  * search_mca_table
 288  *  See if the MCA surfaced in an instruction range
 289  *  that has been tagged as recoverable.
 290  *
 291  *  Inputs
 292  *      first   First address range to check
 293  *      last    Last address range to check
 294  *      ip      Instruction pointer, address we are looking for
 295  *
 296  * Return value:
 297  *      1 on Success (in the table)/ 0 on Failure (not in the  table)
 298  */
 299 int
 300 search_mca_table (const struct mca_table_entry *first,
 301                 const struct mca_table_entry *last,
 302                 unsigned long ip)
 303 {
 304         const struct mca_table_entry *curr;
 305         u64 curr_start, curr_end;
 306
 307         curr = first;
 308         while (curr <= last) {
 309                 curr_start = (u64) &curr->start_addr + curr->start_addr;
 310                 curr_end = (u64) &curr->end_addr + curr->end_addr;
 311
 312                 if ((ip >= curr_start) && (ip <= curr_end)) {
 313                         return 1;
 314                 }
 315                 curr++;
 316         }
 317         return 0;
 318 }
 319
 320 /* Given an address, look for it in the mca tables. */
 321 int mca_recover_range(unsigned long addr)
 322 {
 323         extern struct mca_table_entry __start___mca_table[];
 324         extern struct mca_table_entry __stop___mca_table[];
 325
 326         return search_mca_table(__start___mca_table, __stop___mca_table-1, addr);
 327 }
 328 EXPORT_SYMBOL_GPL(mca_recover_range);
 329
 330 #ifdef CONFIG_ACPI
 331
 332 int cpe_vector = -1;
 333 int ia64_cpe_irq = -1;
 334
 335 static irqreturn_t
 336 ia64_mca_cpe_int_handler (int cpe_irq, void *arg, struct pt_regs *ptregs)
 337 {
 338         static unsigned long    cpe_history[CPE_HISTORY_LENGTH];
 339         static int              index;
 340         static DEFINE_SPINLOCK(cpe_history_lock);
 341
 342         IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
 343                        __FUNCTION__, cpe_irq, smp_processor_id());
 344
 345         /* SAL spec states this should run w/ interrupts enabled */
 346         local_irq_enable();
 347
 348         /* Get the CPE error record and log it */
 349         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE);
 350
 351         spin_lock(&cpe_history_lock);
 352         if (!cpe_poll_enabled && cpe_vector >= 0) {
 353
 354                 int i, count = 1; /* we know 1 happened now */
 355                 unsigned long now = jiffies;
 356
 357                 for (i = 0; i < CPE_HISTORY_LENGTH; i++) {
 358                         if (now - cpe_history[i] <= HZ)
 359                                 count++;
 360                 }
 361
 362                 IA64_MCA_DEBUG(KERN_INFO "CPE threshold %d/%d\n", count, CPE_HISTORY_LENGTH);
 363                 if (count >= CPE_HISTORY_LENGTH) {
 364
 365                         cpe_poll_enabled = 1;
 366                         spin_unlock(&cpe_history_lock);
 367                         disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR));
 368
 369                         /*
 370                          * Corrected errors will still be corrected, but
 371                          * make sure there's a log somewhere that indicates
 372                          * something is generating more than we can handle.
 373                          */
 374                         printk(KERN_WARNING "WARNING: Switching to polling CPE handler; error records may be lost\n");
 375
 376                         mod_timer(&cpe_poll_timer, jiffies + MIN_CPE_POLL_INTERVAL);
 377
 378                         /* lock already released, get out now */
 379                         return IRQ_HANDLED;
 380                 } else {
 381                         cpe_history[index++] = now;
 382                         if (index == CPE_HISTORY_LENGTH)
 383                                 index = 0;
 384                 }
 385         }
 386         spin_unlock(&cpe_history_lock);
 387         return IRQ_HANDLED;
 388 }
 389
 390 #endif /* CONFIG_ACPI */
 391
 392 #ifdef CONFIG_ACPI
 393 /*
 394  * ia64_mca_register_cpev
 395  *
 396  *  Register the corrected platform error vector with SAL.
 397  *
 398  *  Inputs
 399  *      cpev        Corrected Platform Error Vector number
 400  *
 401  *  Outputs
 402  *      None
 403  */
 404 static void __init
 405 ia64_mca_register_cpev (int cpev)
 406 {
 407         /* Register the CPE interrupt vector with SAL */
 408         struct ia64_sal_retval isrv;
 409
 410         isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0);
 411         if (isrv.status) {
 412                 printk(KERN_ERR "Failed to register Corrected Platform "
 413                        "Error interrupt vector with SAL (status %ld)\n", isrv.status);
 414                 return;
 415         }
 416
 417         IA64_MCA_DEBUG("%s: corrected platform error "
 418                        "vector %#x registered\n", __FUNCTION__, cpev);
 419 }
 420 #endif /* CONFIG_ACPI */
 421
 422 /*
 423  * ia64_mca_cmc_vector_setup
 424  *
 425  *  Setup the corrected machine check vector register in the processor.
 426  *  (The interrupt is masked on boot. ia64_mca_late_init unmask this.)
 427  *  This function is invoked on a per-processor basis.
 428  *
 429  * Inputs
 430  *      None
 431  *
 432  * Outputs
 433  *      None
 434  */
 435 void __cpuinit
 436 ia64_mca_cmc_vector_setup (void)
 437 {
 438         cmcv_reg_t      cmcv;
 439
 440         cmcv.cmcv_regval        = 0;
 441         cmcv.cmcv_mask          = 1;        /* Mask/disable interrupt at first */
 442         cmcv.cmcv_vector        = IA64_CMC_VECTOR;
 443         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
 444
 445         IA64_MCA_DEBUG("%s: CPU %d corrected "
 446                        "machine check vector %#x registered.\n",
 447                        __FUNCTION__, smp_processor_id(), IA64_CMC_VECTOR);
 448
 449         IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n",
 450                        __FUNCTION__, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV));
 451 }
 452
 453 /*
 454  * ia64_mca_cmc_vector_disable
 455  *
 456  *  Mask the corrected machine check vector register in the processor.
 457  *  This function is invoked on a per-processor basis.
 458  *
 459  * Inputs
 460  *      dummy(unused)
 461  *
 462  * Outputs
 463  *      None
 464  */
 465 static void
 466 ia64_mca_cmc_vector_disable (void *dummy)
 467 {
 468         cmcv_reg_t      cmcv;
 469
 470         cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
 471
 472         cmcv.cmcv_mask = 1; /* Mask/disable interrupt */
 473         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
 474
 475         IA64_MCA_DEBUG("%s: CPU %d corrected "
 476                        "machine check vector %#x disabled.\n",
 477                        __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
 478 }
 479
 480 /*
 481  * ia64_mca_cmc_vector_enable
 482  *
 483  *  Unmask the corrected machine check vector register in the processor.
 484  *  This function is invoked on a per-processor basis.
 485  *
 486  * Inputs
 487  *      dummy(unused)
 488  *
 489  * Outputs
 490  *      None
 491  */
 492 static void
 493 ia64_mca_cmc_vector_enable (void *dummy)
 494 {
 495         cmcv_reg_t      cmcv;
 496
 497         cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
 498
 499         cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */
 500         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
 501
 502         IA64_MCA_DEBUG("%s: CPU %d corrected "
 503                        "machine check vector %#x enabled.\n",
 504                        __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
 505 }
 506
 507 /*
 508  * ia64_mca_cmc_vector_disable_keventd
 509  *
 510  * Called via keventd (smp_call_function() is not safe in interrupt context) to
 511  * disable the cmc interrupt vector.
 512  */
 513 static void
 514 ia64_mca_cmc_vector_disable_keventd(void *unused)
 515 {
 516         on_each_cpu(ia64_mca_cmc_vector_disable, NULL, 1, 0);
 517 }
 518
 519 /*
 520  * ia64_mca_cmc_vector_enable_keventd
 521  *
 522  * Called via keventd (smp_call_function() is not safe in interrupt context) to
 523  * enable the cmc interrupt vector.
 524  */
 525 static void
 526 ia64_mca_cmc_vector_enable_keventd(void *unused)
 527 {
 528         on_each_cpu(ia64_mca_cmc_vector_enable, NULL, 1, 0);
 529 }
 530
 531 /*
 532  * ia64_mca_wakeup
 533  *
 534  *      Send an inter-cpu interrupt to wake-up a particular cpu
 535  *      and mark that cpu to be out of rendez.
 536  *
 537  *  Inputs  :   cpuid
 538  *  Outputs :   None
 539  */
 540 static void
 541 ia64_mca_wakeup(int cpu)
 542 {
 543         platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0);
 544         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
 545
 546 }
 547
 548 /*
 549  * ia64_mca_wakeup_all
 550  *
 551  *      Wakeup all the cpus which have rendez'ed previously.
 552  *
 553  *  Inputs  :   None
 554  *  Outputs :   None
 555  */
 556 static void
 557 ia64_mca_wakeup_all(void)
 558 {
 559         int cpu;
 560
 561         /* Clear the Rendez checkin flag for all cpus */
 562         for_each_online_cpu(cpu) {
 563                 if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE)
 564                         ia64_mca_wakeup(cpu);
 565         }
 566
 567 }
 568
 569 /*
 570  * ia64_mca_rendez_interrupt_handler
 571  *
 572  *      This is handler used to put slave processors into spinloop
 573  *      while the monarch processor does the mca handling and later
 574  *      wake each slave up once the monarch is done.
 575  *
 576  *  Inputs  :   None
 577  *  Outputs :   None
 578  */
 579 static irqreturn_t
 580 ia64_mca_rendez_int_handler(int rendez_irq, void *arg, struct pt_regs *regs)
 581 {
 582         unsigned long flags;
 583         int cpu = smp_processor_id();
 584
 585         /* Mask all interrupts */
 586         local_irq_save(flags);
 587         if (notify_die(DIE_MCA_RENDZVOUS_ENTER, "MCA", regs, 0, 0, 0)
 588                         == NOTIFY_STOP)
 589                 ia64_mca_spin(__FUNCTION__);
 590
 591         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE;
 592         /* Register with the SAL monarch that the slave has
 593          * reached SAL
 594          */
 595         ia64_sal_mc_rendez();
 596
 597         if (notify_die(DIE_MCA_RENDZVOUS_PROCESS, "MCA", regs, 0, 0, 0)
 598                         == NOTIFY_STOP)
 599                 ia64_mca_spin(__FUNCTION__);
 600
 601         /* Wait for the monarch cpu to exit. */
 602         while (monarch_cpu != -1)
 603                cpu_relax();     /* spin until monarch leaves */
 604
 605         if (notify_die(DIE_MCA_RENDZVOUS_LEAVE, "MCA", regs, 0, 0, 0)
 606                         == NOTIFY_STOP)
 607                 ia64_mca_spin(__FUNCTION__);
 608
 609         /* Enable all interrupts */
 610         local_irq_restore(flags);
 611         return IRQ_HANDLED;
 612 }
 613
 614 /*
 615  * ia64_mca_wakeup_int_handler
 616  *
 617  *      The interrupt handler for processing the inter-cpu interrupt to the
 618  *      slave cpu which was spinning in the rendez loop.
 619  *      Since this spinning is done by turning off the interrupts and
 620  *      polling on the wakeup-interrupt bit in the IRR, there is
 621  *      nothing useful to be done in the handler.
 622  *
 623  *  Inputs  :   wakeup_irq  (Wakeup-interrupt bit)
 624  *      arg             (Interrupt handler specific argument)
 625  *      ptregs          (Exception frame at the time of the interrupt)
 626  *  Outputs :   None
 627  *
 628  */
 629 static irqreturn_t
 630 ia64_mca_wakeup_int_handler(int wakeup_irq, void *arg, struct pt_regs *ptregs)
 631 {
 632         return IRQ_HANDLED;
 633 }
 634
 635 /* Function pointer for extra MCA recovery */
 636 int (*ia64_mca_ucmc_extension)
 637         (void*,struct ia64_sal_os_state*)
 638         = NULL;
 639
 640 int
 641 ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *))
 642 {
 643         if (ia64_mca_ucmc_extension)
 644                 return 1;
 645
 646         ia64_mca_ucmc_extension = fn;
 647         return 0;
 648 }
 649
 650 void
 651 ia64_unreg_MCA_extension(void)
 652 {
 653         if (ia64_mca_ucmc_extension)
 654                 ia64_mca_ucmc_extension = NULL;
 655 }
 656
 657 EXPORT_SYMBOL(ia64_reg_MCA_extension);
 658 EXPORT_SYMBOL(ia64_unreg_MCA_extension);
 659
 660
 661 static inline void
 662 copy_reg(const u64 *fr, u64 fnat, u64 *tr, u64 *tnat)
 663 {
 664         u64 fslot, tslot, nat;
 665         *tr = *fr;
 666         fslot = ((unsigned long)fr >> 3) & 63;
 667         tslot = ((unsigned long)tr >> 3) & 63;
 668         *tnat &= ~(1UL << tslot);
 669         nat = (fnat >> fslot) & 1;
 670         *tnat |= (nat << tslot);
 671 }
 672
 673 /* Change the comm field on the MCA/INT task to include the pid that
 674  * was interrupted, it makes for easier debugging.  If that pid was 0
 675  * (swapper or nested MCA/INIT) then use the start of the previous comm
 676  * field suffixed with its cpu.
 677  */
 678
 679 static void
 680 ia64_mca_modify_comm(const task_t *previous_current)
 681 {
 682         char *p, comm[sizeof(current->comm)];
 683         if (previous_current->pid)
 684                 snprintf(comm, sizeof(comm), "%s %d",
 685                         current->comm, previous_current->pid);
 686         else {
 687                 int l;
 688                 if ((p = strchr(previous_current->comm, ' ')))
 689                         l = p - previous_current->comm;
 690                 else
 691                         l = strlen(previous_current->comm);
 692                 snprintf(comm, sizeof(comm), "%s %*s %d",
 693                         current->comm, l, previous_current->comm,
 694                         task_thread_info(previous_current)->cpu);
 695         }
 696         memcpy(current->comm, comm, sizeof(current->comm));
 697 }
 698
 699 /* On entry to this routine, we are running on the per cpu stack, see
 700  * mca_asm.h.  The original stack has not been touched by this event.  Some of
 701  * the original stack's registers will be in the RBS on this stack.  This stack
 702  * also contains a partial pt_regs and switch_stack, the rest of the data is in
 703  * PAL minstate.
 704  *
 705  * The first thing to do is modify the original stack to look like a blocked
 706  * task so we can run backtrace on the original task.  Also mark the per cpu
 707  * stack as current to ensure that we use the correct task state, it also means
 708  * that we can do backtrace on the MCA/INIT handler code itself.
 709  */
 710
 711 static task_t *
 712 ia64_mca_modify_original_stack(struct pt_regs *regs,
 713                 const struct switch_stack *sw,
 714                 struct ia64_sal_os_state *sos,
 715                 const char *type)
 716 {
 717         char *p;
 718         ia64_va va;
 719         extern char ia64_leave_kernel[];        /* Need asm address, not function descriptor */
 720         const pal_min_state_area_t *ms = sos->pal_min_state;
 721         task_t *previous_current;
 722         struct pt_regs *old_regs;
 723         struct switch_stack *old_sw;
 724         unsigned size = sizeof(struct pt_regs) +
 725                         sizeof(struct switch_stack) + 16;
 726         u64 *old_bspstore, *old_bsp;
 727         u64 *new_bspstore, *new_bsp;
 728         u64 old_unat, old_rnat, new_rnat, nat;
 729         u64 slots, loadrs = regs->loadrs;
 730         u64 r12 = ms->pmsa_gr[12-1], r13 = ms->pmsa_gr[13-1];
 731         u64 ar_bspstore = regs->ar_bspstore;
 732         u64 ar_bsp = regs->ar_bspstore + (loadrs >> 16);
 733         const u64 *bank;
 734         const char *msg;
 735         int cpu = smp_processor_id();
 736
 737         previous_current = curr_task(cpu);
 738         set_curr_task(cpu, current);
 739         if ((p = strchr(current->comm, ' ')))
 740                 *p = '\0';
 741
 742         /* Best effort attempt to cope with MCA/INIT delivered while in
 743          * physical mode.
 744          */
 745         regs->cr_ipsr = ms->pmsa_ipsr;
 746         if (ia64_psr(regs)->dt == 0) {
 747                 va.l = r12;
 748                 if (va.f.reg == 0) {
 749                         va.f.reg = 7;
 750                         r12 = va.l;
 751                 }
 752                 va.l = r13;
 753                 if (va.f.reg == 0) {
 754                         va.f.reg = 7;
 755                         r13 = va.l;
 756                 }
 757         }
 758         if (ia64_psr(regs)->rt == 0) {
 759                 va.l = ar_bspstore;
 760                 if (va.f.reg == 0) {
 761                         va.f.reg = 7;
 762                         ar_bspstore = va.l;
 763                 }
 764                 va.l = ar_bsp;
 765                 if (va.f.reg == 0) {
 766                         va.f.reg = 7;
 767                         ar_bsp = va.l;
 768                 }
 769         }
 770
 771         /* mca_asm.S ia64_old_stack() cannot assume that the dirty registers
 772          * have been copied to the old stack, the old stack may fail the
 773          * validation tests below.  So ia64_old_stack() must restore the dirty
 774          * registers from the new stack.  The old and new bspstore probably
 775          * have different alignments, so loadrs calculated on the old bsp
 776          * cannot be used to restore from the new bsp.  Calculate a suitable
 777          * loadrs for the new stack and save it in the new pt_regs, where
 778          * ia64_old_stack() can get it.
 779          */
 780         old_bspstore = (u64 *)ar_bspstore;
 781         old_bsp = (u64 *)ar_bsp;
 782         slots = ia64_rse_num_regs(old_bspstore, old_bsp);
 783         new_bspstore = (u64 *)((u64)current + IA64_RBS_OFFSET);
 784         new_bsp = ia64_rse_skip_regs(new_bspstore, slots);
 785         regs->loadrs = (new_bsp - new_bspstore) * 8 << 16;
 786
 787         /* Verify the previous stack state before we change it */
 788         if (user_mode(regs)) {
 789                 msg = "occurred in user space";
 790                 /* previous_current is guaranteed to be valid when the task was
 791                  * in user space, so ...
 792                  */
 793                 ia64_mca_modify_comm(previous_current);
 794                 goto no_mod;
 795         }
 796
 797         if (!mca_recover_range(ms->pmsa_iip)) {
 798                 if (r13 != sos->prev_IA64_KR_CURRENT) {
 799                         msg = "inconsistent previous current and r13";
 800                         goto no_mod;
 801                 }
 802                 if ((r12 - r13) >= KERNEL_STACK_SIZE) {
 803                         msg = "inconsistent r12 and r13";
 804                         goto no_mod;
 805                 }
 806                 if ((ar_bspstore - r13) >= KERNEL_STACK_SIZE) {
 807                         msg = "inconsistent ar.bspstore and r13";
 808                         goto no_mod;
 809                 }
 810                 va.p = old_bspstore;
 811                 if (va.f.reg < 5) {
 812                         msg = "old_bspstore is in the wrong region";
 813                         goto no_mod;
 814                 }
 815                 if ((ar_bsp - r13) >= KERNEL_STACK_SIZE) {
 816                         msg = "inconsistent ar.bsp and r13";
 817                         goto no_mod;
 818                 }
 819                 size += (ia64_rse_skip_regs(old_bspstore, slots) - old_bspstore) * 8;
 820                 if (ar_bspstore + size > r12) {
 821                         msg = "no room for blocked state";
 822                         goto no_mod;
 823                 }
 824         }
 825
 826         ia64_mca_modify_comm(previous_current);
 827
 828         /* Make the original task look blocked.  First stack a struct pt_regs,
 829          * describing the state at the time of interrupt.  mca_asm.S built a
 830          * partial pt_regs, copy it and fill in the blanks using minstate.
 831          */
 832         p = (char *)r12 - sizeof(*regs);
 833         old_regs = (struct pt_regs *)p;
 834         memcpy(old_regs, regs, sizeof(*regs));
 835         /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use
 836          * pmsa_{xip,xpsr,xfs}
 837          */
 838         if (ia64_psr(regs)->ic) {
 839                 old_regs->cr_iip = ms->pmsa_iip;
 840                 old_regs->cr_ipsr = ms->pmsa_ipsr;
 841                 old_regs->cr_ifs = ms->pmsa_ifs;
 842         } else {
 843                 old_regs->cr_iip = ms->pmsa_xip;
 844                 old_regs->cr_ipsr = ms->pmsa_xpsr;
 845                 old_regs->cr_ifs = ms->pmsa_xfs;
 846         }
 847         old_regs->pr = ms->pmsa_pr;
 848         old_regs->b0 = ms->pmsa_br0;
 849         old_regs->loadrs = loadrs;
 850         old_regs->ar_rsc = ms->pmsa_rsc;
 851         old_unat = old_regs->ar_unat;
 852         copy_reg(&ms->pmsa_gr[1-1], ms->pmsa_nat_bits, &old_regs->r1, &old_unat);
 853         copy_reg(&ms->pmsa_gr[2-1], ms->pmsa_nat_bits, &old_regs->r2, &old_unat);
 854         copy_reg(&ms->pmsa_gr[3-1], ms->pmsa_nat_bits, &old_regs->r3, &old_unat);
 855         copy_reg(&ms->pmsa_gr[8-1], ms->pmsa_nat_bits, &old_regs->r8, &old_unat);
 856         copy_reg(&ms->pmsa_gr[9-1], ms->pmsa_nat_bits, &old_regs->r9, &old_unat);
 857         copy_reg(&ms->pmsa_gr[10-1], ms->pmsa_nat_bits, &old_regs->r10, &old_unat);
 858         copy_reg(&ms->pmsa_gr[11-1], ms->pmsa_nat_bits, &old_regs->r11, &old_unat);
 859         copy_reg(&ms->pmsa_gr[12-1], ms->pmsa_nat_bits, &old_regs->r12, &old_unat);
 860         copy_reg(&ms->pmsa_gr[13-1], ms->pmsa_nat_bits, &old_regs->r13, &old_unat);
 861         copy_reg(&ms->pmsa_gr[14-1], ms->pmsa_nat_bits, &old_regs->r14, &old_unat);
 862         copy_reg(&ms->pmsa_gr[15-1], ms->pmsa_nat_bits, &old_regs->r15, &old_unat);
 863         if (ia64_psr(old_regs)->bn)
 864                 bank = ms->pmsa_bank1_gr;
 865         else
 866                 bank = ms->pmsa_bank0_gr;
 867         copy_reg(&bank[16-16], ms->pmsa_nat_bits, &old_regs->r16, &old_unat);
 868         copy_reg(&bank[17-16], ms->pmsa_nat_bits, &old_regs->r17, &old_unat);
 869         copy_reg(&bank[18-16], ms->pmsa_nat_bits, &old_regs->r18, &old_unat);
 870         copy_reg(&bank[19-16], ms->pmsa_nat_bits, &old_regs->r19, &old_unat);
 871         copy_reg(&bank[20-16], ms->pmsa_nat_bits, &old_regs->r20, &old_unat);
 872         copy_reg(&bank[21-16], ms->pmsa_nat_bits, &old_regs->r21, &old_unat);
 873         copy_reg(&bank[22-16], ms->pmsa_nat_bits, &old_regs->r22, &old_unat);
 874         copy_reg(&bank[23-16], ms->pmsa_nat_bits, &old_regs->r23, &old_unat);
 875         copy_reg(&bank[24-16], ms->pmsa_nat_bits, &old_regs->r24, &old_unat);
 876         copy_reg(&bank[25-16], ms->pmsa_nat_bits, &old_regs->r25, &old_unat);
 877         copy_reg(&bank[26-16], ms->pmsa_nat_bits, &old_regs->r26, &old_unat);
 878         copy_reg(&bank[27-16], ms->pmsa_nat_bits, &old_regs->r27, &old_unat);
 879         copy_reg(&bank[28-16], ms->pmsa_nat_bits, &old_regs->r28, &old_unat);
 880         copy_reg(&bank[29-16], ms->pmsa_nat_bits, &old_regs->r29, &old_unat);
 881         copy_reg(&bank[30-16], ms->pmsa_nat_bits, &old_regs->r30, &old_unat);
 882         copy_reg(&bank[31-16], ms->pmsa_nat_bits, &old_regs->r31, &old_unat);
 883
 884         /* Next stack a struct switch_stack.  mca_asm.S built a partial
 885          * switch_stack, copy it and fill in the blanks using pt_regs and
 886          * minstate.
 887          *
 888          * In the synthesized switch_stack, b0 points to ia64_leave_kernel,
 889          * ar.pfs is set to 0.
 890          *
 891          * unwind.c::unw_unwind() does special processing for interrupt frames.
 892          * It checks if the PRED_NON_SYSCALL predicate is set, if the predicate
 893          * is clear then unw_unwind() does _not_ adjust bsp over pt_regs.  Not
 894          * that this is documented, of course.  Set PRED_NON_SYSCALL in the
 895          * switch_stack on the original stack so it will unwind correctly when
 896          * unwind.c reads pt_regs.
 897          *
 898          * thread.ksp is updated to point to the synthesized switch_stack.
 899          */
 900         p -= sizeof(struct switch_stack);
 901         old_sw = (struct switch_stack *)p;
 902         memcpy(old_sw, sw, sizeof(*sw));
 903         old_sw->caller_unat = old_unat;
 904         old_sw->ar_fpsr = old_regs->ar_fpsr;
 905         copy_reg(&ms->pmsa_gr[4-1], ms->pmsa_nat_bits, &old_sw->r4, &old_unat);
 906         copy_reg(&ms->pmsa_gr[5-1], ms->pmsa_nat_bits, &old_sw->r5, &old_unat);
 907         copy_reg(&ms->pmsa_gr[6-1], ms->pmsa_nat_bits, &old_sw->r6, &old_unat);
 908         copy_reg(&ms->pmsa_gr[7-1], ms->pmsa_nat_bits, &old_sw->r7, &old_unat);
 909         old_sw->b0 = (u64)ia64_leave_kernel;
 910         old_sw->b1 = ms->pmsa_br1;
 911         old_sw->ar_pfs = 0;
 912         old_sw->ar_unat = old_unat;
 913         old_sw->pr = old_regs->pr | (1UL << PRED_NON_SYSCALL);
 914         previous_current->thread.ksp = (u64)p - 16;
 915
 916         /* Finally copy the original stack's registers back to its RBS.
 917          * Registers from ar.bspstore through ar.bsp at the time of the event
 918          * are in the current RBS, copy them back to the original stack.  The
 919          * copy must be done register by register because the original bspstore
 920          * and the current one have different alignments, so the saved RNAT
 921          * data occurs at different places.
 922          *
 923          * mca_asm does cover, so the old_bsp already includes all registers at
 924          * the time of MCA/INIT.  It also does flushrs, so all registers before
 925          * this function have been written to backing store on the MCA/INIT
 926          * stack.
 927          */
 928         new_rnat = ia64_get_rnat(ia64_rse_rnat_addr(new_bspstore));
 929         old_rnat = regs->ar_rnat;
 930         while (slots--) {
 931                 if (ia64_rse_is_rnat_slot(new_bspstore)) {
 932                         new_rnat = ia64_get_rnat(new_bspstore++);
 933                 }
 934                 if (ia64_rse_is_rnat_slot(old_bspstore)) {
 935                         *old_bspstore++ = old_rnat;
 936                         old_rnat = 0;
 937                 }
 938                 nat = (new_rnat >> ia64_rse_slot_num(new_bspstore)) & 1UL;
 939                 old_rnat &= ~(1UL << ia64_rse_slot_num(old_bspstore));
 940                 old_rnat |= (nat << ia64_rse_slot_num(old_bspstore));
 941                 *old_bspstore++ = *new_bspstore++;
 942         }
 943         old_sw->ar_bspstore = (unsigned long)old_bspstore;
 944         old_sw->ar_rnat = old_rnat;
 945
 946         sos->prev_task = previous_current;
 947         return previous_current;
 948
 949 no_mod:
 950         printk(KERN_INFO "cpu %d, %s %s, original stack not modified\n",
 951                         smp_processor_id(), type, msg);
 952         return previous_current;
 953 }
 954
 955 /* The monarch/slave interaction is based on monarch_cpu and requires that all
 956  * slaves have entered rendezvous before the monarch leaves.  If any cpu has
 957  * not entered rendezvous yet then wait a bit.  The assumption is that any
 958  * slave that has not rendezvoused after a reasonable time is never going to do
 959  * so.  In this context, slave includes cpus that respond to the MCA rendezvous
 960  * interrupt, as well as cpus that receive the INIT slave event.
 961  */
 962
 963 static void
 964 ia64_wait_for_slaves(int monarch)
 965 {
 966         int c, wait = 0, missing = 0;
 967         for_each_online_cpu(c) {
 968                 if (c == monarch)
 969                         continue;
 970                 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) {
 971                         udelay(1000);           /* short wait first */
 972                         wait = 1;
 973                         break;
 974                 }
 975         }
 976         if (!wait)
 977                 goto all_in;
 978         for_each_online_cpu(c) {
 979                 if (c == monarch)
 980                         continue;
 981                 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) {
 982                         udelay(5*1000000);      /* wait 5 seconds for slaves (arbitrary) */
 983                         if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE)
 984                                 missing = 1;
 985                         break;
 986                 }
 987         }
 988         if (!missing)
 989                 goto all_in;
 990         printk(KERN_INFO "OS MCA slave did not rendezvous on cpu");
 991         for_each_online_cpu(c) {
 992                 if (c == monarch)
 993                         continue;
 994                 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE)
 995                         printk(" %d", c);
 996         }
 997         printk("\n");
 998         return;
 999
1000 all_in:
1001         printk(KERN_INFO "All OS MCA slaves have reached rendezvous\n");
1002         return;
1003 }
1004
1005 /*
1006  * ia64_mca_handler
1007  *
1008  *      This is uncorrectable machine check handler called from OS_MCA
1009  *      dispatch code which is in turn called from SAL_CHECK().
1010  *      This is the place where the core of OS MCA handling is done.
1011  *      Right now the logs are extracted and displayed in a well-defined
1012  *      format. This handler code is supposed to be run only on the
1013  *      monarch processor. Once the monarch is done with MCA handling
1014  *      further MCA logging is enabled by clearing logs.
1015  *      Monarch also has the duty of sending wakeup-IPIs to pull the
1016  *      slave processors out of rendezvous spinloop.
1017  */
1018 void
1019 ia64_mca_handler(struct pt_regs *regs, struct switch_stack *sw,
1020                  struct ia64_sal_os_state *sos)
1021 {
1022         pal_processor_state_info_t *psp = (pal_processor_state_info_t *)
1023                 &sos->proc_state_param;
1024         int recover, cpu = smp_processor_id();
1025         task_t *previous_current;
1026
1027         oops_in_progress = 1;   /* FIXME: make printk NMI/MCA/INIT safe */
1028         console_loglevel = 15;  /* make sure printks make it to console */
1029         printk(KERN_INFO "Entered OS MCA handler. PSP=%lx cpu=%d monarch=%ld\n",
1030                 sos->proc_state_param, cpu, sos->monarch);
1031
1032         previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "MCA");
1033         monarch_cpu = cpu;
1034         if (notify_die(DIE_MCA_MONARCH_ENTER, "MCA", regs, 0, 0, 0)
1035                         == NOTIFY_STOP)
1036                 ia64_mca_spin(__FUNCTION__);
1037         ia64_wait_for_slaves(cpu);
1038
1039         /* Wakeup all the processors which are spinning in the rendezvous loop.
1040          * They will leave SAL, then spin in the OS with interrupts disabled
1041          * until this monarch cpu leaves the MCA handler.  That gets control
1042          * back to the OS so we can backtrace the other cpus, backtrace when
1043          * spinning in SAL does not work.
1044          */
1045         ia64_mca_wakeup_all();
1046         if (notify_die(DIE_MCA_MONARCH_PROCESS, "MCA", regs, 0, 0, 0)
1047                         == NOTIFY_STOP)
1048                 ia64_mca_spin(__FUNCTION__);
1049
1050         /* Get the MCA error record and log it */
1051         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
1052
1053         /* TLB error is only exist in this SAL error record */
1054         recover = (psp->tc && !(psp->cc || psp->bc || psp->rc || psp->uc))
1055         /* other error recovery */
1056            || (ia64_mca_ucmc_extension
1057                 && ia64_mca_ucmc_extension(
1058                         IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA),
1059                         sos));
1060
1061         if (recover) {
1062                 sal_log_record_header_t *rh = IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA);
1063                 rh->severity = sal_log_severity_corrected;
1064                 ia64_sal_clear_state_info(SAL_INFO_TYPE_MCA);
1065                 sos->os_status = IA64_MCA_CORRECTED;
1066         }
1067         if (notify_die(DIE_MCA_MONARCH_LEAVE, "MCA", regs, 0, 0, recover)
1068                         == NOTIFY_STOP)
1069                 ia64_mca_spin(__FUNCTION__);
1070
1071         set_curr_task(cpu, previous_current);
1072         monarch_cpu = -1;
1073 }
1074
1075 static DECLARE_WORK(cmc_disable_work, ia64_mca_cmc_vector_disable_keventd, NULL);
1076 static DECLARE_WORK(cmc_enable_work, ia64_mca_cmc_vector_enable_keventd, NULL);
1077
1078 /*
1079  * ia64_mca_cmc_int_handler
1080  *
1081  *  This is corrected machine check interrupt handler.
1082  *      Right now the logs are extracted and displayed in a well-defined
1083  *      format.
1084  *
1085  * Inputs
1086  *      interrupt number
1087  *      client data arg ptr
1088  *      saved registers ptr
1089  *
1090  * Outputs
1091  *      None
1092  */
1093 static irqreturn_t
1094 ia64_mca_cmc_int_handler(int cmc_irq, void *arg, struct pt_regs *ptregs)
1095 {
1096         static unsigned long    cmc_history[CMC_HISTORY_LENGTH];
1097         static int              index;
1098         static DEFINE_SPINLOCK(cmc_history_lock);
1099
1100         IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
1101                        __FUNCTION__, cmc_irq, smp_processor_id());
1102
1103         /* SAL spec states this should run w/ interrupts enabled */
1104         local_irq_enable();
1105
1106         /* Get the CMC error record and log it */
1107         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC);
1108
1109         spin_lock(&cmc_history_lock);
1110         if (!cmc_polling_enabled) {
1111                 int i, count = 1; /* we know 1 happened now */
1112                 unsigned long now = jiffies;
1113
1114                 for (i = 0; i < CMC_HISTORY_LENGTH; i++) {
1115                         if (now - cmc_history[i] <= HZ)
1116                                 count++;
1117                 }
1118
1119                 IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH);
1120                 if (count >= CMC_HISTORY_LENGTH) {
1121
1122                         cmc_polling_enabled = 1;
1123                         spin_unlock(&cmc_history_lock);
1124                         /* If we're being hit with CMC interrupts, we won't
1125                          * ever execute the schedule_work() below.  Need to
1126                          * disable CMC interrupts on this processor now.
1127                          */
1128                         ia64_mca_cmc_vector_disable(NULL);
1129                         schedule_work(&cmc_disable_work);
1130
1131                         /*
1132                          * Corrected errors will still be corrected, but
1133                          * make sure there's a log somewhere that indicates
1134                          * something is generating more than we can handle.
1135                          */
1136                         printk(KERN_WARNING "WARNING: Switching to polling CMC handler; error records may be lost\n");
1137
1138                         mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1139
1140                         /* lock already released, get out now */
1141                         return IRQ_HANDLED;
1142                 } else {
1143                         cmc_history[index++] = now;
1144                         if (index == CMC_HISTORY_LENGTH)
1145                                 index = 0;
1146                 }
1147         }
1148         spin_unlock(&cmc_history_lock);
1149         return IRQ_HANDLED;
1150 }
1151
1152 /*
1153  *  ia64_mca_cmc_int_caller
1154  *
1155  *      Triggered by sw interrupt from CMC polling routine.  Calls
1156  *      real interrupt handler and either triggers a sw interrupt
1157  *      on the next cpu or does cleanup at the end.
1158  *
1159  * Inputs
1160  *      interrupt number
1161  *      client data arg ptr
1162  *      saved registers ptr
1163  * Outputs
1164  *      handled
1165  */
1166 static irqreturn_t
1167 ia64_mca_cmc_int_caller(int cmc_irq, void *arg, struct pt_regs *ptregs)
1168 {
1169         static int start_count = -1;
1170         unsigned int cpuid;
1171
1172         cpuid = smp_processor_id();
1173
1174         /* If first cpu, update count */
1175         if (start_count == -1)
1176                 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CMC);
1177
1178         ia64_mca_cmc_int_handler(cmc_irq, arg, ptregs);
1179
1180         for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
1181
1182         if (cpuid < NR_CPUS) {
1183                 platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1184         } else {
1185                 /* If no log record, switch out of polling mode */
1186                 if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) {
1187
1188                         printk(KERN_WARNING "Returning to interrupt driven CMC handler\n");
1189                         schedule_work(&cmc_enable_work);
1190                         cmc_polling_enabled = 0;
1191
1192                 } else {
1193
1194                         mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1195                 }
1196
1197                 start_count = -1;
1198         }
1199
1200         return IRQ_HANDLED;
1201 }
1202
1203 /*
1204  *  ia64_mca_cmc_poll
1205  *
1206  *      Poll for Corrected Machine Checks (CMCs)
1207  *
1208  * Inputs   :   dummy(unused)
1209  * Outputs  :   None
1210  *
1211  */
1212 static void
1213 ia64_mca_cmc_poll (unsigned long dummy)
1214 {
1215         /* Trigger a CMC interrupt cascade  */
1216         platform_send_ipi(first_cpu(cpu_online_map), IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1217 }
1218
1219 /*
1220  *  ia64_mca_cpe_int_caller
1221  *
1222  *      Triggered by sw interrupt from CPE polling routine.  Calls
1223  *      real interrupt handler and either triggers a sw interrupt
1224  *      on the next cpu or does cleanup at the end.
1225  *
1226  * Inputs
1227  *      interrupt number
1228  *      client data arg ptr
1229  *      saved registers ptr
1230  * Outputs
1231  *      handled
1232  */
1233 #ifdef CONFIG_ACPI
1234
1235 static irqreturn_t
1236 ia64_mca_cpe_int_caller(int cpe_irq, void *arg, struct pt_regs *ptregs)
1237 {
1238         static int start_count = -1;
1239         static int poll_time = MIN_CPE_POLL_INTERVAL;
1240         unsigned int cpuid;
1241
1242         cpuid = smp_processor_id();
1243
1244         /* If first cpu, update count */
1245         if (start_count == -1)
1246                 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CPE);
1247
1248         ia64_mca_cpe_int_handler(cpe_irq, arg, ptregs);
1249
1250         for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
1251
1252         if (cpuid < NR_CPUS) {
1253                 platform_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1254         } else {
1255                 /*
1256                  * If a log was recorded, increase our polling frequency,
1257                  * otherwise, backoff or return to interrupt mode.
1258                  */
1259                 if (start_count != IA64_LOG_COUNT(SAL_INFO_TYPE_CPE)) {
1260                         poll_time = max(MIN_CPE_POLL_INTERVAL, poll_time / 2);
1261                 } else if (cpe_vector < 0) {
1262                         poll_time = min(MAX_CPE_POLL_INTERVAL, poll_time * 2);
1263                 } else {
1264                         poll_time = MIN_CPE_POLL_INTERVAL;
1265
1266                         printk(KERN_WARNING "Returning to interrupt driven CPE handler\n");
1267                         enable_irq(local_vector_to_irq(IA64_CPE_VECTOR));
1268                         cpe_poll_enabled = 0;
1269                 }
1270
1271                 if (cpe_poll_enabled)
1272                         mod_timer(&cpe_poll_timer, jiffies + poll_time);
1273                 start_count = -1;
1274         }
1275
1276         return IRQ_HANDLED;
1277 }
1278
1279 /*
1280  *  ia64_mca_cpe_poll
1281  *
1282  *      Poll for Corrected Platform Errors (CPEs), trigger interrupt
1283  *      on first cpu, from there it will trickle through all the cpus.
1284  *
1285  * Inputs   :   dummy(unused)
1286  * Outputs  :   None
1287  *
1288  */
1289 static void
1290 ia64_mca_cpe_poll (unsigned long dummy)
1291 {
1292         /* Trigger a CPE interrupt cascade  */
1293         platform_send_ipi(first_cpu(cpu_online_map), IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1294 }
1295
1296 #endif /* CONFIG_ACPI */
1297
1298 static int
1299 default_monarch_init_process(struct notifier_block *self, unsigned long val, void *data)
1300 {
1301         int c;
1302         struct task_struct *g, *t;
1303         if (val != DIE_INIT_MONARCH_PROCESS)
1304                 return NOTIFY_DONE;
1305         printk(KERN_ERR "Processes interrupted by INIT -");
1306         for_each_online_cpu(c) {
1307                 struct ia64_sal_os_state *s;
1308                 t = __va(__per_cpu_mca[c] + IA64_MCA_CPU_INIT_STACK_OFFSET);
1309                 s = (struct ia64_sal_os_state *)((char *)t + MCA_SOS_OFFSET);
1310                 g = s->prev_task;
1311                 if (g) {
1312                         if (g->pid)
1313                                 printk(" %d", g->pid);
1314                         else
1315                                 printk(" %d (cpu %d task 0x%p)", g->pid, task_cpu(g), g);
1316                 }
1317         }
1318         printk("\n\n");
1319         if (read_trylock(&tasklist_lock)) {
1320                 do_each_thread (g, t) {
1321                         printk("\nBacktrace of pid %d (%s)\n", t->pid, t->comm);
1322                         show_stack(t, NULL);
1323                 } while_each_thread (g, t);
1324                 read_unlock(&tasklist_lock);
1325         }
1326         return NOTIFY_DONE;
1327 }
1328
1329 /*
1330  * C portion of the OS INIT handler
1331  *
1332  * Called from ia64_os_init_dispatch
1333  *
1334  * Inputs: pointer to pt_regs where processor info was saved.  SAL/OS state for
1335  * this event.  This code is used for both monarch and slave INIT events, see
1336  * sos->monarch.
1337  *
1338  * All INIT events switch to the INIT stack and change the previous process to
1339  * blocked status.  If one of the INIT events is the monarch then we are
1340  * probably processing the nmi button/command.  Use the monarch cpu to dump all
1341  * the processes.  The slave INIT events all spin until the monarch cpu
1342  * returns.  We can also get INIT slave events for MCA, in which case the MCA
1343  * process is the monarch.
1344  */
1345
1346 void
1347 ia64_init_handler(struct pt_regs *regs, struct switch_stack *sw,
1348                   struct ia64_sal_os_state *sos)
1349 {
1350         static atomic_t slaves;
1351         static atomic_t monarchs;
1352         task_t *previous_current;
1353         int cpu = smp_processor_id();
1354
1355         oops_in_progress = 1;   /* FIXME: make printk NMI/MCA/INIT safe */
1356         console_loglevel = 15;  /* make sure printks make it to console */
1357
1358         printk(KERN_INFO "Entered OS INIT handler. PSP=%lx cpu=%d monarch=%ld\n",
1359                 sos->proc_state_param, cpu, sos->monarch);
1360         salinfo_log_wakeup(SAL_INFO_TYPE_INIT, NULL, 0, 0);
1361
1362         previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "INIT");
1363         sos->os_status = IA64_INIT_RESUME;
1364
1365         /* FIXME: Workaround for broken proms that drive all INIT events as
1366          * slaves.  The last slave that enters is promoted to be a monarch.
1367          * Remove this code in September 2006, that gives platforms a year to
1368          * fix their proms and get their customers updated.
1369          */
1370         if (!sos->monarch && atomic_add_return(1, &slaves) == num_online_cpus()) {
1371                 printk(KERN_WARNING "%s: Promoting cpu %d to monarch.\n",
1372                        __FUNCTION__, cpu);
1373                 atomic_dec(&slaves);
1374                 sos->monarch = 1;
1375         }
1376
1377         /* FIXME: Workaround for broken proms that drive all INIT events as
1378          * monarchs.  Second and subsequent monarchs are demoted to slaves.
1379          * Remove this code in September 2006, that gives platforms a year to
1380          * fix their proms and get their customers updated.
1381          */
1382         if (sos->monarch && atomic_add_return(1, &monarchs) > 1) {
1383                 printk(KERN_WARNING "%s: Demoting cpu %d to slave.\n",
1384                                __FUNCTION__, cpu);
1385                 atomic_dec(&monarchs);
1386                 sos->monarch = 0;
1387         }
1388
1389         if (!sos->monarch) {
1390                 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_INIT;
1391                 while (monarch_cpu == -1)
1392                        cpu_relax();     /* spin until monarch enters */
1393                 if (notify_die(DIE_INIT_SLAVE_ENTER, "INIT", regs, 0, 0, 0)
1394                                 == NOTIFY_STOP)
1395                         ia64_mca_spin(__FUNCTION__);
1396                 if (notify_die(DIE_INIT_SLAVE_PROCESS, "INIT", regs, 0, 0, 0)
1397                                 == NOTIFY_STOP)
1398                         ia64_mca_spin(__FUNCTION__);
1399                 while (monarch_cpu != -1)
1400                        cpu_relax();     /* spin until monarch leaves */
1401                 if (notify_die(DIE_INIT_SLAVE_LEAVE, "INIT", regs, 0, 0, 0)
1402                                 == NOTIFY_STOP)
1403                         ia64_mca_spin(__FUNCTION__);
1404                 printk("Slave on cpu %d returning to normal service.\n", cpu);
1405                 set_curr_task(cpu, previous_current);
1406                 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1407                 atomic_dec(&slaves);
1408                 return;
1409         }
1410
1411         monarch_cpu = cpu;
1412         if (notify_die(DIE_INIT_MONARCH_ENTER, "INIT", regs, 0, 0, 0)
1413                         == NOTIFY_STOP)
1414                 ia64_mca_spin(__FUNCTION__);
1415
1416         /*
1417          * Wait for a bit.  On some machines (e.g., HP's zx2000 and zx6000, INIT can be
1418          * generated via the BMC's command-line interface, but since the console is on the
1419          * same serial line, the user will need some time to switch out of the BMC before
1420          * the dump begins.
1421          */
1422         printk("Delaying for 5 seconds...\n");
1423         udelay(5*1000000);
1424         ia64_wait_for_slaves(cpu);
1425         /* If nobody intercepts DIE_INIT_MONARCH_PROCESS then we drop through
1426          * to default_monarch_init_process() above and just print all the
1427          * tasks.
1428          */
1429         if (notify_die(DIE_INIT_MONARCH_PROCESS, "INIT", regs, 0, 0, 0)
1430                         == NOTIFY_STOP)
1431                 ia64_mca_spin(__FUNCTION__);
1432         if (notify_die(DIE_INIT_MONARCH_LEAVE, "INIT", regs, 0, 0, 0)
1433                         == NOTIFY_STOP)
1434                 ia64_mca_spin(__FUNCTION__);
1435         printk("\nINIT dump complete.  Monarch on cpu %d returning to normal service.\n", cpu);
1436         atomic_dec(&monarchs);
1437         set_curr_task(cpu, previous_current);
1438         monarch_cpu = -1;
1439         return;
1440 }
1441
1442 static int __init
1443 ia64_mca_disable_cpe_polling(char *str)
1444 {
1445         cpe_poll_enabled = 0;
1446         return 1;
1447 }
1448
1449 __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling);
1450
1451 static struct irqaction cmci_irqaction = {
1452         .handler =      ia64_mca_cmc_int_handler,
1453         .flags =        SA_INTERRUPT,
1454         .name =         "cmc_hndlr"
1455 };
1456
1457 static struct irqaction cmcp_irqaction = {
1458         .handler =      ia64_mca_cmc_int_caller,
1459         .flags =        SA_INTERRUPT,
1460         .name =         "cmc_poll"
1461 };
1462
1463 static struct irqaction mca_rdzv_irqaction = {
1464         .handler =      ia64_mca_rendez_int_handler,
1465         .flags =        SA_INTERRUPT,
1466         .name =         "mca_rdzv"
1467 };
1468
1469 static struct irqaction mca_wkup_irqaction = {
1470         .handler =      ia64_mca_wakeup_int_handler,
1471         .flags =        SA_INTERRUPT,
1472         .name =         "mca_wkup"
1473 };
1474
1475 #ifdef CONFIG_ACPI
1476 static struct irqaction mca_cpe_irqaction = {
1477         .handler =      ia64_mca_cpe_int_handler,
1478         .flags =        SA_INTERRUPT,
1479         .name =         "cpe_hndlr"
1480 };
1481
1482 static struct irqaction mca_cpep_irqaction = {
1483         .handler =      ia64_mca_cpe_int_caller,
1484         .flags =        SA_INTERRUPT,
1485         .name =         "cpe_poll"
1486 };
1487 #endif /* CONFIG_ACPI */
1488
1489 /* Minimal format of the MCA/INIT stacks.  The pseudo processes that run on
1490  * these stacks can never sleep, they cannot return from the kernel to user
1491  * space, they do not appear in a normal ps listing.  So there is no need to
1492  * format most of the fields.
1493  */
1494
1495 static void __cpuinit
1496 format_mca_init_stack(void *mca_data, unsigned long offset,
1497                 const char *type, int cpu)
1498 {
1499         struct task_struct *p = (struct task_struct *)((char *)mca_data + offset);
1500         struct thread_info *ti;
1501         memset(p, 0, KERNEL_STACK_SIZE);
1502         ti = task_thread_info(p);
1503         ti->flags = _TIF_MCA_INIT;
1504         ti->preempt_count = 1;
1505         ti->task = p;
1506         ti->cpu = cpu;
1507         p->thread_info = ti;
1508         p->state = TASK_UNINTERRUPTIBLE;
1509         cpu_set(cpu, p->cpus_allowed);
1510         INIT_LIST_HEAD(&p->tasks);
1511         p->parent = p->real_parent = p->group_leader = p;
1512         INIT_LIST_HEAD(&p->children);
1513         INIT_LIST_HEAD(&p->sibling);
1514         strncpy(p->comm, type, sizeof(p->comm)-1);
1515 }
1516
1517 /* Do per-CPU MCA-related initialization.  */
1518
1519 void __cpuinit
1520 ia64_mca_cpu_init(void *cpu_data)
1521 {
1522         void *pal_vaddr;
1523         static int first_time = 1;
1524
1525         if (first_time) {
1526                 void *mca_data;
1527                 int cpu;
1528
1529                 first_time = 0;
1530                 mca_data = alloc_bootmem(sizeof(struct ia64_mca_cpu)
1531                                          * NR_CPUS + KERNEL_STACK_SIZE);
1532                 mca_data = (void *)(((unsigned long)mca_data +
1533                                         KERNEL_STACK_SIZE - 1) &
1534                                 (-KERNEL_STACK_SIZE));
1535                 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1536                         format_mca_init_stack(mca_data,
1537                                         offsetof(struct ia64_mca_cpu, mca_stack),
1538                                         "MCA", cpu);
1539                         format_mca_init_stack(mca_data,
1540                                         offsetof(struct ia64_mca_cpu, init_stack),
1541                                         "INIT", cpu);
1542                         __per_cpu_mca[cpu] = __pa(mca_data);
1543                         mca_data += sizeof(struct ia64_mca_cpu);
1544                 }
1545         }
1546
1547         /*
1548          * The MCA info structure was allocated earlier and its
1549          * physical address saved in __per_cpu_mca[cpu].  Copy that
1550          * address * to ia64_mca_data so we can access it as a per-CPU
1551          * variable.
1552          */
1553         __get_cpu_var(ia64_mca_data) = __per_cpu_mca[smp_processor_id()];
1554
1555         /*
1556          * Stash away a copy of the PTE needed to map the per-CPU page.
1557          * We may need it during MCA recovery.
1558          */
1559         __get_cpu_var(ia64_mca_per_cpu_pte) =
1560                 pte_val(mk_pte_phys(__pa(cpu_data), PAGE_KERNEL));
1561
1562         /*
1563          * Also, stash away a copy of the PAL address and the PTE
1564          * needed to map it.
1565          */
1566         pal_vaddr = efi_get_pal_addr();
1567         if (!pal_vaddr)
1568                 return;
1569         __get_cpu_var(ia64_mca_pal_base) =
1570                 GRANULEROUNDDOWN((unsigned long) pal_vaddr);
1571         __get_cpu_var(ia64_mca_pal_pte) = pte_val(mk_pte_phys(__pa(pal_vaddr),
1572                                                               PAGE_KERNEL));
1573 }
1574
1575 /*
1576  * ia64_mca_init
1577  *
1578  *  Do all the system level mca specific initialization.
1579  *
1580  *      1. Register spinloop and wakeup request interrupt vectors
1581  *
1582  *      2. Register OS_MCA handler entry point
1583  *
1584  *      3. Register OS_INIT handler entry point
1585  *
1586  *  4. Initialize MCA/CMC/INIT related log buffers maintained by the OS.
1587  *
1588  *  Note that this initialization is done very early before some kernel
1589  *  services are available.
1590  *
1591  *  Inputs  :   None
1592  *
1593  *  Outputs :   None
1594  */
1595 void __init
1596 ia64_mca_init(void)
1597 {
1598         ia64_fptr_t *init_hldlr_ptr_monarch = (ia64_fptr_t *)ia64_os_init_dispatch_monarch;
1599         ia64_fptr_t *init_hldlr_ptr_slave = (ia64_fptr_t *)ia64_os_init_dispatch_slave;
1600         ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch;
1601         int i;
1602         s64 rc;
1603         struct ia64_sal_retval isrv;
1604         u64 timeout = IA64_MCA_RENDEZ_TIMEOUT;  /* platform specific */
1605         static struct notifier_block default_init_monarch_nb = {
1606                 .notifier_call = default_monarch_init_process,
1607                 .priority = 0/* we need to notified last */
1608         };
1609
1610         IA64_MCA_DEBUG("%s: begin\n", __FUNCTION__);
1611
1612         /* Clear the Rendez checkin flag for all cpus */
1613         for(i = 0 ; i < NR_CPUS; i++)
1614                 ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1615
1616         /*
1617          * Register the rendezvous spinloop and wakeup mechanism with SAL
1618          */
1619
1620         /* Register the rendezvous interrupt vector with SAL */
1621         while (1) {
1622                 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT,
1623                                               SAL_MC_PARAM_MECHANISM_INT,
1624                                               IA64_MCA_RENDEZ_VECTOR,
1625                                               timeout,
1626                                               SAL_MC_PARAM_RZ_ALWAYS);
1627                 rc = isrv.status;
1628                 if (rc == 0)
1629                         break;
1630                 if (rc == -2) {
1631                         printk(KERN_INFO "Increasing MCA rendezvous timeout from "
1632                                 "%ld to %ld milliseconds\n", timeout, isrv.v0);
1633                         timeout = isrv.v0;
1634                         continue;
1635                 }
1636                 printk(KERN_ERR "Failed to register rendezvous interrupt "
1637                        "with SAL (status %ld)\n", rc);
1638                 return;
1639         }
1640
1641         /* Register the wakeup interrupt vector with SAL */
1642         isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP,
1643                                       SAL_MC_PARAM_MECHANISM_INT,
1644                                       IA64_MCA_WAKEUP_VECTOR,
1645                                       0, 0);
1646         rc = isrv.status;
1647         if (rc) {
1648                 printk(KERN_ERR "Failed to register wakeup interrupt with SAL "
1649                        "(status %ld)\n", rc);
1650                 return;
1651         }
1652
1653         IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __FUNCTION__);
1654
1655         ia64_mc_info.imi_mca_handler        = ia64_tpa(mca_hldlr_ptr->fp);
1656         /*
1657          * XXX - disable SAL checksum by setting size to 0; should be
1658          *      ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch);
1659          */
1660         ia64_mc_info.imi_mca_handler_size       = 0;
1661
1662         /* Register the os mca handler with SAL */
1663         if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA,
1664                                        ia64_mc_info.imi_mca_handler,
1665                                        ia64_tpa(mca_hldlr_ptr->gp),
1666                                        ia64_mc_info.imi_mca_handler_size,
1667                                        0, 0, 0)))
1668         {
1669                 printk(KERN_ERR "Failed to register OS MCA handler with SAL "
1670                        "(status %ld)\n", rc);
1671                 return;
1672         }
1673
1674         IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __FUNCTION__,
1675                        ia64_mc_info.imi_mca_handler, ia64_tpa(mca_hldlr_ptr->gp));
1676
1677         /*
1678          * XXX - disable SAL checksum by setting size to 0, should be
1679          * size of the actual init handler in mca_asm.S.
1680          */
1681         ia64_mc_info.imi_monarch_init_handler           = ia64_tpa(init_hldlr_ptr_monarch->fp);
1682         ia64_mc_info.imi_monarch_init_handler_size      = 0;
1683         ia64_mc_info.imi_slave_init_handler             = ia64_tpa(init_hldlr_ptr_slave->fp);
1684         ia64_mc_info.imi_slave_init_handler_size        = 0;
1685
1686         IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __FUNCTION__,
1687                        ia64_mc_info.imi_monarch_init_handler);
1688
1689         /* Register the os init handler with SAL */
1690         if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT,
1691                                        ia64_mc_info.imi_monarch_init_handler,
1692                                        ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1693                                        ia64_mc_info.imi_monarch_init_handler_size,
1694                                        ia64_mc_info.imi_slave_init_handler,
1695                                        ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1696                                        ia64_mc_info.imi_slave_init_handler_size)))
1697         {
1698                 printk(KERN_ERR "Failed to register m/s INIT handlers with SAL "
1699                        "(status %ld)\n", rc);
1700                 return;
1701         }
1702         if (register_die_notifier(&default_init_monarch_nb)) {
1703                 printk(KERN_ERR "Failed to register default monarch INIT process\n");
1704                 return;
1705         }
1706
1707         IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __FUNCTION__);
1708
1709         /*
1710          *  Configure the CMCI/P vector and handler. Interrupts for CMC are
1711          *  per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
1712          */
1713         register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction);
1714         register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction);
1715         ia64_mca_cmc_vector_setup();       /* Setup vector on BSP */
1716
1717         /* Setup the MCA rendezvous interrupt vector */
1718         register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction);
1719
1720         /* Setup the MCA wakeup interrupt vector */
1721         register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction);
1722
1723 #ifdef CONFIG_ACPI
1724         /* Setup the CPEI/P handler */
1725         register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
1726 #endif
1727
1728         /* Initialize the areas set aside by the OS to buffer the
1729          * platform/processor error states for MCA/INIT/CMC
1730          * handling.
1731          */
1732         ia64_log_init(SAL_INFO_TYPE_MCA);
1733         ia64_log_init(SAL_INFO_TYPE_INIT);
1734         ia64_log_init(SAL_INFO_TYPE_CMC);
1735         ia64_log_init(SAL_INFO_TYPE_CPE);
1736
1737         mca_init = 1;
1738         printk(KERN_INFO "MCA related initialization done\n");
1739 }
1740
1741 /*
1742  * ia64_mca_late_init
1743  *
1744  *      Opportunity to setup things that require initialization later
1745  *      than ia64_mca_init.  Setup a timer to poll for CPEs if the
1746  *      platform doesn't support an interrupt driven mechanism.
1747  *
1748  *  Inputs  :   None
1749  *  Outputs :   Status
1750  */
1751 static int __init
1752 ia64_mca_late_init(void)
1753 {
1754         if (!mca_init)
1755                 return 0;
1756
1757         /* Setup the CMCI/P vector and handler */
1758         init_timer(&cmc_poll_timer);
1759         cmc_poll_timer.function = ia64_mca_cmc_poll;
1760
1761         /* Unmask/enable the vector */
1762         cmc_polling_enabled = 0;
1763         schedule_work(&cmc_enable_work);
1764
1765         IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __FUNCTION__);
1766
1767 #ifdef CONFIG_ACPI
1768         /* Setup the CPEI/P vector and handler */
1769         cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI);
1770         init_timer(&cpe_poll_timer);
1771         cpe_poll_timer.function = ia64_mca_cpe_poll;
1772
1773         {
1774                 irq_desc_t *desc;
1775                 unsigned int irq;
1776
1777                 if (cpe_vector >= 0) {
1778                         /* If platform supports CPEI, enable the irq. */
1779                         cpe_poll_enabled = 0;
1780                         for (irq = 0; irq < NR_IRQS; ++irq)
1781                                 if (irq_to_vector(irq) == cpe_vector) {
1782                                         desc = irq_descp(irq);
1783                                         desc->status |= IRQ_PER_CPU;
1784                                         setup_irq(irq, &mca_cpe_irqaction);
1785                                         ia64_cpe_irq = irq;
1786                                 }
1787                         ia64_mca_register_cpev(cpe_vector);
1788                         IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n", __FUNCTION__);
1789                 } else {
1790                         /* If platform doesn't support CPEI, get the timer going. */
1791                         if (cpe_poll_enabled) {
1792                                 ia64_mca_cpe_poll(0UL);
1793                                 IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __FUNCTION__);
1794                         }
1795                 }
1796         }
1797 #endif
1798
1799         return 0;
1800 }
1801
1802 device_initcall(ia64_mca_late_init);