2 * Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
3 * Copyright (C) 2004 Intel Corp.
5 * This code is released under the GNU General Public License version 2.
9 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
12 #include <linux/pci.h>
13 #include <linux/init.h>
14 #include <linux/acpi.h>
18 /* aperture is up to 256MB but BIOS may reserve less */
19 #define MMCONFIG_APER_MIN (2 * 1024*1024)
20 #define MMCONFIG_APER_MAX (256 * 1024*1024)
22 /* Assume systems with more busses have correct MCFG */
23 #define MAX_CHECK_BUS 16
25 #define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))
27 /* The base address of the last MMCONFIG device accessed */
28 static u32 mmcfg_last_accessed_device;
30 static DECLARE_BITMAP(fallback_slots, MAX_CHECK_BUS*32);
33 * Functions for accessing PCI configuration space with MMCONFIG accesses
35 static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
38 struct acpi_table_mcfg_config *cfg;
40 if (seg == 0 && bus < MAX_CHECK_BUS &&
41 test_bit(PCI_SLOT(devfn) + 32*bus, fallback_slots))
46 if (cfg_num >= pci_mmcfg_config_num) {
49 cfg = &pci_mmcfg_config[cfg_num];
50 if (cfg->pci_segment_group_number != seg)
52 if ((cfg->start_bus_number <= bus) &&
53 (cfg->end_bus_number >= bus))
54 return cfg->base_address;
57 /* Handle more broken MCFG tables on Asus etc.
58 They only contain a single entry for bus 0-0. Assume
59 this applies to all busses. */
60 cfg = &pci_mmcfg_config[0];
61 if (pci_mmcfg_config_num == 1 &&
62 cfg->pci_segment_group_number == 0 &&
63 (cfg->start_bus_number | cfg->end_bus_number) == 0)
64 return cfg->base_address;
66 /* Fall back to type 0 */
70 static inline void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
72 u32 dev_base = base | (bus << 20) | (devfn << 12);
73 if (dev_base != mmcfg_last_accessed_device) {
74 mmcfg_last_accessed_device = dev_base;
75 set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
79 static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
80 unsigned int devfn, int reg, int len, u32 *value)
85 if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
90 base = get_base_addr(seg, bus, devfn);
92 return pci_conf1_read(seg,bus,devfn,reg,len,value);
94 spin_lock_irqsave(&pci_config_lock, flags);
96 pci_exp_set_dev_base(base, bus, devfn);
100 *value = readb(mmcfg_virt_addr + reg);
103 *value = readw(mmcfg_virt_addr + reg);
106 *value = readl(mmcfg_virt_addr + reg);
110 spin_unlock_irqrestore(&pci_config_lock, flags);
115 static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
116 unsigned int devfn, int reg, int len, u32 value)
121 if ((bus > 255) || (devfn > 255) || (reg > 4095))
124 base = get_base_addr(seg, bus, devfn);
126 return pci_conf1_write(seg,bus,devfn,reg,len,value);
128 spin_lock_irqsave(&pci_config_lock, flags);
130 pci_exp_set_dev_base(base, bus, devfn);
134 writeb(value, mmcfg_virt_addr + reg);
137 writew(value, mmcfg_virt_addr + reg);
140 writel(value, mmcfg_virt_addr + reg);
144 spin_unlock_irqrestore(&pci_config_lock, flags);
149 static struct pci_raw_ops pci_mmcfg = {
150 .read = pci_mmcfg_read,
151 .write = pci_mmcfg_write,
155 static __init void pci_mmcfg_insert_resources(void)
157 #define PCI_MMCFG_RESOURCE_NAME_LEN 19
159 struct resource *res;
163 res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
164 pci_mmcfg_config_num, GFP_KERNEL);
167 printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
171 names = (void *)&res[pci_mmcfg_config_num];
172 for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
173 num_buses = pci_mmcfg_config[i].end_bus_number -
174 pci_mmcfg_config[i].start_bus_number + 1;
176 snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, "PCI MMCONFIG %u",
177 pci_mmcfg_config[i].pci_segment_group_number);
178 res->start = pci_mmcfg_config[i].base_address;
179 res->end = res->start + (num_buses << 20) - 1;
180 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
181 insert_resource(&iomem_resource, res);
182 names += PCI_MMCFG_RESOURCE_NAME_LEN;
186 /* K8 systems have some devices (typically in the builtin northbridge)
187 that are only accessible using type1
188 Normally this can be expressed in the MCFG by not listing them
189 and assigning suitable _SEGs, but this isn't implemented in some BIOS.
190 Instead try to discover all devices on bus 0 that are unreachable using MM
191 and fallback for them. */
192 static __init void unreachable_devices(void)
197 for (k = 0; k < MAX_CHECK_BUS; k++) {
198 for (i = 0; i < 32; i++) {
202 pci_conf1_read(0, k, PCI_DEVFN(i, 0), 0, 4, &val1);
203 if (val1 == 0xffffffff)
206 /* Locking probably not needed, but safer */
207 spin_lock_irqsave(&pci_config_lock, flags);
208 addr = get_base_addr(0, k, PCI_DEVFN(i, 0));
210 pci_exp_set_dev_base(addr, k, PCI_DEVFN(i, 0));
212 readl((u32 __iomem *)mmcfg_virt_addr) != val1) {
213 set_bit(i + 32*k, fallback_slots);
215 "PCI: No mmconfig possible on %x:%x\n", k, i);
217 spin_unlock_irqrestore(&pci_config_lock, flags);
224 void __init pci_mmcfg_init(int type)
226 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
229 acpi_table_parse(ACPI_MCFG, acpi_parse_mcfg);
230 if ((pci_mmcfg_config_num == 0) ||
231 (pci_mmcfg_config == NULL) ||
232 (pci_mmcfg_config[0].base_address == 0))
235 /* Only do this check when type 1 works. If it doesn't work
236 assume we run on a Mac and always use MCFG */
237 if (type == 1 && !e820_all_mapped(pci_mmcfg_config[0].base_address,
238 pci_mmcfg_config[0].base_address + MMCONFIG_APER_MIN,
240 printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %x is not E820-reserved\n",
241 pci_mmcfg_config[0].base_address);
242 printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
246 printk(KERN_INFO "PCI: Using MMCONFIG\n");
247 raw_pci_ops = &pci_mmcfg;
248 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
250 unreachable_devices();
251 pci_mmcfg_insert_resources();