2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
17 #include <linux/init.h>
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/config.h>
21 #include <linux/bootmem.h>
22 #include <linux/smp_lock.h>
23 #include <linux/kernel_stat.h>
24 #include <linux/mc146818rtc.h>
25 #include <linux/bitops.h>
30 #include <asm/mpspec.h>
31 #include <asm/io_apic.h>
33 #include <mach_apic.h>
34 #include <mach_mpparse.h>
35 #include <bios_ebda.h>
37 /* Have we found an MP table */
39 unsigned int __initdata maxcpus = NR_CPUS;
42 * Various Linux-internal data structures created from the
45 int apic_version [MAX_APICS];
46 int mp_bus_id_to_type [MAX_MP_BUSSES];
47 int mp_bus_id_to_node [MAX_MP_BUSSES];
48 int mp_bus_id_to_local [MAX_MP_BUSSES];
49 int quad_local_to_mp_bus_id [NR_CPUS/4][4];
50 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
51 static int mp_current_pci_id;
53 /* I/O APIC entries */
54 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
56 /* # of MP IRQ source entries */
57 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
59 /* MP IRQ source entries */
65 unsigned long mp_lapic_addr;
67 unsigned int def_to_bigsmp = 0;
69 /* Processor that is doing the boot up */
70 unsigned int boot_cpu_physical_apicid = -1U;
71 /* Internal processor count */
72 static unsigned int __devinitdata num_processors;
74 /* Bitmask of physically existing CPUs */
75 physid_mask_t phys_cpu_present_map;
77 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
80 * Intel MP BIOS table parsing routines:
85 * Checksum an MP configuration block.
88 static int __init mpf_checksum(unsigned char *mp, int len)
99 * Have to match translation table entries to main table entries by counter
100 * hence the mpc_record variable .... can't see a less disgusting way of
104 static int mpc_record;
105 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __initdata;
107 static void __devinit MP_processor_info (struct mpc_config_processor *m)
110 physid_mask_t phys_cpu;
112 if (!(m->mpc_cpuflag & CPU_ENABLED))
115 apicid = mpc_apic_id(m, translation_table[mpc_record]);
117 if (m->mpc_featureflag&(1<<0))
118 Dprintk(" Floating point unit present.\n");
119 if (m->mpc_featureflag&(1<<7))
120 Dprintk(" Machine Exception supported.\n");
121 if (m->mpc_featureflag&(1<<8))
122 Dprintk(" 64 bit compare & exchange supported.\n");
123 if (m->mpc_featureflag&(1<<9))
124 Dprintk(" Internal APIC present.\n");
125 if (m->mpc_featureflag&(1<<11))
126 Dprintk(" SEP present.\n");
127 if (m->mpc_featureflag&(1<<12))
128 Dprintk(" MTRR present.\n");
129 if (m->mpc_featureflag&(1<<13))
130 Dprintk(" PGE present.\n");
131 if (m->mpc_featureflag&(1<<14))
132 Dprintk(" MCA present.\n");
133 if (m->mpc_featureflag&(1<<15))
134 Dprintk(" CMOV present.\n");
135 if (m->mpc_featureflag&(1<<16))
136 Dprintk(" PAT present.\n");
137 if (m->mpc_featureflag&(1<<17))
138 Dprintk(" PSE present.\n");
139 if (m->mpc_featureflag&(1<<18))
140 Dprintk(" PSN present.\n");
141 if (m->mpc_featureflag&(1<<19))
142 Dprintk(" Cache Line Flush Instruction present.\n");
144 if (m->mpc_featureflag&(1<<21))
145 Dprintk(" Debug Trace and EMON Store present.\n");
146 if (m->mpc_featureflag&(1<<22))
147 Dprintk(" ACPI Thermal Throttle Registers present.\n");
148 if (m->mpc_featureflag&(1<<23))
149 Dprintk(" MMX present.\n");
150 if (m->mpc_featureflag&(1<<24))
151 Dprintk(" FXSR present.\n");
152 if (m->mpc_featureflag&(1<<25))
153 Dprintk(" XMM present.\n");
154 if (m->mpc_featureflag&(1<<26))
155 Dprintk(" Willamette New Instructions present.\n");
156 if (m->mpc_featureflag&(1<<27))
157 Dprintk(" Self Snoop present.\n");
158 if (m->mpc_featureflag&(1<<28))
159 Dprintk(" HT present.\n");
160 if (m->mpc_featureflag&(1<<29))
161 Dprintk(" Thermal Monitor present.\n");
162 /* 30, 31 Reserved */
165 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
166 Dprintk(" Bootup CPU\n");
167 boot_cpu_physical_apicid = m->mpc_apicid;
170 ver = m->mpc_apicver;
176 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
177 "fixing up to 0x10. (tell your hw vendor)\n",
181 apic_version[m->mpc_apicid] = ver;
183 phys_cpu = apicid_to_cpu_present(apicid);
184 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
186 if (num_processors >= NR_CPUS) {
187 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
188 " Processor ignored.\n", NR_CPUS);
192 if (num_processors >= maxcpus) {
193 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
194 " Processor ignored.\n", maxcpus);
198 cpu_set(num_processors, cpu_possible_map);
202 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
203 * but we need to work other dependencies like SMP_SUSPEND etc
204 * before this can be done without some confusion.
205 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
206 * - Ashok Raj <ashok.raj@intel.com>
208 if (num_processors > 8) {
209 switch (boot_cpu_data.x86_vendor) {
210 case X86_VENDOR_INTEL:
211 if (!APIC_XAPIC(ver)) {
215 /* If P4 and above fall through */
220 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
223 static void __init MP_bus_info (struct mpc_config_bus *m)
227 memcpy(str, m->mpc_bustype, 6);
230 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
232 if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
233 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
234 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
235 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
236 } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
237 mpc_oem_pci_bus(m, translation_table[mpc_record]);
238 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
239 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
241 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
242 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
243 } else if (strncmp(str, BUSTYPE_NEC98, sizeof(BUSTYPE_NEC98)-1) == 0) {
244 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_NEC98;
246 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
250 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
252 if (!(m->mpc_flags & MPC_APIC_USABLE))
255 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%lX.\n",
256 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
257 if (nr_ioapics >= MAX_IO_APICS) {
258 printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
259 MAX_IO_APICS, nr_ioapics);
260 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
262 if (!m->mpc_apicaddr) {
263 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
264 " found in MP table, skipping!\n");
267 mp_ioapics[nr_ioapics] = *m;
271 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
273 mp_irqs [mp_irq_entries] = *m;
274 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
275 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
276 m->mpc_irqtype, m->mpc_irqflag & 3,
277 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
278 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
279 if (++mp_irq_entries == MAX_IRQ_SOURCES)
280 panic("Max # of irq sources exceeded!!\n");
283 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
285 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
286 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
287 m->mpc_irqtype, m->mpc_irqflag & 3,
288 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
289 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
291 * Well it seems all SMP boards in existence
292 * use ExtINT/LVT1 == LINT0 and
293 * NMI/LVT2 == LINT1 - the following check
294 * will show us if this assumptions is false.
295 * Until then we do not have to add baggage.
297 if ((m->mpc_irqtype == mp_ExtINT) &&
298 (m->mpc_destapiclint != 0))
300 if ((m->mpc_irqtype == mp_NMI) &&
301 (m->mpc_destapiclint != 1))
305 #ifdef CONFIG_X86_NUMAQ
306 static void __init MP_translation_info (struct mpc_config_translation *m)
308 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
310 if (mpc_record >= MAX_MPC_ENTRY)
311 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
313 translation_table[mpc_record] = m; /* stash this for later */
314 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
315 node_set_online(m->trans_quad);
319 * Read/parse the MPC oem tables
322 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
323 unsigned short oemsize)
325 int count = sizeof (*oemtable); /* the header size */
326 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
329 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
330 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
332 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
333 oemtable->oem_signature[0],
334 oemtable->oem_signature[1],
335 oemtable->oem_signature[2],
336 oemtable->oem_signature[3]);
339 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
341 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
344 while (count < oemtable->oem_length) {
348 struct mpc_config_translation *m=
349 (struct mpc_config_translation *)oemptr;
350 MP_translation_info(m);
351 oemptr += sizeof(*m);
358 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
365 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
368 if (strncmp(oem, "IBM NUMA", 8))
369 printk("Warning! May not be a NUMA-Q system!\n");
371 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
374 #endif /* CONFIG_X86_NUMAQ */
380 static int __init smp_read_mpc(struct mp_config_table *mpc)
384 int count=sizeof(*mpc);
385 unsigned char *mpt=((unsigned char *)mpc)+count;
387 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
388 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
389 *(u32 *)mpc->mpc_signature);
392 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
393 printk(KERN_ERR "SMP mptable: checksum error!\n");
396 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
397 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
401 if (!mpc->mpc_lapic) {
402 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
405 memcpy(oem,mpc->mpc_oem,8);
407 printk(KERN_INFO "OEM ID: %s ",oem);
409 memcpy(str,mpc->mpc_productid,12);
411 printk("Product ID: %s ",str);
413 mps_oem_check(mpc, oem, str);
415 printk("APIC at: 0x%lX\n",mpc->mpc_lapic);
418 * Save the local APIC address (it might be non-default) -- but only
419 * if we're not using ACPI.
422 mp_lapic_addr = mpc->mpc_lapic;
425 * Now process the configuration blocks.
428 while (count < mpc->mpc_length) {
432 struct mpc_config_processor *m=
433 (struct mpc_config_processor *)mpt;
434 /* ACPI may have already provided this data */
436 MP_processor_info(m);
443 struct mpc_config_bus *m=
444 (struct mpc_config_bus *)mpt;
452 struct mpc_config_ioapic *m=
453 (struct mpc_config_ioapic *)mpt;
461 struct mpc_config_intsrc *m=
462 (struct mpc_config_intsrc *)mpt;
471 struct mpc_config_lintsrc *m=
472 (struct mpc_config_lintsrc *)mpt;
480 count = mpc->mpc_length;
486 clustered_apic_check();
488 printk(KERN_ERR "SMP mptable: no processors registered!\n");
489 return num_processors;
492 static int __init ELCR_trigger(unsigned int irq)
496 port = 0x4d0 + (irq >> 3);
497 return (inb(port) >> (irq & 7)) & 1;
500 static void __init construct_default_ioirq_mptable(int mpc_default_type)
502 struct mpc_config_intsrc intsrc;
504 int ELCR_fallback = 0;
506 intsrc.mpc_type = MP_INTSRC;
507 intsrc.mpc_irqflag = 0; /* conforming */
508 intsrc.mpc_srcbus = 0;
509 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
511 intsrc.mpc_irqtype = mp_INT;
514 * If true, we have an ISA/PCI system with no IRQ entries
515 * in the MP table. To prevent the PCI interrupts from being set up
516 * incorrectly, we try to use the ELCR. The sanity check to see if
517 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
518 * never be level sensitive, so we simply see if the ELCR agrees.
519 * If it does, we assume it's valid.
521 if (mpc_default_type == 5) {
522 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
524 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
525 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
527 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
532 for (i = 0; i < 16; i++) {
533 switch (mpc_default_type) {
535 if (i == 0 || i == 13)
536 continue; /* IRQ0 & IRQ13 not connected */
540 continue; /* IRQ2 is never connected */
545 * If the ELCR indicates a level-sensitive interrupt, we
546 * copy that information over to the MP table in the
547 * irqflag field (level sensitive, active high polarity).
550 intsrc.mpc_irqflag = 13;
552 intsrc.mpc_irqflag = 0;
555 intsrc.mpc_srcbusirq = i;
556 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
557 MP_intsrc_info(&intsrc);
560 intsrc.mpc_irqtype = mp_ExtINT;
561 intsrc.mpc_srcbusirq = 0;
562 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
563 MP_intsrc_info(&intsrc);
566 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
568 struct mpc_config_processor processor;
569 struct mpc_config_bus bus;
570 struct mpc_config_ioapic ioapic;
571 struct mpc_config_lintsrc lintsrc;
572 int linttypes[2] = { mp_ExtINT, mp_NMI };
576 * local APIC has default address
578 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
581 * 2 CPUs, numbered 0 & 1.
583 processor.mpc_type = MP_PROCESSOR;
584 /* Either an integrated APIC or a discrete 82489DX. */
585 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
586 processor.mpc_cpuflag = CPU_ENABLED;
587 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
588 (boot_cpu_data.x86_model << 4) |
589 boot_cpu_data.x86_mask;
590 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
591 processor.mpc_reserved[0] = 0;
592 processor.mpc_reserved[1] = 0;
593 for (i = 0; i < 2; i++) {
594 processor.mpc_apicid = i;
595 MP_processor_info(&processor);
598 bus.mpc_type = MP_BUS;
600 switch (mpc_default_type) {
603 printk(KERN_ERR "Unknown standard configuration %d\n",
608 memcpy(bus.mpc_bustype, "ISA ", 6);
613 memcpy(bus.mpc_bustype, "EISA ", 6);
617 memcpy(bus.mpc_bustype, "MCA ", 6);
620 if (mpc_default_type > 4) {
622 memcpy(bus.mpc_bustype, "PCI ", 6);
626 ioapic.mpc_type = MP_IOAPIC;
627 ioapic.mpc_apicid = 2;
628 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
629 ioapic.mpc_flags = MPC_APIC_USABLE;
630 ioapic.mpc_apicaddr = 0xFEC00000;
631 MP_ioapic_info(&ioapic);
634 * We set up most of the low 16 IO-APIC pins according to MPS rules.
636 construct_default_ioirq_mptable(mpc_default_type);
638 lintsrc.mpc_type = MP_LINTSRC;
639 lintsrc.mpc_irqflag = 0; /* conforming */
640 lintsrc.mpc_srcbusid = 0;
641 lintsrc.mpc_srcbusirq = 0;
642 lintsrc.mpc_destapic = MP_APIC_ALL;
643 for (i = 0; i < 2; i++) {
644 lintsrc.mpc_irqtype = linttypes[i];
645 lintsrc.mpc_destapiclint = i;
646 MP_lintsrc_info(&lintsrc);
650 static struct intel_mp_floating *mpf_found;
653 * Scan the memory blocks for an SMP configuration block.
655 void __init get_smp_config (void)
657 struct intel_mp_floating *mpf = mpf_found;
660 * ACPI supports both logical (e.g. Hyper-Threading) and physical
661 * processors, where MPS only supports physical.
663 if (acpi_lapic && acpi_ioapic) {
664 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
668 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
670 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
671 if (mpf->mpf_feature2 & (1<<7)) {
672 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
675 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
680 * Now see if we need to read further.
682 if (mpf->mpf_feature1 != 0) {
684 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
685 construct_default_ISA_mptable(mpf->mpf_feature1);
687 } else if (mpf->mpf_physptr) {
690 * Read the physical hardware table. Anything here will
691 * override the defaults.
693 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
694 smp_found_config = 0;
695 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
696 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
700 * If there are no explicit MP IRQ entries, then we are
701 * broken. We set up most of the low 16 IO-APIC pins to
702 * ISA defaults and hope it will work.
704 if (!mp_irq_entries) {
705 struct mpc_config_bus bus;
707 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
709 bus.mpc_type = MP_BUS;
711 memcpy(bus.mpc_bustype, "ISA ", 6);
714 construct_default_ioirq_mptable(0);
720 printk(KERN_INFO "Processors: %d\n", num_processors);
722 * Only use the first configuration found.
726 static int __init smp_scan_config (unsigned long base, unsigned long length)
728 unsigned long *bp = phys_to_virt(base);
729 struct intel_mp_floating *mpf;
731 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
732 if (sizeof(*mpf) != 16)
733 printk("Error: MPF size\n");
736 mpf = (struct intel_mp_floating *)bp;
737 if ((*bp == SMP_MAGIC_IDENT) &&
738 (mpf->mpf_length == 1) &&
739 !mpf_checksum((unsigned char *)bp, 16) &&
740 ((mpf->mpf_specification == 1)
741 || (mpf->mpf_specification == 4)) ) {
743 smp_found_config = 1;
744 printk(KERN_INFO "found SMP MP-table at %08lx\n",
746 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE);
747 if (mpf->mpf_physptr) {
749 * We cannot access to MPC table to compute
750 * table size yet, as only few megabytes from
751 * the bottom is mapped now.
752 * PC-9800's MPC table places on the very last
753 * of physical memory; so that simply reserving
754 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
755 * in reserve_bootmem.
757 unsigned long size = PAGE_SIZE;
758 unsigned long end = max_low_pfn * PAGE_SIZE;
759 if (mpf->mpf_physptr + size > end)
760 size = end - mpf->mpf_physptr;
761 reserve_bootmem(mpf->mpf_physptr, size);
773 void __init find_smp_config (void)
775 unsigned int address;
778 * FIXME: Linux assumes you have 640K of base ram..
779 * this continues the error...
781 * 1) Scan the bottom 1K for a signature
782 * 2) Scan the top 1K of base RAM
783 * 3) Scan the 64K of bios
785 if (smp_scan_config(0x0,0x400) ||
786 smp_scan_config(639*0x400,0x400) ||
787 smp_scan_config(0xF0000,0x10000))
790 * If it is an SMP machine we should know now, unless the
791 * configuration is in an EISA/MCA bus machine with an
792 * extended bios data area.
794 * there is a real-mode segmented pointer pointing to the
795 * 4K EBDA area at 0x40E, calculate and scan it here.
797 * NOTE! There are Linux loaders that will corrupt the EBDA
798 * area, and as such this kind of SMP config may be less
799 * trustworthy, simply because the SMP table may have been
800 * stomped on during early boot. These loaders are buggy and
803 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
806 address = get_bios_ebda();
808 smp_scan_config(address, 0x400);
813 /* --------------------------------------------------------------------------
814 ACPI-based MP Configuration
815 -------------------------------------------------------------------------- */
819 void __init mp_register_lapic_address (
822 mp_lapic_addr = (unsigned long) address;
824 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
826 if (boot_cpu_physical_apicid == -1U)
827 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
829 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
833 void __devinit mp_register_lapic (
837 struct mpc_config_processor processor;
840 if (MAX_APICS - id <= 0) {
841 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
846 if (id == boot_cpu_physical_apicid)
849 processor.mpc_type = MP_PROCESSOR;
850 processor.mpc_apicid = id;
851 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
852 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
853 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
854 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
855 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
856 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
857 processor.mpc_reserved[0] = 0;
858 processor.mpc_reserved[1] = 0;
860 MP_processor_info(&processor);
863 #ifdef CONFIG_X86_IO_APIC
866 #define MP_MAX_IOAPIC_PIN 127
868 static struct mp_ioapic_routing {
872 u32 pin_programmed[4];
873 } mp_ioapic_routing[MAX_IO_APICS];
876 static int mp_find_ioapic (
881 /* Find the IOAPIC that manages this GSI. */
882 for (i = 0; i < nr_ioapics; i++) {
883 if ((gsi >= mp_ioapic_routing[i].gsi_base)
884 && (gsi <= mp_ioapic_routing[i].gsi_end))
888 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
894 void __init mp_register_ioapic (
902 if (nr_ioapics >= MAX_IO_APICS) {
903 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
904 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
905 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
908 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
909 " found in MADT table, skipping!\n");
915 mp_ioapics[idx].mpc_type = MP_IOAPIC;
916 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
917 mp_ioapics[idx].mpc_apicaddr = address;
919 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
920 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
921 && !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
922 tmpid = io_apic_get_unique_id(idx, id);
929 mp_ioapics[idx].mpc_apicid = tmpid;
930 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
933 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
934 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
936 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
937 mp_ioapic_routing[idx].gsi_base = gsi_base;
938 mp_ioapic_routing[idx].gsi_end = gsi_base +
939 io_apic_get_redir_entries(idx);
941 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%lx, "
942 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
943 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
944 mp_ioapic_routing[idx].gsi_base,
945 mp_ioapic_routing[idx].gsi_end);
951 void __init mp_override_legacy_irq (
957 struct mpc_config_intsrc intsrc;
962 * Convert 'gsi' to 'ioapic.pin'.
964 ioapic = mp_find_ioapic(gsi);
967 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
970 * TBD: This check is for faulty timer entries, where the override
971 * erroneously sets the trigger to level, resulting in a HUGE
972 * increase of timer interrupts!
974 if ((bus_irq == 0) && (trigger == 3))
977 intsrc.mpc_type = MP_INTSRC;
978 intsrc.mpc_irqtype = mp_INT;
979 intsrc.mpc_irqflag = (trigger << 2) | polarity;
980 intsrc.mpc_srcbus = MP_ISA_BUS;
981 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
982 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
983 intsrc.mpc_dstirq = pin; /* INTIN# */
985 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
986 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
987 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
988 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
990 mp_irqs[mp_irq_entries] = intsrc;
991 if (++mp_irq_entries == MAX_IRQ_SOURCES)
992 panic("Max # of irq sources exceeded!\n");
997 void __init mp_config_acpi_legacy_irqs (void)
999 struct mpc_config_intsrc intsrc;
1004 * Fabricate the legacy ISA bus (bus #31).
1006 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
1007 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
1010 * Older generations of ES7000 have no legacy identity mappings
1012 if (es7000_plat == 1)
1016 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1018 ioapic = mp_find_ioapic(0);
1022 intsrc.mpc_type = MP_INTSRC;
1023 intsrc.mpc_irqflag = 0; /* Conforming */
1024 intsrc.mpc_srcbus = MP_ISA_BUS;
1025 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1028 * Use the default configuration for the IRQs 0-15. Unless
1029 * overriden by (MADT) interrupt source override entries.
1031 for (i = 0; i < 16; i++) {
1034 for (idx = 0; idx < mp_irq_entries; idx++) {
1035 struct mpc_config_intsrc *irq = mp_irqs + idx;
1037 /* Do we already have a mapping for this ISA IRQ? */
1038 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1041 /* Do we already have a mapping for this IOAPIC pin */
1042 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1043 (irq->mpc_dstirq == i))
1047 if (idx != mp_irq_entries) {
1048 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1049 continue; /* IRQ already used */
1052 intsrc.mpc_irqtype = mp_INT;
1053 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1054 intsrc.mpc_dstirq = i;
1056 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1057 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1058 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1059 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1062 mp_irqs[mp_irq_entries] = intsrc;
1063 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1064 panic("Max # of irq sources exceeded!\n");
1068 #define MAX_GSI_NUM 4096
1070 int mp_register_gsi (u32 gsi, int triggering, int polarity)
1075 static int pci_irq = 16;
1077 * Mapping between Global System Interrups, which
1078 * represent all possible interrupts, and IRQs
1079 * assigned to actual devices.
1081 static int gsi_to_irq[MAX_GSI_NUM];
1083 /* Don't set up the ACPI SCI because it's already set up */
1084 if (acpi_fadt.sci_int == gsi)
1087 ioapic = mp_find_ioapic(gsi);
1089 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1093 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1095 if (ioapic_renumber_irq)
1096 gsi = ioapic_renumber_irq(ioapic, gsi);
1099 * Avoid pin reprogramming. PRTs typically include entries
1100 * with redundant pin->gsi mappings (but unique PCI devices);
1101 * we only program the IOAPIC on the first.
1103 bit = ioapic_pin % 32;
1104 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1106 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1107 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1111 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1112 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1113 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1114 return gsi_to_irq[gsi];
1117 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1119 if (triggering == ACPI_LEVEL_SENSITIVE) {
1121 * For PCI devices assign IRQs in order, avoiding gaps
1122 * due to unused I/O APIC pins.
1125 if (gsi < MAX_GSI_NUM) {
1129 * Don't assign IRQ used by ACPI SCI
1131 if (gsi == acpi_fadt.sci_int)
1133 gsi_to_irq[irq] = gsi;
1135 printk(KERN_ERR "GSI %u is too high\n", gsi);
1140 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1141 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1142 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1146 #endif /* CONFIG_X86_IO_APIC */
1147 #endif /* CONFIG_ACPI */