arch/i386/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/compiler.h>
  31 #include <linux/acpi.h>
  32 #include <linux/module.h>
  33 #include <linux/sysdev.h>
  34 #include <linux/pci.h>
  35 #include <linux/msi.h>
  36 #include <linux/htirq.h>
  37 #include <linux/freezer.h>
  38
  39 #include <asm/io.h>
  40 #include <asm/smp.h>
  41 #include <asm/desc.h>
  42 #include <asm/timer.h>
  43 #include <asm/i8259.h>
  44 #include <asm/nmi.h>
  45 #include <asm/msidef.h>
  46 #include <asm/hypertransport.h>
  47
  48 #include <mach_apic.h>
  49 #include <mach_apicdef.h>
  50
  51 #include "io_ports.h"
  52
  53 int (*ioapic_renumber_irq)(int ioapic, int irq);
  54 atomic_t irq_mis_count;
  55
  56 /* Where if anywhere is the i8259 connect in external int mode */
  57 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  58
  59 static DEFINE_SPINLOCK(ioapic_lock);
  60 static DEFINE_SPINLOCK(vector_lock);
  61
  62 int timer_over_8254 __initdata = 1;
  63
  64 /*
  65  *      Is the SiS APIC rmw bug present ?
  66  *      -1 = don't know, 0 = no, 1 = yes
  67  */
  68 int sis_apic_bug = -1;
  69
  70 /*
  71  * # of IRQ routing registers
  72  */
  73 int nr_ioapic_registers[MAX_IO_APICS];
  74
  75 static int disable_timer_pin_1 __initdata;
  76
  77 /*
  78  * Rough estimation of how many shared IRQs there are, can
  79  * be changed anytime.
  80  */
  81 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  82 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  83
  84 /*
  85  * This is performance-critical, we want to do it O(1)
  86  *
  87  * the indexing order of this array favors 1:1 mappings
  88  * between pins and IRQs.
  89  */
  90
  91 static struct irq_pin_list {
  92         int apic, pin, next;
  93 } irq_2_pin[PIN_MAP_SIZE];
  94
  95 struct io_apic {
  96         unsigned int index;
  97         unsigned int unused[3];
  98         unsigned int data;
  99 };
 100
 101 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 102 {
 103         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 104                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
 105 }
 106
 107 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 108 {
 109         struct io_apic __iomem *io_apic = io_apic_base(apic);
 110         writel(reg, &io_apic->index);
 111         return readl(&io_apic->data);
 112 }
 113
 114 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 115 {
 116         struct io_apic __iomem *io_apic = io_apic_base(apic);
 117         writel(reg, &io_apic->index);
 118         writel(value, &io_apic->data);
 119 }
 120
 121 /*
 122  * Re-write a value: to be used for read-modify-write
 123  * cycles where the read already set up the index register.
 124  *
 125  * Older SiS APIC requires we rewrite the index register
 126  */
 127 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
 128 {
 129         volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
 130         if (sis_apic_bug)
 131                 writel(reg, &io_apic->index);
 132         writel(value, &io_apic->data);
 133 }
 134
 135 union entry_union {
 136         struct { u32 w1, w2; };
 137         struct IO_APIC_route_entry entry;
 138 };
 139
 140 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 141 {
 142         union entry_union eu;
 143         unsigned long flags;
 144         spin_lock_irqsave(&ioapic_lock, flags);
 145         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 146         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 147         spin_unlock_irqrestore(&ioapic_lock, flags);
 148         return eu.entry;
 149 }
 150
 151 /*
 152  * When we write a new IO APIC routing entry, we need to write the high
 153  * word first! If the mask bit in the low word is clear, we will enable
 154  * the interrupt, and we need to make sure the entry is fully populated
 155  * before that happens.
 156  */
 157 static void
 158 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 159 {
 160         union entry_union eu;
 161         eu.entry = e;
 162         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 163         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 164 }
 165
 166 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 167 {
 168         unsigned long flags;
 169         spin_lock_irqsave(&ioapic_lock, flags);
 170         __ioapic_write_entry(apic, pin, e);
 171         spin_unlock_irqrestore(&ioapic_lock, flags);
 172 }
 173
 174 /*
 175  * When we mask an IO APIC routing entry, we need to write the low
 176  * word first, in order to set the mask bit before we change the
 177  * high bits!
 178  */
 179 static void ioapic_mask_entry(int apic, int pin)
 180 {
 181         unsigned long flags;
 182         union entry_union eu = { .entry.mask = 1 };
 183
 184         spin_lock_irqsave(&ioapic_lock, flags);
 185         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 186         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 187         spin_unlock_irqrestore(&ioapic_lock, flags);
 188 }
 189
 190 /*
 191  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 192  * shared ISA-space IRQs, so we have to support them. We are super
 193  * fast in the common case, and fast for shared ISA-space IRQs.
 194  */
 195 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 196 {
 197         static int first_free_entry = NR_IRQS;
 198         struct irq_pin_list *entry = irq_2_pin + irq;
 199
 200         while (entry->next)
 201                 entry = irq_2_pin + entry->next;
 202
 203         if (entry->pin != -1) {
 204                 entry->next = first_free_entry;
 205                 entry = irq_2_pin + entry->next;
 206                 if (++first_free_entry >= PIN_MAP_SIZE)
 207                         panic("io_apic.c: whoops");
 208         }
 209         entry->apic = apic;
 210         entry->pin = pin;
 211 }
 212
 213 /*
 214  * Reroute an IRQ to a different pin.
 215  */
 216 static void __init replace_pin_at_irq(unsigned int irq,
 217                                       int oldapic, int oldpin,
 218                                       int newapic, int newpin)
 219 {
 220         struct irq_pin_list *entry = irq_2_pin + irq;
 221
 222         while (1) {
 223                 if (entry->apic == oldapic && entry->pin == oldpin) {
 224                         entry->apic = newapic;
 225                         entry->pin = newpin;
 226                 }
 227                 if (!entry->next)
 228                         break;
 229                 entry = irq_2_pin + entry->next;
 230         }
 231 }
 232
 233 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 234 {
 235         struct irq_pin_list *entry = irq_2_pin + irq;
 236         unsigned int pin, reg;
 237
 238         for (;;) {
 239                 pin = entry->pin;
 240                 if (pin == -1)
 241                         break;
 242                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 243                 reg &= ~disable;
 244                 reg |= enable;
 245                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 246                 if (!entry->next)
 247                         break;
 248                 entry = irq_2_pin + entry->next;
 249         }
 250 }
 251
 252 /* mask = 1 */
 253 static void __mask_IO_APIC_irq (unsigned int irq)
 254 {
 255         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 256 }
 257
 258 /* mask = 0 */
 259 static void __unmask_IO_APIC_irq (unsigned int irq)
 260 {
 261         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 262 }
 263
 264 /* mask = 1, trigger = 0 */
 265 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 266 {
 267         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 268 }
 269
 270 /* mask = 0, trigger = 1 */
 271 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 272 {
 273         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 274 }
 275
 276 static void mask_IO_APIC_irq (unsigned int irq)
 277 {
 278         unsigned long flags;
 279
 280         spin_lock_irqsave(&ioapic_lock, flags);
 281         __mask_IO_APIC_irq(irq);
 282         spin_unlock_irqrestore(&ioapic_lock, flags);
 283 }
 284
 285 static void unmask_IO_APIC_irq (unsigned int irq)
 286 {
 287         unsigned long flags;
 288
 289         spin_lock_irqsave(&ioapic_lock, flags);
 290         __unmask_IO_APIC_irq(irq);
 291         spin_unlock_irqrestore(&ioapic_lock, flags);
 292 }
 293
 294 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 295 {
 296         struct IO_APIC_route_entry entry;
 297
 298         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 299         entry = ioapic_read_entry(apic, pin);
 300         if (entry.delivery_mode == dest_SMI)
 301                 return;
 302
 303         /*
 304          * Disable it in the IO-APIC irq-routing table:
 305          */
 306         ioapic_mask_entry(apic, pin);
 307 }
 308
 309 static void clear_IO_APIC (void)
 310 {
 311         int apic, pin;
 312
 313         for (apic = 0; apic < nr_ioapics; apic++)
 314                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 315                         clear_IO_APIC_pin(apic, pin);
 316 }
 317
 318 #ifdef CONFIG_SMP
 319 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 320 {
 321         unsigned long flags;
 322         int pin;
 323         struct irq_pin_list *entry = irq_2_pin + irq;
 324         unsigned int apicid_value;
 325         cpumask_t tmp;
 326
 327         cpus_and(tmp, cpumask, cpu_online_map);
 328         if (cpus_empty(tmp))
 329                 tmp = TARGET_CPUS;
 330
 331         cpus_and(cpumask, tmp, CPU_MASK_ALL);
 332
 333         apicid_value = cpu_mask_to_apicid(cpumask);
 334         /* Prepare to do the io_apic_write */
 335         apicid_value = apicid_value << 24;
 336         spin_lock_irqsave(&ioapic_lock, flags);
 337         for (;;) {
 338                 pin = entry->pin;
 339                 if (pin == -1)
 340                         break;
 341                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 342                 if (!entry->next)
 343                         break;
 344                 entry = irq_2_pin + entry->next;
 345         }
 346         irq_desc[irq].affinity = cpumask;
 347         spin_unlock_irqrestore(&ioapic_lock, flags);
 348 }
 349
 350 #if defined(CONFIG_IRQBALANCE)
 351 # include <asm/processor.h>     /* kernel_thread() */
 352 # include <linux/kernel_stat.h> /* kstat */
 353 # include <linux/slab.h>                /* kmalloc() */
 354 # include <linux/timer.h>       /* time_after() */
 355
 356 #ifdef CONFIG_BALANCED_IRQ_DEBUG
 357 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
 358 #  define Dprintk(x...) do { TDprintk(x); } while (0)
 359 # else
 360 #  define TDprintk(x...)
 361 #  define Dprintk(x...)
 362 # endif
 363
 364 #define IRQBALANCE_CHECK_ARCH -999
 365 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 366 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 367 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 368 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 369
 370 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
 371 static int physical_balance __read_mostly;
 372 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
 373
 374 static struct irq_cpu_info {
 375         unsigned long * last_irq;
 376         unsigned long * irq_delta;
 377         unsigned long irq;
 378 } irq_cpu_data[NR_CPUS];
 379
 380 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 381 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 382 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 383
 384 #define IDLE_ENOUGH(cpu,now) \
 385         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 386
 387 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 388
 389 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
 390
 391 static cpumask_t balance_irq_affinity[NR_IRQS] = {
 392         [0 ... NR_IRQS-1] = CPU_MASK_ALL
 393 };
 394
 395 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
 396 {
 397         balance_irq_affinity[irq] = mask;
 398 }
 399
 400 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 401                         unsigned long now, int direction)
 402 {
 403         int search_idle = 1;
 404         int cpu = curr_cpu;
 405
 406         goto inside;
 407
 408         do {
 409                 if (unlikely(cpu == curr_cpu))
 410                         search_idle = 0;
 411 inside:
 412                 if (direction == 1) {
 413                         cpu++;
 414                         if (cpu >= NR_CPUS)
 415                                 cpu = 0;
 416                 } else {
 417                         cpu--;
 418                         if (cpu == -1)
 419                                 cpu = NR_CPUS-1;
 420                 }
 421         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 422                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 423
 424         return cpu;
 425 }
 426
 427 static inline void balance_irq(int cpu, int irq)
 428 {
 429         unsigned long now = jiffies;
 430         cpumask_t allowed_mask;
 431         unsigned int new_cpu;
 432
 433         if (irqbalance_disabled)
 434                 return;
 435
 436         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
 437         new_cpu = move(cpu, allowed_mask, now, 1);
 438         if (cpu != new_cpu) {
 439                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
 440         }
 441 }
 442
 443 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 444 {
 445         int i, j;
 446         Dprintk("Rotating IRQs among CPUs.\n");
 447         for_each_online_cpu(i) {
 448                 for (j = 0; j < NR_IRQS; j++) {
 449                         if (!irq_desc[j].action)
 450                                 continue;
 451                         /* Is it a significant load ?  */
 452                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 453                                                 useful_load_threshold)
 454                                 continue;
 455                         balance_irq(i, j);
 456                 }
 457         }
 458         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 459                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 460         return;
 461 }
 462
 463 static void do_irq_balance(void)
 464 {
 465         int i, j;
 466         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 467         unsigned long move_this_load = 0;
 468         int max_loaded = 0, min_loaded = 0;
 469         int load;
 470         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 471         int selected_irq;
 472         int tmp_loaded, first_attempt = 1;
 473         unsigned long tmp_cpu_irq;
 474         unsigned long imbalance = 0;
 475         cpumask_t allowed_mask, target_cpu_mask, tmp;
 476
 477         for_each_possible_cpu(i) {
 478                 int package_index;
 479                 CPU_IRQ(i) = 0;
 480                 if (!cpu_online(i))
 481                         continue;
 482                 package_index = CPU_TO_PACKAGEINDEX(i);
 483                 for (j = 0; j < NR_IRQS; j++) {
 484                         unsigned long value_now, delta;
 485                         /* Is this an active IRQ or balancing disabled ? */
 486                         if (!irq_desc[j].action || irq_balancing_disabled(j))
 487                                 continue;
 488                         if ( package_index == i )
 489                                 IRQ_DELTA(package_index,j) = 0;
 490                         /* Determine the total count per processor per IRQ */
 491                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 492
 493                         /* Determine the activity per processor per IRQ */
 494                         delta = value_now - LAST_CPU_IRQ(i,j);
 495
 496                         /* Update last_cpu_irq[][] for the next time */
 497                         LAST_CPU_IRQ(i,j) = value_now;
 498
 499                         /* Ignore IRQs whose rate is less than the clock */
 500                         if (delta < useful_load_threshold)
 501                                 continue;
 502                         /* update the load for the processor or package total */
 503                         IRQ_DELTA(package_index,j) += delta;
 504
 505                         /* Keep track of the higher numbered sibling as well */
 506                         if (i != package_index)
 507                                 CPU_IRQ(i) += delta;
 508                         /*
 509                          * We have sibling A and sibling B in the package
 510                          *
 511                          * cpu_irq[A] = load for cpu A + load for cpu B
 512                          * cpu_irq[B] = load for cpu B
 513                          */
 514                         CPU_IRQ(package_index) += delta;
 515                 }
 516         }
 517         /* Find the least loaded processor package */
 518         for_each_online_cpu(i) {
 519                 if (i != CPU_TO_PACKAGEINDEX(i))
 520                         continue;
 521                 if (min_cpu_irq > CPU_IRQ(i)) {
 522                         min_cpu_irq = CPU_IRQ(i);
 523                         min_loaded = i;
 524                 }
 525         }
 526         max_cpu_irq = ULONG_MAX;
 527
 528 tryanothercpu:
 529         /* Look for heaviest loaded processor.
 530          * We may come back to get the next heaviest loaded processor.
 531          * Skip processors with trivial loads.
 532          */
 533         tmp_cpu_irq = 0;
 534         tmp_loaded = -1;
 535         for_each_online_cpu(i) {
 536                 if (i != CPU_TO_PACKAGEINDEX(i))
 537                         continue;
 538                 if (max_cpu_irq <= CPU_IRQ(i))
 539                         continue;
 540                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 541                         tmp_cpu_irq = CPU_IRQ(i);
 542                         tmp_loaded = i;
 543                 }
 544         }
 545
 546         if (tmp_loaded == -1) {
 547          /* In the case of small number of heavy interrupt sources,
 548           * loading some of the cpus too much. We use Ingo's original
 549           * approach to rotate them around.
 550           */
 551                 if (!first_attempt && imbalance >= useful_load_threshold) {
 552                         rotate_irqs_among_cpus(useful_load_threshold);
 553                         return;
 554                 }
 555                 goto not_worth_the_effort;
 556         }
 557
 558         first_attempt = 0;              /* heaviest search */
 559         max_cpu_irq = tmp_cpu_irq;      /* load */
 560         max_loaded = tmp_loaded;        /* processor */
 561         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 562
 563         Dprintk("max_loaded cpu = %d\n", max_loaded);
 564         Dprintk("min_loaded cpu = %d\n", min_loaded);
 565         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
 566         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
 567         Dprintk("load imbalance = %lu\n", imbalance);
 568
 569         /* if imbalance is less than approx 10% of max load, then
 570          * observe diminishing returns action. - quit
 571          */
 572         if (imbalance < (max_cpu_irq >> 3)) {
 573                 Dprintk("Imbalance too trivial\n");
 574                 goto not_worth_the_effort;
 575         }
 576
 577 tryanotherirq:
 578         /* if we select an IRQ to move that can't go where we want, then
 579          * see if there is another one to try.
 580          */
 581         move_this_load = 0;
 582         selected_irq = -1;
 583         for (j = 0; j < NR_IRQS; j++) {
 584                 /* Is this an active IRQ? */
 585                 if (!irq_desc[j].action)
 586                         continue;
 587                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 588                         continue;
 589                 /* Try to find the IRQ that is closest to the imbalance
 590                  * without going over.
 591                  */
 592                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 593                         move_this_load = IRQ_DELTA(max_loaded,j);
 594                         selected_irq = j;
 595                 }
 596         }
 597         if (selected_irq == -1) {
 598                 goto tryanothercpu;
 599         }
 600
 601         imbalance = move_this_load;
 602
 603         /* For physical_balance case, we accumlated both load
 604          * values in the one of the siblings cpu_irq[],
 605          * to use the same code for physical and logical processors
 606          * as much as possible.
 607          *
 608          * NOTE: the cpu_irq[] array holds the sum of the load for
 609          * sibling A and sibling B in the slot for the lowest numbered
 610          * sibling (A), _AND_ the load for sibling B in the slot for
 611          * the higher numbered sibling.
 612          *
 613          * We seek the least loaded sibling by making the comparison
 614          * (A+B)/2 vs B
 615          */
 616         load = CPU_IRQ(min_loaded) >> 1;
 617         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
 618                 if (load > CPU_IRQ(j)) {
 619                         /* This won't change cpu_sibling_map[min_loaded] */
 620                         load = CPU_IRQ(j);
 621                         min_loaded = j;
 622                 }
 623         }
 624
 625         cpus_and(allowed_mask,
 626                 cpu_online_map,
 627                 balance_irq_affinity[selected_irq]);
 628         target_cpu_mask = cpumask_of_cpu(min_loaded);
 629         cpus_and(tmp, target_cpu_mask, allowed_mask);
 630
 631         if (!cpus_empty(tmp)) {
 632
 633                 Dprintk("irq = %d moved to cpu = %d\n",
 634                                 selected_irq, min_loaded);
 635                 /* mark for change destination */
 636                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 637
 638                 /* Since we made a change, come back sooner to
 639                  * check for more variation.
 640                  */
 641                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 642                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 643                 return;
 644         }
 645         goto tryanotherirq;
 646
 647 not_worth_the_effort:
 648         /*
 649          * if we did not find an IRQ to move, then adjust the time interval
 650          * upward
 651          */
 652         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 653                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 654         Dprintk("IRQ worth rotating not found\n");
 655         return;
 656 }
 657
 658 static int balanced_irq(void *unused)
 659 {
 660         int i;
 661         unsigned long prev_balance_time = jiffies;
 662         long time_remaining = balanced_irq_interval;
 663
 664         daemonize("kirqd");
 665
 666         /* push everything to CPU 0 to give us a starting point.  */
 667         for (i = 0 ; i < NR_IRQS ; i++) {
 668                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
 669                 set_pending_irq(i, cpumask_of_cpu(0));
 670         }
 671
 672         for ( ; ; ) {
 673                 time_remaining = schedule_timeout_interruptible(time_remaining);
 674                 try_to_freeze();
 675                 if (time_after(jiffies,
 676                                 prev_balance_time+balanced_irq_interval)) {
 677                         preempt_disable();
 678                         do_irq_balance();
 679                         prev_balance_time = jiffies;
 680                         time_remaining = balanced_irq_interval;
 681                         preempt_enable();
 682                 }
 683         }
 684         return 0;
 685 }
 686
 687 static int __init balanced_irq_init(void)
 688 {
 689         int i;
 690         struct cpuinfo_x86 *c;
 691         cpumask_t tmp;
 692
 693         cpus_shift_right(tmp, cpu_online_map, 2);
 694         c = &boot_cpu_data;
 695         /* When not overwritten by the command line ask subarchitecture. */
 696         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 697                 irqbalance_disabled = NO_BALANCE_IRQ;
 698         if (irqbalance_disabled)
 699                 return 0;
 700
 701          /* disable irqbalance completely if there is only one processor online */
 702         if (num_online_cpus() < 2) {
 703                 irqbalance_disabled = 1;
 704                 return 0;
 705         }
 706         /*
 707          * Enable physical balance only if more than 1 physical processor
 708          * is present
 709          */
 710         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 711                 physical_balance = 1;
 712
 713         for_each_online_cpu(i) {
 714                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 715                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 716                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 717                         printk(KERN_ERR "balanced_irq_init: out of memory");
 718                         goto failed;
 719                 }
 720                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 721                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 722         }
 723
 724         printk(KERN_INFO "Starting balanced_irq\n");
 725         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
 726                 return 0;
 727         else
 728                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 729 failed:
 730         for_each_possible_cpu(i) {
 731                 kfree(irq_cpu_data[i].irq_delta);
 732                 irq_cpu_data[i].irq_delta = NULL;
 733                 kfree(irq_cpu_data[i].last_irq);
 734                 irq_cpu_data[i].last_irq = NULL;
 735         }
 736         return 0;
 737 }
 738
 739 int __devinit irqbalance_disable(char *str)
 740 {
 741         irqbalance_disabled = 1;
 742         return 1;
 743 }
 744
 745 __setup("noirqbalance", irqbalance_disable);
 746
 747 late_initcall(balanced_irq_init);
 748 #endif /* CONFIG_IRQBALANCE */
 749 #endif /* CONFIG_SMP */
 750
 751 #ifndef CONFIG_SMP
 752 void fastcall send_IPI_self(int vector)
 753 {
 754         unsigned int cfg;
 755
 756         /*
 757          * Wait for idle.
 758          */
 759         apic_wait_icr_idle();
 760         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 761         /*
 762          * Send the IPI. The write to APIC_ICR fires this off.
 763          */
 764         apic_write_around(APIC_ICR, cfg);
 765 }
 766 #endif /* !CONFIG_SMP */
 767
 768
 769 /*
 770  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 771  * specific CPU-side IRQs.
 772  */
 773
 774 #define MAX_PIRQS 8
 775 static int pirq_entries [MAX_PIRQS];
 776 static int pirqs_enabled;
 777 int skip_ioapic_setup;
 778
 779 static int __init ioapic_setup(char *str)
 780 {
 781         skip_ioapic_setup = 1;
 782         return 1;
 783 }
 784
 785 __setup("noapic", ioapic_setup);
 786
 787 static int __init ioapic_pirq_setup(char *str)
 788 {
 789         int i, max;
 790         int ints[MAX_PIRQS+1];
 791
 792         get_options(str, ARRAY_SIZE(ints), ints);
 793
 794         for (i = 0; i < MAX_PIRQS; i++)
 795                 pirq_entries[i] = -1;
 796
 797         pirqs_enabled = 1;
 798         apic_printk(APIC_VERBOSE, KERN_INFO
 799                         "PIRQ redirection, working around broken MP-BIOS.\n");
 800         max = MAX_PIRQS;
 801         if (ints[0] < MAX_PIRQS)
 802                 max = ints[0];
 803
 804         for (i = 0; i < max; i++) {
 805                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 806                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 807                 /*
 808                  * PIRQs are mapped upside down, usually.
 809                  */
 810                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 811         }
 812         return 1;
 813 }
 814
 815 __setup("pirq=", ioapic_pirq_setup);
 816
 817 /*
 818  * Find the IRQ entry number of a certain pin.
 819  */
 820 static int find_irq_entry(int apic, int pin, int type)
 821 {
 822         int i;
 823
 824         for (i = 0; i < mp_irq_entries; i++)
 825                 if (mp_irqs[i].mpc_irqtype == type &&
 826                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 827                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 828                     mp_irqs[i].mpc_dstirq == pin)
 829                         return i;
 830
 831         return -1;
 832 }
 833
 834 /*
 835  * Find the pin to which IRQ[irq] (ISA) is connected
 836  */
 837 static int __init find_isa_irq_pin(int irq, int type)
 838 {
 839         int i;
 840
 841         for (i = 0; i < mp_irq_entries; i++) {
 842                 int lbus = mp_irqs[i].mpc_srcbus;
 843
 844                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 845                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 846                      mp_bus_id_to_type[lbus] == MP_BUS_MCA
 847                     ) &&
 848                     (mp_irqs[i].mpc_irqtype == type) &&
 849                     (mp_irqs[i].mpc_srcbusirq == irq))
 850
 851                         return mp_irqs[i].mpc_dstirq;
 852         }
 853         return -1;
 854 }
 855
 856 static int __init find_isa_irq_apic(int irq, int type)
 857 {
 858         int i;
 859
 860         for (i = 0; i < mp_irq_entries; i++) {
 861                 int lbus = mp_irqs[i].mpc_srcbus;
 862
 863                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 864                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 865                      mp_bus_id_to_type[lbus] == MP_BUS_MCA
 866                     ) &&
 867                     (mp_irqs[i].mpc_irqtype == type) &&
 868                     (mp_irqs[i].mpc_srcbusirq == irq))
 869                         break;
 870         }
 871         if (i < mp_irq_entries) {
 872                 int apic;
 873                 for(apic = 0; apic < nr_ioapics; apic++) {
 874                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 875                                 return apic;
 876                 }
 877         }
 878
 879         return -1;
 880 }
 881
 882 /*
 883  * Find a specific PCI IRQ entry.
 884  * Not an __init, possibly needed by modules
 885  */
 886 static int pin_2_irq(int idx, int apic, int pin);
 887
 888 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 889 {
 890         int apic, i, best_guess = -1;
 891
 892         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 893                 "slot:%d, pin:%d.\n", bus, slot, pin);
 894         if (mp_bus_id_to_pci_bus[bus] == -1) {
 895                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 896                 return -1;
 897         }
 898         for (i = 0; i < mp_irq_entries; i++) {
 899                 int lbus = mp_irqs[i].mpc_srcbus;
 900
 901                 for (apic = 0; apic < nr_ioapics; apic++)
 902                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 903                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 904                                 break;
 905
 906                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 907                     !mp_irqs[i].mpc_irqtype &&
 908                     (bus == lbus) &&
 909                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 910                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 911
 912                         if (!(apic || IO_APIC_IRQ(irq)))
 913                                 continue;
 914
 915                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 916                                 return irq;
 917                         /*
 918                          * Use the first all-but-pin matching entry as a
 919                          * best-guess fuzzy result for broken mptables.
 920                          */
 921                         if (best_guess < 0)
 922                                 best_guess = irq;
 923                 }
 924         }
 925         return best_guess;
 926 }
 927 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 928
 929 /*
 930  * This function currently is only a helper for the i386 smp boot process where
 931  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 932  * so mask in all cases should simply be TARGET_CPUS
 933  */
 934 #ifdef CONFIG_SMP
 935 void __init setup_ioapic_dest(void)
 936 {
 937         int pin, ioapic, irq, irq_entry;
 938
 939         if (skip_ioapic_setup == 1)
 940                 return;
 941
 942         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 943                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 944                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 945                         if (irq_entry == -1)
 946                                 continue;
 947                         irq = pin_2_irq(irq_entry, ioapic, pin);
 948                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 949                 }
 950
 951         }
 952 }
 953 #endif
 954
 955 /*
 956  * EISA Edge/Level control register, ELCR
 957  */
 958 static int EISA_ELCR(unsigned int irq)
 959 {
 960         if (irq < 16) {
 961                 unsigned int port = 0x4d0 + (irq >> 3);
 962                 return (inb(port) >> (irq & 7)) & 1;
 963         }
 964         apic_printk(APIC_VERBOSE, KERN_INFO
 965                         "Broken MPtable reports ISA irq %d\n", irq);
 966         return 0;
 967 }
 968
 969 /* EISA interrupts are always polarity zero and can be edge or level
 970  * trigger depending on the ELCR value.  If an interrupt is listed as
 971  * EISA conforming in the MP table, that means its trigger type must
 972  * be read in from the ELCR */
 973
 974 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 975 #define default_EISA_polarity(idx)      (0)
 976
 977 /* ISA interrupts are always polarity zero edge triggered,
 978  * when listed as conforming in the MP table. */
 979
 980 #define default_ISA_trigger(idx)        (0)
 981 #define default_ISA_polarity(idx)       (0)
 982
 983 /* PCI interrupts are always polarity one level triggered,
 984  * when listed as conforming in the MP table. */
 985
 986 #define default_PCI_trigger(idx)        (1)
 987 #define default_PCI_polarity(idx)       (1)
 988
 989 /* MCA interrupts are always polarity zero level triggered,
 990  * when listed as conforming in the MP table. */
 991
 992 #define default_MCA_trigger(idx)        (1)
 993 #define default_MCA_polarity(idx)       (0)
 994
 995 static int __init MPBIOS_polarity(int idx)
 996 {
 997         int bus = mp_irqs[idx].mpc_srcbus;
 998         int polarity;
 999
1000         /*
1001          * Determine IRQ line polarity (high active or low active):
1002          */
1003         switch (mp_irqs[idx].mpc_irqflag & 3)
1004         {
1005                 case 0: /* conforms, ie. bus-type dependent polarity */
1006                 {
1007                         switch (mp_bus_id_to_type[bus])
1008                         {
1009                                 case MP_BUS_ISA: /* ISA pin */
1010                                 {
1011                                         polarity = default_ISA_polarity(idx);
1012                                         break;
1013                                 }
1014                                 case MP_BUS_EISA: /* EISA pin */
1015                                 {
1016                                         polarity = default_EISA_polarity(idx);
1017                                         break;
1018                                 }
1019                                 case MP_BUS_PCI: /* PCI pin */
1020                                 {
1021                                         polarity = default_PCI_polarity(idx);
1022                                         break;
1023                                 }
1024                                 case MP_BUS_MCA: /* MCA pin */
1025                                 {
1026                                         polarity = default_MCA_polarity(idx);
1027                                         break;
1028                                 }
1029                                 default:
1030                                 {
1031                                         printk(KERN_WARNING "broken BIOS!!\n");
1032                                         polarity = 1;
1033                                         break;
1034                                 }
1035                         }
1036                         break;
1037                 }
1038                 case 1: /* high active */
1039                 {
1040                         polarity = 0;
1041                         break;
1042                 }
1043                 case 2: /* reserved */
1044                 {
1045                         printk(KERN_WARNING "broken BIOS!!\n");
1046                         polarity = 1;
1047                         break;
1048                 }
1049                 case 3: /* low active */
1050                 {
1051                         polarity = 1;
1052                         break;
1053                 }
1054                 default: /* invalid */
1055                 {
1056                         printk(KERN_WARNING "broken BIOS!!\n");
1057                         polarity = 1;
1058                         break;
1059                 }
1060         }
1061         return polarity;
1062 }
1063
1064 static int MPBIOS_trigger(int idx)
1065 {
1066         int bus = mp_irqs[idx].mpc_srcbus;
1067         int trigger;
1068
1069         /*
1070          * Determine IRQ trigger mode (edge or level sensitive):
1071          */
1072         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1073         {
1074                 case 0: /* conforms, ie. bus-type dependent */
1075                 {
1076                         switch (mp_bus_id_to_type[bus])
1077                         {
1078                                 case MP_BUS_ISA: /* ISA pin */
1079                                 {
1080                                         trigger = default_ISA_trigger(idx);
1081                                         break;
1082                                 }
1083                                 case MP_BUS_EISA: /* EISA pin */
1084                                 {
1085                                         trigger = default_EISA_trigger(idx);
1086                                         break;
1087                                 }
1088                                 case MP_BUS_PCI: /* PCI pin */
1089                                 {
1090                                         trigger = default_PCI_trigger(idx);
1091                                         break;
1092                                 }
1093                                 case MP_BUS_MCA: /* MCA pin */
1094                                 {
1095                                         trigger = default_MCA_trigger(idx);
1096                                         break;
1097                                 }
1098                                 default:
1099                                 {
1100                                         printk(KERN_WARNING "broken BIOS!!\n");
1101                                         trigger = 1;
1102                                         break;
1103                                 }
1104                         }
1105                         break;
1106                 }
1107                 case 1: /* edge */
1108                 {
1109                         trigger = 0;
1110                         break;
1111                 }
1112                 case 2: /* reserved */
1113                 {
1114                         printk(KERN_WARNING "broken BIOS!!\n");
1115                         trigger = 1;
1116                         break;
1117                 }
1118                 case 3: /* level */
1119                 {
1120                         trigger = 1;
1121                         break;
1122                 }
1123                 default: /* invalid */
1124                 {
1125                         printk(KERN_WARNING "broken BIOS!!\n");
1126                         trigger = 0;
1127                         break;
1128                 }
1129         }
1130         return trigger;
1131 }
1132
1133 static inline int irq_polarity(int idx)
1134 {
1135         return MPBIOS_polarity(idx);
1136 }
1137
1138 static inline int irq_trigger(int idx)
1139 {
1140         return MPBIOS_trigger(idx);
1141 }
1142
1143 static int pin_2_irq(int idx, int apic, int pin)
1144 {
1145         int irq, i;
1146         int bus = mp_irqs[idx].mpc_srcbus;
1147
1148         /*
1149          * Debugging check, we are in big trouble if this message pops up!
1150          */
1151         if (mp_irqs[idx].mpc_dstirq != pin)
1152                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1153
1154         switch (mp_bus_id_to_type[bus])
1155         {
1156                 case MP_BUS_ISA: /* ISA pin */
1157                 case MP_BUS_EISA:
1158                 case MP_BUS_MCA:
1159                 {
1160                         irq = mp_irqs[idx].mpc_srcbusirq;
1161                         break;
1162                 }
1163                 case MP_BUS_PCI: /* PCI pin */
1164                 {
1165                         /*
1166                          * PCI IRQs are mapped in order
1167                          */
1168                         i = irq = 0;
1169                         while (i < apic)
1170                                 irq += nr_ioapic_registers[i++];
1171                         irq += pin;
1172
1173                         /*
1174                          * For MPS mode, so far only needed by ES7000 platform
1175                          */
1176                         if (ioapic_renumber_irq)
1177                                 irq = ioapic_renumber_irq(apic, irq);
1178
1179                         break;
1180                 }
1181                 default:
1182                 {
1183                         printk(KERN_ERR "unknown bus type %d.\n",bus);
1184                         irq = 0;
1185                         break;
1186                 }
1187         }
1188
1189         /*
1190          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1191          */
1192         if ((pin >= 16) && (pin <= 23)) {
1193                 if (pirq_entries[pin-16] != -1) {
1194                         if (!pirq_entries[pin-16]) {
1195                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1196                                                 "disabling PIRQ%d\n", pin-16);
1197                         } else {
1198                                 irq = pirq_entries[pin-16];
1199                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1200                                                 "using PIRQ%d -> IRQ %d\n",
1201                                                 pin-16, irq);
1202                         }
1203                 }
1204         }
1205         return irq;
1206 }
1207
1208 static inline int IO_APIC_irq_trigger(int irq)
1209 {
1210         int apic, idx, pin;
1211
1212         for (apic = 0; apic < nr_ioapics; apic++) {
1213                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1214                         idx = find_irq_entry(apic,pin,mp_INT);
1215                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1216                                 return irq_trigger(idx);
1217                 }
1218         }
1219         /*
1220          * nonexistent IRQs are edge default
1221          */
1222         return 0;
1223 }
1224
1225 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1226 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1227
1228 static int __assign_irq_vector(int irq)
1229 {
1230         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1231         int vector, offset, i;
1232
1233         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1234
1235         if (irq_vector[irq] > 0)
1236                 return irq_vector[irq];
1237
1238         vector = current_vector;
1239         offset = current_offset;
1240 next:
1241         vector += 8;
1242         if (vector >= FIRST_SYSTEM_VECTOR) {
1243                 offset = (offset + 1) % 8;
1244                 vector = FIRST_DEVICE_VECTOR + offset;
1245         }
1246         if (vector == current_vector)
1247                 return -ENOSPC;
1248         if (vector == SYSCALL_VECTOR)
1249                 goto next;
1250         for (i = 0; i < NR_IRQ_VECTORS; i++)
1251                 if (irq_vector[i] == vector)
1252                         goto next;
1253
1254         current_vector = vector;
1255         current_offset = offset;
1256         irq_vector[irq] = vector;
1257
1258         return vector;
1259 }
1260
1261 static int assign_irq_vector(int irq)
1262 {
1263         unsigned long flags;
1264         int vector;
1265
1266         spin_lock_irqsave(&vector_lock, flags);
1267         vector = __assign_irq_vector(irq);
1268         spin_unlock_irqrestore(&vector_lock, flags);
1269
1270         return vector;
1271 }
1272 static struct irq_chip ioapic_chip;
1273
1274 #define IOAPIC_AUTO     -1
1275 #define IOAPIC_EDGE     0
1276 #define IOAPIC_LEVEL    1
1277
1278 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1279 {
1280         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1281                         trigger == IOAPIC_LEVEL)
1282                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1283                                          handle_fasteoi_irq, "fasteoi");
1284         else
1285                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1286                                          handle_edge_irq, "edge");
1287         set_intr_gate(vector, interrupt[irq]);
1288 }
1289
1290 static void __init setup_IO_APIC_irqs(void)
1291 {
1292         struct IO_APIC_route_entry entry;
1293         int apic, pin, idx, irq, first_notcon = 1, vector;
1294         unsigned long flags;
1295
1296         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1297
1298         for (apic = 0; apic < nr_ioapics; apic++) {
1299         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1300
1301                 /*
1302                  * add it to the IO-APIC irq-routing table:
1303                  */
1304                 memset(&entry,0,sizeof(entry));
1305
1306                 entry.delivery_mode = INT_DELIVERY_MODE;
1307                 entry.dest_mode = INT_DEST_MODE;
1308                 entry.mask = 0;                         /* enable IRQ */
1309                 entry.dest.logical.logical_dest =
1310                                         cpu_mask_to_apicid(TARGET_CPUS);
1311
1312                 idx = find_irq_entry(apic,pin,mp_INT);
1313                 if (idx == -1) {
1314                         if (first_notcon) {
1315                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1316                                                 " IO-APIC (apicid-pin) %d-%d",
1317                                                 mp_ioapics[apic].mpc_apicid,
1318                                                 pin);
1319                                 first_notcon = 0;
1320                         } else
1321                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1322                                         mp_ioapics[apic].mpc_apicid, pin);
1323                         continue;
1324                 }
1325
1326                 entry.trigger = irq_trigger(idx);
1327                 entry.polarity = irq_polarity(idx);
1328
1329                 if (irq_trigger(idx)) {
1330                         entry.trigger = 1;
1331                         entry.mask = 1;
1332                 }
1333
1334                 irq = pin_2_irq(idx, apic, pin);
1335                 /*
1336                  * skip adding the timer int on secondary nodes, which causes
1337                  * a small but painful rift in the time-space continuum
1338                  */
1339                 if (multi_timer_check(apic, irq))
1340                         continue;
1341                 else
1342                         add_pin_to_irq(irq, apic, pin);
1343
1344                 if (!apic && !IO_APIC_IRQ(irq))
1345                         continue;
1346
1347                 if (IO_APIC_IRQ(irq)) {
1348                         vector = assign_irq_vector(irq);
1349                         entry.vector = vector;
1350                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1351
1352                         if (!apic && (irq < 16))
1353                                 disable_8259A_irq(irq);
1354                 }
1355                 spin_lock_irqsave(&ioapic_lock, flags);
1356                 __ioapic_write_entry(apic, pin, entry);
1357                 spin_unlock_irqrestore(&ioapic_lock, flags);
1358         }
1359         }
1360
1361         if (!first_notcon)
1362                 apic_printk(APIC_VERBOSE, " not connected.\n");
1363 }
1364
1365 /*
1366  * Set up the 8259A-master output pin:
1367  */
1368 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1369 {
1370         struct IO_APIC_route_entry entry;
1371
1372         memset(&entry,0,sizeof(entry));
1373
1374         disable_8259A_irq(0);
1375
1376         /* mask LVT0 */
1377         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1378
1379         /*
1380          * We use logical delivery to get the timer IRQ
1381          * to the first CPU.
1382          */
1383         entry.dest_mode = INT_DEST_MODE;
1384         entry.mask = 0;                                 /* unmask IRQ now */
1385         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1386         entry.delivery_mode = INT_DELIVERY_MODE;
1387         entry.polarity = 0;
1388         entry.trigger = 0;
1389         entry.vector = vector;
1390
1391         /*
1392          * The timer IRQ doesn't have to know that behind the
1393          * scene we have a 8259A-master in AEOI mode ...
1394          */
1395         irq_desc[0].chip = &ioapic_chip;
1396         set_irq_handler(0, handle_edge_irq);
1397
1398         /*
1399          * Add it to the IO-APIC irq-routing table:
1400          */
1401         ioapic_write_entry(apic, pin, entry);
1402
1403         enable_8259A_irq(0);
1404 }
1405
1406 void __init print_IO_APIC(void)
1407 {
1408         int apic, i;
1409         union IO_APIC_reg_00 reg_00;
1410         union IO_APIC_reg_01 reg_01;
1411         union IO_APIC_reg_02 reg_02;
1412         union IO_APIC_reg_03 reg_03;
1413         unsigned long flags;
1414
1415         if (apic_verbosity == APIC_QUIET)
1416                 return;
1417
1418         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1419         for (i = 0; i < nr_ioapics; i++)
1420                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1421                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1422
1423         /*
1424          * We are a bit conservative about what we expect.  We have to
1425          * know about every hardware change ASAP.
1426          */
1427         printk(KERN_INFO "testing the IO APIC.......................\n");
1428
1429         for (apic = 0; apic < nr_ioapics; apic++) {
1430
1431         spin_lock_irqsave(&ioapic_lock, flags);
1432         reg_00.raw = io_apic_read(apic, 0);
1433         reg_01.raw = io_apic_read(apic, 1);
1434         if (reg_01.bits.version >= 0x10)
1435                 reg_02.raw = io_apic_read(apic, 2);
1436         if (reg_01.bits.version >= 0x20)
1437                 reg_03.raw = io_apic_read(apic, 3);
1438         spin_unlock_irqrestore(&ioapic_lock, flags);
1439
1440         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1441         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1442         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1443         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1444         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1445
1446         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1447         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1448
1449         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1450         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1451
1452         /*
1453          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1454          * but the value of reg_02 is read as the previous read register
1455          * value, so ignore it if reg_02 == reg_01.
1456          */
1457         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1458                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1459                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1460         }
1461
1462         /*
1463          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1464          * or reg_03, but the value of reg_0[23] is read as the previous read
1465          * register value, so ignore it if reg_03 == reg_0[12].
1466          */
1467         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1468             reg_03.raw != reg_01.raw) {
1469                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1470                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1471         }
1472
1473         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1474
1475         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1476                           " Stat Dest Deli Vect:   \n");
1477
1478         for (i = 0; i <= reg_01.bits.entries; i++) {
1479                 struct IO_APIC_route_entry entry;
1480
1481                 entry = ioapic_read_entry(apic, i);
1482
1483                 printk(KERN_DEBUG " %02x %03X %02X  ",
1484                         i,
1485                         entry.dest.logical.logical_dest,
1486                         entry.dest.physical.physical_dest
1487                 );
1488
1489                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1490                         entry.mask,
1491                         entry.trigger,
1492                         entry.irr,
1493                         entry.polarity,
1494                         entry.delivery_status,
1495                         entry.dest_mode,
1496                         entry.delivery_mode,
1497                         entry.vector
1498                 );
1499         }
1500         }
1501         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1502         for (i = 0; i < NR_IRQS; i++) {
1503                 struct irq_pin_list *entry = irq_2_pin + i;
1504                 if (entry->pin < 0)
1505                         continue;
1506                 printk(KERN_DEBUG "IRQ%d ", i);
1507                 for (;;) {
1508                         printk("-> %d:%d", entry->apic, entry->pin);
1509                         if (!entry->next)
1510                                 break;
1511                         entry = irq_2_pin + entry->next;
1512                 }
1513                 printk("\n");
1514         }
1515
1516         printk(KERN_INFO ".................................... done.\n");
1517
1518         return;
1519 }
1520
1521 #if 0
1522
1523 static void print_APIC_bitfield (int base)
1524 {
1525         unsigned int v;
1526         int i, j;
1527
1528         if (apic_verbosity == APIC_QUIET)
1529                 return;
1530
1531         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1532         for (i = 0; i < 8; i++) {
1533                 v = apic_read(base + i*0x10);
1534                 for (j = 0; j < 32; j++) {
1535                         if (v & (1<<j))
1536                                 printk("1");
1537                         else
1538                                 printk("0");
1539                 }
1540                 printk("\n");
1541         }
1542 }
1543
1544 void /*__init*/ print_local_APIC(void * dummy)
1545 {
1546         unsigned int v, ver, maxlvt;
1547
1548         if (apic_verbosity == APIC_QUIET)
1549                 return;
1550
1551         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1552                 smp_processor_id(), hard_smp_processor_id());
1553         v = apic_read(APIC_ID);
1554         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1555         v = apic_read(APIC_LVR);
1556         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1557         ver = GET_APIC_VERSION(v);
1558         maxlvt = lapic_get_maxlvt();
1559
1560         v = apic_read(APIC_TASKPRI);
1561         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1562
1563         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1564                 v = apic_read(APIC_ARBPRI);
1565                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1566                         v & APIC_ARBPRI_MASK);
1567                 v = apic_read(APIC_PROCPRI);
1568                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1569         }
1570
1571         v = apic_read(APIC_EOI);
1572         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1573         v = apic_read(APIC_RRR);
1574         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1575         v = apic_read(APIC_LDR);
1576         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1577         v = apic_read(APIC_DFR);
1578         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1579         v = apic_read(APIC_SPIV);
1580         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1581
1582         printk(KERN_DEBUG "... APIC ISR field:\n");
1583         print_APIC_bitfield(APIC_ISR);
1584         printk(KERN_DEBUG "... APIC TMR field:\n");
1585         print_APIC_bitfield(APIC_TMR);
1586         printk(KERN_DEBUG "... APIC IRR field:\n");
1587         print_APIC_bitfield(APIC_IRR);
1588
1589         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1590                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1591                         apic_write(APIC_ESR, 0);
1592                 v = apic_read(APIC_ESR);
1593                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1594         }
1595
1596         v = apic_read(APIC_ICR);
1597         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1598         v = apic_read(APIC_ICR2);
1599         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1600
1601         v = apic_read(APIC_LVTT);
1602         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1603
1604         if (maxlvt > 3) {                       /* PC is LVT#4. */
1605                 v = apic_read(APIC_LVTPC);
1606                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1607         }
1608         v = apic_read(APIC_LVT0);
1609         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1610         v = apic_read(APIC_LVT1);
1611         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1612
1613         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1614                 v = apic_read(APIC_LVTERR);
1615                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1616         }
1617
1618         v = apic_read(APIC_TMICT);
1619         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1620         v = apic_read(APIC_TMCCT);
1621         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1622         v = apic_read(APIC_TDCR);
1623         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1624         printk("\n");
1625 }
1626
1627 void print_all_local_APICs (void)
1628 {
1629         on_each_cpu(print_local_APIC, NULL, 1, 1);
1630 }
1631
1632 void /*__init*/ print_PIC(void)
1633 {
1634         unsigned int v;
1635         unsigned long flags;
1636
1637         if (apic_verbosity == APIC_QUIET)
1638                 return;
1639
1640         printk(KERN_DEBUG "\nprinting PIC contents\n");
1641
1642         spin_lock_irqsave(&i8259A_lock, flags);
1643
1644         v = inb(0xa1) << 8 | inb(0x21);
1645         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1646
1647         v = inb(0xa0) << 8 | inb(0x20);
1648         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1649
1650         outb(0x0b,0xa0);
1651         outb(0x0b,0x20);
1652         v = inb(0xa0) << 8 | inb(0x20);
1653         outb(0x0a,0xa0);
1654         outb(0x0a,0x20);
1655
1656         spin_unlock_irqrestore(&i8259A_lock, flags);
1657
1658         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1659
1660         v = inb(0x4d1) << 8 | inb(0x4d0);
1661         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1662 }
1663
1664 #endif  /*  0  */
1665
1666 static void __init enable_IO_APIC(void)
1667 {
1668         union IO_APIC_reg_01 reg_01;
1669         int i8259_apic, i8259_pin;
1670         int i, apic;
1671         unsigned long flags;
1672
1673         for (i = 0; i < PIN_MAP_SIZE; i++) {
1674                 irq_2_pin[i].pin = -1;
1675                 irq_2_pin[i].next = 0;
1676         }
1677         if (!pirqs_enabled)
1678                 for (i = 0; i < MAX_PIRQS; i++)
1679                         pirq_entries[i] = -1;
1680
1681         /*
1682          * The number of IO-APIC IRQ registers (== #pins):
1683          */
1684         for (apic = 0; apic < nr_ioapics; apic++) {
1685                 spin_lock_irqsave(&ioapic_lock, flags);
1686                 reg_01.raw = io_apic_read(apic, 1);
1687                 spin_unlock_irqrestore(&ioapic_lock, flags);
1688                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1689         }
1690         for(apic = 0; apic < nr_ioapics; apic++) {
1691                 int pin;
1692                 /* See if any of the pins is in ExtINT mode */
1693                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1694                         struct IO_APIC_route_entry entry;
1695                         entry = ioapic_read_entry(apic, pin);
1696
1697
1698                         /* If the interrupt line is enabled and in ExtInt mode
1699                          * I have found the pin where the i8259 is connected.
1700                          */
1701                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1702                                 ioapic_i8259.apic = apic;
1703                                 ioapic_i8259.pin  = pin;
1704                                 goto found_i8259;
1705                         }
1706                 }
1707         }
1708  found_i8259:
1709         /* Look to see what if the MP table has reported the ExtINT */
1710         /* If we could not find the appropriate pin by looking at the ioapic
1711          * the i8259 probably is not connected the ioapic but give the
1712          * mptable a chance anyway.
1713          */
1714         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1715         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1716         /* Trust the MP table if nothing is setup in the hardware */
1717         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1718                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1719                 ioapic_i8259.pin  = i8259_pin;
1720                 ioapic_i8259.apic = i8259_apic;
1721         }
1722         /* Complain if the MP table and the hardware disagree */
1723         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1724                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1725         {
1726                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1727         }
1728
1729         /*
1730          * Do not trust the IO-APIC being empty at bootup
1731          */
1732         clear_IO_APIC();
1733 }
1734
1735 /*
1736  * Not an __init, needed by the reboot code
1737  */
1738 void disable_IO_APIC(void)
1739 {
1740         /*
1741          * Clear the IO-APIC before rebooting:
1742          */
1743         clear_IO_APIC();
1744
1745         /*
1746          * If the i8259 is routed through an IOAPIC
1747          * Put that IOAPIC in virtual wire mode
1748          * so legacy interrupts can be delivered.
1749          */
1750         if (ioapic_i8259.pin != -1) {
1751                 struct IO_APIC_route_entry entry;
1752
1753                 memset(&entry, 0, sizeof(entry));
1754                 entry.mask            = 0; /* Enabled */
1755                 entry.trigger         = 0; /* Edge */
1756                 entry.irr             = 0;
1757                 entry.polarity        = 0; /* High */
1758                 entry.delivery_status = 0;
1759                 entry.dest_mode       = 0; /* Physical */
1760                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1761                 entry.vector          = 0;
1762                 entry.dest.physical.physical_dest =
1763                                         GET_APIC_ID(apic_read(APIC_ID));
1764
1765                 /*
1766                  * Add it to the IO-APIC irq-routing table:
1767                  */
1768                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1769         }
1770         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1771 }
1772
1773 /*
1774  * function to set the IO-APIC physical IDs based on the
1775  * values stored in the MPC table.
1776  *
1777  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1778  */
1779
1780 #ifndef CONFIG_X86_NUMAQ
1781 static void __init setup_ioapic_ids_from_mpc(void)
1782 {
1783         union IO_APIC_reg_00 reg_00;
1784         physid_mask_t phys_id_present_map;
1785         int apic;
1786         int i;
1787         unsigned char old_id;
1788         unsigned long flags;
1789
1790         /*
1791          * Don't check I/O APIC IDs for xAPIC systems.  They have
1792          * no meaning without the serial APIC bus.
1793          */
1794         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1795                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1796                 return;
1797         /*
1798          * This is broken; anything with a real cpu count has to
1799          * circumvent this idiocy regardless.
1800          */
1801         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1802
1803         /*
1804          * Set the IOAPIC ID to the value stored in the MPC table.
1805          */
1806         for (apic = 0; apic < nr_ioapics; apic++) {
1807
1808                 /* Read the register 0 value */
1809                 spin_lock_irqsave(&ioapic_lock, flags);
1810                 reg_00.raw = io_apic_read(apic, 0);
1811                 spin_unlock_irqrestore(&ioapic_lock, flags);
1812
1813                 old_id = mp_ioapics[apic].mpc_apicid;
1814
1815                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1816                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1817                                 apic, mp_ioapics[apic].mpc_apicid);
1818                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1819                                 reg_00.bits.ID);
1820                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1821                 }
1822
1823                 /*
1824                  * Sanity check, is the ID really free? Every APIC in a
1825                  * system must have a unique ID or we get lots of nice
1826                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1827                  */
1828                 if (check_apicid_used(phys_id_present_map,
1829                                         mp_ioapics[apic].mpc_apicid)) {
1830                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1831                                 apic, mp_ioapics[apic].mpc_apicid);
1832                         for (i = 0; i < get_physical_broadcast(); i++)
1833                                 if (!physid_isset(i, phys_id_present_map))
1834                                         break;
1835                         if (i >= get_physical_broadcast())
1836                                 panic("Max APIC ID exceeded!\n");
1837                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1838                                 i);
1839                         physid_set(i, phys_id_present_map);
1840                         mp_ioapics[apic].mpc_apicid = i;
1841                 } else {
1842                         physid_mask_t tmp;
1843                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1844                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1845                                         "phys_id_present_map\n",
1846                                         mp_ioapics[apic].mpc_apicid);
1847                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1848                 }
1849
1850
1851                 /*
1852                  * We need to adjust the IRQ routing table
1853                  * if the ID changed.
1854                  */
1855                 if (old_id != mp_ioapics[apic].mpc_apicid)
1856                         for (i = 0; i < mp_irq_entries; i++)
1857                                 if (mp_irqs[i].mpc_dstapic == old_id)
1858                                         mp_irqs[i].mpc_dstapic
1859                                                 = mp_ioapics[apic].mpc_apicid;
1860
1861                 /*
1862                  * Read the right value from the MPC table and
1863                  * write it into the ID register.
1864                  */
1865                 apic_printk(APIC_VERBOSE, KERN_INFO
1866                         "...changing IO-APIC physical APIC ID to %d ...",
1867                         mp_ioapics[apic].mpc_apicid);
1868
1869                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1870                 spin_lock_irqsave(&ioapic_lock, flags);
1871                 io_apic_write(apic, 0, reg_00.raw);
1872                 spin_unlock_irqrestore(&ioapic_lock, flags);
1873
1874                 /*
1875                  * Sanity check
1876                  */
1877                 spin_lock_irqsave(&ioapic_lock, flags);
1878                 reg_00.raw = io_apic_read(apic, 0);
1879                 spin_unlock_irqrestore(&ioapic_lock, flags);
1880                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1881                         printk("could not set ID!\n");
1882                 else
1883                         apic_printk(APIC_VERBOSE, " ok.\n");
1884         }
1885 }
1886 #else
1887 static void __init setup_ioapic_ids_from_mpc(void) { }
1888 #endif
1889
1890 int no_timer_check __initdata;
1891
1892 static int __init notimercheck(char *s)
1893 {
1894         no_timer_check = 1;
1895         return 1;
1896 }
1897 __setup("no_timer_check", notimercheck);
1898
1899 /*
1900  * There is a nasty bug in some older SMP boards, their mptable lies
1901  * about the timer IRQ. We do the following to work around the situation:
1902  *
1903  *      - timer IRQ defaults to IO-APIC IRQ
1904  *      - if this function detects that timer IRQs are defunct, then we fall
1905  *        back to ISA timer IRQs
1906  */
1907 int __init timer_irq_works(void)
1908 {
1909         unsigned long t1 = jiffies;
1910
1911         if (no_timer_check)
1912                 return 1;
1913
1914         local_irq_enable();
1915         /* Let ten ticks pass... */
1916         mdelay((10 * 1000) / HZ);
1917
1918         /*
1919          * Expect a few ticks at least, to be sure some possible
1920          * glue logic does not lock up after one or two first
1921          * ticks in a non-ExtINT mode.  Also the local APIC
1922          * might have cached one ExtINT interrupt.  Finally, at
1923          * least one tick may be lost due to delays.
1924          */
1925         if (jiffies - t1 > 4)
1926                 return 1;
1927
1928         return 0;
1929 }
1930
1931 /*
1932  * In the SMP+IOAPIC case it might happen that there are an unspecified
1933  * number of pending IRQ events unhandled. These cases are very rare,
1934  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1935  * better to do it this way as thus we do not have to be aware of
1936  * 'pending' interrupts in the IRQ path, except at this point.
1937  */
1938 /*
1939  * Edge triggered needs to resend any interrupt
1940  * that was delayed but this is now handled in the device
1941  * independent code.
1942  */
1943
1944 /*
1945  * Startup quirk:
1946  *
1947  * Starting up a edge-triggered IO-APIC interrupt is
1948  * nasty - we need to make sure that we get the edge.
1949  * If it is already asserted for some reason, we need
1950  * return 1 to indicate that is was pending.
1951  *
1952  * This is not complete - we should be able to fake
1953  * an edge even if it isn't on the 8259A...
1954  *
1955  * (We do this for level-triggered IRQs too - it cannot hurt.)
1956  */
1957 static unsigned int startup_ioapic_irq(unsigned int irq)
1958 {
1959         int was_pending = 0;
1960         unsigned long flags;
1961
1962         spin_lock_irqsave(&ioapic_lock, flags);
1963         if (irq < 16) {
1964                 disable_8259A_irq(irq);
1965                 if (i8259A_irq_pending(irq))
1966                         was_pending = 1;
1967         }
1968         __unmask_IO_APIC_irq(irq);
1969         spin_unlock_irqrestore(&ioapic_lock, flags);
1970
1971         return was_pending;
1972 }
1973
1974 static void ack_ioapic_irq(unsigned int irq)
1975 {
1976         move_native_irq(irq);
1977         ack_APIC_irq();
1978 }
1979
1980 static void ack_ioapic_quirk_irq(unsigned int irq)
1981 {
1982         unsigned long v;
1983         int i;
1984
1985         move_native_irq(irq);
1986 /*
1987  * It appears there is an erratum which affects at least version 0x11
1988  * of I/O APIC (that's the 82093AA and cores integrated into various
1989  * chipsets).  Under certain conditions a level-triggered interrupt is
1990  * erroneously delivered as edge-triggered one but the respective IRR
1991  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1992  * message but it will never arrive and further interrupts are blocked
1993  * from the source.  The exact reason is so far unknown, but the
1994  * phenomenon was observed when two consecutive interrupt requests
1995  * from a given source get delivered to the same CPU and the source is
1996  * temporarily disabled in between.
1997  *
1998  * A workaround is to simulate an EOI message manually.  We achieve it
1999  * by setting the trigger mode to edge and then to level when the edge
2000  * trigger mode gets detected in the TMR of a local APIC for a
2001  * level-triggered interrupt.  We mask the source for the time of the
2002  * operation to prevent an edge-triggered interrupt escaping meanwhile.
2003  * The idea is from Manfred Spraul.  --macro
2004  */
2005         i = irq_vector[irq];
2006
2007         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2008
2009         ack_APIC_irq();
2010
2011         if (!(v & (1 << (i & 0x1f)))) {
2012                 atomic_inc(&irq_mis_count);
2013                 spin_lock(&ioapic_lock);
2014                 __mask_and_edge_IO_APIC_irq(irq);
2015                 __unmask_and_level_IO_APIC_irq(irq);
2016                 spin_unlock(&ioapic_lock);
2017         }
2018 }
2019
2020 static int ioapic_retrigger_irq(unsigned int irq)
2021 {
2022         send_IPI_self(irq_vector[irq]);
2023
2024         return 1;
2025 }
2026
2027 static struct irq_chip ioapic_chip __read_mostly = {
2028         .name           = "IO-APIC",
2029         .startup        = startup_ioapic_irq,
2030         .mask           = mask_IO_APIC_irq,
2031         .unmask         = unmask_IO_APIC_irq,
2032         .ack            = ack_ioapic_irq,
2033         .eoi            = ack_ioapic_quirk_irq,
2034 #ifdef CONFIG_SMP
2035         .set_affinity   = set_ioapic_affinity_irq,
2036 #endif
2037         .retrigger      = ioapic_retrigger_irq,
2038 };
2039
2040
2041 static inline void init_IO_APIC_traps(void)
2042 {
2043         int irq;
2044
2045         /*
2046          * NOTE! The local APIC isn't very good at handling
2047          * multiple interrupts at the same interrupt level.
2048          * As the interrupt level is determined by taking the
2049          * vector number and shifting that right by 4, we
2050          * want to spread these out a bit so that they don't
2051          * all fall in the same interrupt level.
2052          *
2053          * Also, we've got to be careful not to trash gate
2054          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2055          */
2056         for (irq = 0; irq < NR_IRQS ; irq++) {
2057                 int tmp = irq;
2058                 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
2059                         /*
2060                          * Hmm.. We don't have an entry for this,
2061                          * so default to an old-fashioned 8259
2062                          * interrupt if we can..
2063                          */
2064                         if (irq < 16)
2065                                 make_8259A_irq(irq);
2066                         else
2067                                 /* Strange. Oh, well.. */
2068                                 irq_desc[irq].chip = &no_irq_chip;
2069                 }
2070         }
2071 }
2072
2073 /*
2074  * The local APIC irq-chip implementation:
2075  */
2076
2077 static void ack_apic(unsigned int irq)
2078 {
2079         ack_APIC_irq();
2080 }
2081
2082 static void mask_lapic_irq (unsigned int irq)
2083 {
2084         unsigned long v;
2085
2086         v = apic_read(APIC_LVT0);
2087         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2088 }
2089
2090 static void unmask_lapic_irq (unsigned int irq)
2091 {
2092         unsigned long v;
2093
2094         v = apic_read(APIC_LVT0);
2095         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2096 }
2097
2098 static struct irq_chip lapic_chip __read_mostly = {
2099         .name           = "local-APIC-edge",
2100         .mask           = mask_lapic_irq,
2101         .unmask         = unmask_lapic_irq,
2102         .eoi            = ack_apic,
2103 };
2104
2105 static void setup_nmi (void)
2106 {
2107         /*
2108          * Dirty trick to enable the NMI watchdog ...
2109          * We put the 8259A master into AEOI mode and
2110          * unmask on all local APICs LVT0 as NMI.
2111          *
2112          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2113          * is from Maciej W. Rozycki - so we do not have to EOI from
2114          * the NMI handler or the timer interrupt.
2115          */
2116         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2117
2118         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2119
2120         apic_printk(APIC_VERBOSE, " done.\n");
2121 }
2122
2123 /*
2124  * This looks a bit hackish but it's about the only one way of sending
2125  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2126  * not support the ExtINT mode, unfortunately.  We need to send these
2127  * cycles as some i82489DX-based boards have glue logic that keeps the
2128  * 8259A interrupt line asserted until INTA.  --macro
2129  */
2130 static inline void unlock_ExtINT_logic(void)
2131 {
2132         int apic, pin, i;
2133         struct IO_APIC_route_entry entry0, entry1;
2134         unsigned char save_control, save_freq_select;
2135
2136         pin  = find_isa_irq_pin(8, mp_INT);
2137         if (pin == -1) {
2138                 WARN_ON_ONCE(1);
2139                 return;
2140         }
2141         apic = find_isa_irq_apic(8, mp_INT);
2142         if (apic == -1) {
2143                 WARN_ON_ONCE(1);
2144                 return;
2145         }
2146
2147         entry0 = ioapic_read_entry(apic, pin);
2148         clear_IO_APIC_pin(apic, pin);
2149
2150         memset(&entry1, 0, sizeof(entry1));
2151
2152         entry1.dest_mode = 0;                   /* physical delivery */
2153         entry1.mask = 0;                        /* unmask IRQ now */
2154         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2155         entry1.delivery_mode = dest_ExtINT;
2156         entry1.polarity = entry0.polarity;
2157         entry1.trigger = 0;
2158         entry1.vector = 0;
2159
2160         ioapic_write_entry(apic, pin, entry1);
2161
2162         save_control = CMOS_READ(RTC_CONTROL);
2163         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2164         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2165                    RTC_FREQ_SELECT);
2166         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2167
2168         i = 100;
2169         while (i-- > 0) {
2170                 mdelay(10);
2171                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2172                         i -= 10;
2173         }
2174
2175         CMOS_WRITE(save_control, RTC_CONTROL);
2176         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2177         clear_IO_APIC_pin(apic, pin);
2178
2179         ioapic_write_entry(apic, pin, entry0);
2180 }
2181
2182 int timer_uses_ioapic_pin_0;
2183
2184 /*
2185  * This code may look a bit paranoid, but it's supposed to cooperate with
2186  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2187  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2188  * fanatically on his truly buggy board.
2189  */
2190 static inline void __init check_timer(void)
2191 {
2192         int apic1, pin1, apic2, pin2;
2193         int vector;
2194
2195         /*
2196          * get/set the timer IRQ vector:
2197          */
2198         disable_8259A_irq(0);
2199         vector = assign_irq_vector(0);
2200         set_intr_gate(vector, interrupt[0]);
2201
2202         /*
2203          * Subtle, code in do_timer_interrupt() expects an AEOI
2204          * mode for the 8259A whenever interrupts are routed
2205          * through I/O APICs.  Also IRQ0 has to be enabled in
2206          * the 8259A which implies the virtual wire has to be
2207          * disabled in the local APIC.
2208          */
2209         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2210         init_8259A(1);
2211         timer_ack = 1;
2212         if (timer_over_8254 > 0)
2213                 enable_8259A_irq(0);
2214
2215         pin1  = find_isa_irq_pin(0, mp_INT);
2216         apic1 = find_isa_irq_apic(0, mp_INT);
2217         pin2  = ioapic_i8259.pin;
2218         apic2 = ioapic_i8259.apic;
2219
2220         if (pin1 == 0)
2221                 timer_uses_ioapic_pin_0 = 1;
2222
2223         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2224                 vector, apic1, pin1, apic2, pin2);
2225
2226         if (pin1 != -1) {
2227                 /*
2228                  * Ok, does IRQ0 through the IOAPIC work?
2229                  */
2230                 unmask_IO_APIC_irq(0);
2231                 if (timer_irq_works()) {
2232                         if (nmi_watchdog == NMI_IO_APIC) {
2233                                 disable_8259A_irq(0);
2234                                 setup_nmi();
2235                                 enable_8259A_irq(0);
2236                         }
2237                         if (disable_timer_pin_1 > 0)
2238                                 clear_IO_APIC_pin(0, pin1);
2239                         return;
2240                 }
2241                 clear_IO_APIC_pin(apic1, pin1);
2242                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2243                                 "IO-APIC\n");
2244         }
2245
2246         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2247         if (pin2 != -1) {
2248                 printk("\n..... (found pin %d) ...", pin2);
2249                 /*
2250                  * legacy devices should be connected to IO APIC #0
2251                  */
2252                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2253                 if (timer_irq_works()) {
2254                         printk("works.\n");
2255                         if (pin1 != -1)
2256                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2257                         else
2258                                 add_pin_to_irq(0, apic2, pin2);
2259                         if (nmi_watchdog == NMI_IO_APIC) {
2260                                 setup_nmi();
2261                         }
2262                         return;
2263                 }
2264                 /*
2265                  * Cleanup, just in case ...
2266                  */
2267                 clear_IO_APIC_pin(apic2, pin2);
2268         }
2269         printk(" failed.\n");
2270
2271         if (nmi_watchdog == NMI_IO_APIC) {
2272                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2273                 nmi_watchdog = 0;
2274         }
2275
2276         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2277
2278         disable_8259A_irq(0);
2279         set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2280                                       "fasteoi");
2281         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2282         enable_8259A_irq(0);
2283
2284         if (timer_irq_works()) {
2285                 printk(" works.\n");
2286                 return;
2287         }
2288         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2289         printk(" failed.\n");
2290
2291         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2292
2293         timer_ack = 0;
2294         init_8259A(0);
2295         make_8259A_irq(0);
2296         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2297
2298         unlock_ExtINT_logic();
2299
2300         if (timer_irq_works()) {
2301                 printk(" works.\n");
2302                 return;
2303         }
2304         printk(" failed :(.\n");
2305         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2306                 "report.  Then try booting with the 'noapic' option");
2307 }
2308
2309 /*
2310  *
2311  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2312  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2313  *   Linux doesn't really care, as it's not actually used
2314  *   for any interrupt handling anyway.
2315  */
2316 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2317
2318 void __init setup_IO_APIC(void)
2319 {
2320         enable_IO_APIC();
2321
2322         if (acpi_ioapic)
2323                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2324         else
2325                 io_apic_irqs = ~PIC_IRQS;
2326
2327         printk("ENABLING IO-APIC IRQs\n");
2328
2329         /*
2330          * Set up IO-APIC IRQ routing.
2331          */
2332         if (!acpi_ioapic)
2333                 setup_ioapic_ids_from_mpc();
2334         sync_Arb_IDs();
2335         setup_IO_APIC_irqs();
2336         init_IO_APIC_traps();
2337         check_timer();
2338         if (!acpi_ioapic)
2339                 print_IO_APIC();
2340 }
2341
2342 static int __init setup_disable_8254_timer(char *s)
2343 {
2344         timer_over_8254 = -1;
2345         return 1;
2346 }
2347 static int __init setup_enable_8254_timer(char *s)
2348 {
2349         timer_over_8254 = 2;
2350         return 1;
2351 }
2352
2353 __setup("disable_8254_timer", setup_disable_8254_timer);
2354 __setup("enable_8254_timer", setup_enable_8254_timer);
2355
2356 /*
2357  *      Called after all the initialization is done. If we didnt find any
2358  *      APIC bugs then we can allow the modify fast path
2359  */
2360
2361 static int __init io_apic_bug_finalize(void)
2362 {
2363         if(sis_apic_bug == -1)
2364                 sis_apic_bug = 0;
2365         return 0;
2366 }
2367
2368 late_initcall(io_apic_bug_finalize);
2369
2370 struct sysfs_ioapic_data {
2371         struct sys_device dev;
2372         struct IO_APIC_route_entry entry[0];
2373 };
2374 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2375
2376 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2377 {
2378         struct IO_APIC_route_entry *entry;
2379         struct sysfs_ioapic_data *data;
2380         int i;
2381
2382         data = container_of(dev, struct sysfs_ioapic_data, dev);
2383         entry = data->entry;
2384         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2385                 entry[i] = ioapic_read_entry(dev->id, i);
2386
2387         return 0;
2388 }
2389
2390 static int ioapic_resume(struct sys_device *dev)
2391 {
2392         struct IO_APIC_route_entry *entry;
2393         struct sysfs_ioapic_data *data;
2394         unsigned long flags;
2395         union IO_APIC_reg_00 reg_00;
2396         int i;
2397
2398         data = container_of(dev, struct sysfs_ioapic_data, dev);
2399         entry = data->entry;
2400
2401         spin_lock_irqsave(&ioapic_lock, flags);
2402         reg_00.raw = io_apic_read(dev->id, 0);
2403         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2404                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2405                 io_apic_write(dev->id, 0, reg_00.raw);
2406         }
2407         spin_unlock_irqrestore(&ioapic_lock, flags);
2408         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2409                 ioapic_write_entry(dev->id, i, entry[i]);
2410
2411         return 0;
2412 }
2413
2414 static struct sysdev_class ioapic_sysdev_class = {
2415         set_kset_name("ioapic"),
2416         .suspend = ioapic_suspend,
2417         .resume = ioapic_resume,
2418 };
2419
2420 static int __init ioapic_init_sysfs(void)
2421 {
2422         struct sys_device * dev;
2423         int i, size, error = 0;
2424
2425         error = sysdev_class_register(&ioapic_sysdev_class);
2426         if (error)
2427                 return error;
2428
2429         for (i = 0; i < nr_ioapics; i++ ) {
2430                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2431                         * sizeof(struct IO_APIC_route_entry);
2432                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2433                 if (!mp_ioapic_data[i]) {
2434                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2435                         continue;
2436                 }
2437                 memset(mp_ioapic_data[i], 0, size);
2438                 dev = &mp_ioapic_data[i]->dev;
2439                 dev->id = i;
2440                 dev->cls = &ioapic_sysdev_class;
2441                 error = sysdev_register(dev);
2442                 if (error) {
2443                         kfree(mp_ioapic_data[i]);
2444                         mp_ioapic_data[i] = NULL;
2445                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2446                         continue;
2447                 }
2448         }
2449
2450         return 0;
2451 }
2452
2453 device_initcall(ioapic_init_sysfs);
2454
2455 /*
2456  * Dynamic irq allocate and deallocation
2457  */
2458 int create_irq(void)
2459 {
2460         /* Allocate an unused irq */
2461         int irq, new, vector = 0;
2462         unsigned long flags;
2463
2464         irq = -ENOSPC;
2465         spin_lock_irqsave(&vector_lock, flags);
2466         for (new = (NR_IRQS - 1); new >= 0; new--) {
2467                 if (platform_legacy_irq(new))
2468                         continue;
2469                 if (irq_vector[new] != 0)
2470                         continue;
2471                 vector = __assign_irq_vector(new);
2472                 if (likely(vector > 0))
2473                         irq = new;
2474                 break;
2475         }
2476         spin_unlock_irqrestore(&vector_lock, flags);
2477
2478         if (irq >= 0) {
2479                 set_intr_gate(vector, interrupt[irq]);
2480                 dynamic_irq_init(irq);
2481         }
2482         return irq;
2483 }
2484
2485 void destroy_irq(unsigned int irq)
2486 {
2487         unsigned long flags;
2488
2489         dynamic_irq_cleanup(irq);
2490
2491         spin_lock_irqsave(&vector_lock, flags);
2492         irq_vector[irq] = 0;
2493         spin_unlock_irqrestore(&vector_lock, flags);
2494 }
2495
2496 /*
2497  * MSI mesage composition
2498  */
2499 #ifdef CONFIG_PCI_MSI
2500 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2501 {
2502         int vector;
2503         unsigned dest;
2504
2505         vector = assign_irq_vector(irq);
2506         if (vector >= 0) {
2507                 dest = cpu_mask_to_apicid(TARGET_CPUS);
2508
2509                 msg->address_hi = MSI_ADDR_BASE_HI;
2510                 msg->address_lo =
2511                         MSI_ADDR_BASE_LO |
2512                         ((INT_DEST_MODE == 0) ?
2513                                 MSI_ADDR_DEST_MODE_PHYSICAL:
2514                                 MSI_ADDR_DEST_MODE_LOGICAL) |
2515                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2516                                 MSI_ADDR_REDIRECTION_CPU:
2517                                 MSI_ADDR_REDIRECTION_LOWPRI) |
2518                         MSI_ADDR_DEST_ID(dest);
2519
2520                 msg->data =
2521                         MSI_DATA_TRIGGER_EDGE |
2522                         MSI_DATA_LEVEL_ASSERT |
2523                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2524                                 MSI_DATA_DELIVERY_FIXED:
2525                                 MSI_DATA_DELIVERY_LOWPRI) |
2526                         MSI_DATA_VECTOR(vector);
2527         }
2528         return vector;
2529 }
2530
2531 #ifdef CONFIG_SMP
2532 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2533 {
2534         struct msi_msg msg;
2535         unsigned int dest;
2536         cpumask_t tmp;
2537         int vector;
2538
2539         cpus_and(tmp, mask, cpu_online_map);
2540         if (cpus_empty(tmp))
2541                 tmp = TARGET_CPUS;
2542
2543         vector = assign_irq_vector(irq);
2544         if (vector < 0)
2545                 return;
2546
2547         dest = cpu_mask_to_apicid(mask);
2548
2549         read_msi_msg(irq, &msg);
2550
2551         msg.data &= ~MSI_DATA_VECTOR_MASK;
2552         msg.data |= MSI_DATA_VECTOR(vector);
2553         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2554         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2555
2556         write_msi_msg(irq, &msg);
2557         irq_desc[irq].affinity = mask;
2558 }
2559 #endif /* CONFIG_SMP */
2560
2561 /*
2562  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2563  * which implement the MSI or MSI-X Capability Structure.
2564  */
2565 static struct irq_chip msi_chip = {
2566         .name           = "PCI-MSI",
2567         .unmask         = unmask_msi_irq,
2568         .mask           = mask_msi_irq,
2569         .ack            = ack_ioapic_irq,
2570 #ifdef CONFIG_SMP
2571         .set_affinity   = set_msi_irq_affinity,
2572 #endif
2573         .retrigger      = ioapic_retrigger_irq,
2574 };
2575
2576 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2577 {
2578         struct msi_msg msg;
2579         int irq, ret;
2580         irq = create_irq();
2581         if (irq < 0)
2582                 return irq;
2583
2584         set_irq_msi(irq, desc);
2585         ret = msi_compose_msg(dev, irq, &msg);
2586         if (ret < 0) {
2587                 destroy_irq(irq);
2588                 return ret;
2589         }
2590
2591         write_msi_msg(irq, &msg);
2592
2593         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2594                                       "edge");
2595
2596         return irq;
2597 }
2598
2599 void arch_teardown_msi_irq(unsigned int irq)
2600 {
2601         destroy_irq(irq);
2602 }
2603
2604 #endif /* CONFIG_PCI_MSI */
2605
2606 /*
2607  * Hypertransport interrupt support
2608  */
2609 #ifdef CONFIG_HT_IRQ
2610
2611 #ifdef CONFIG_SMP
2612
2613 static void target_ht_irq(unsigned int irq, unsigned int dest)
2614 {
2615         struct ht_irq_msg msg;
2616         fetch_ht_irq_msg(irq, &msg);
2617
2618         msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2619         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2620
2621         msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2622         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2623
2624         write_ht_irq_msg(irq, &msg);
2625 }
2626
2627 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2628 {
2629         unsigned int dest;
2630         cpumask_t tmp;
2631
2632         cpus_and(tmp, mask, cpu_online_map);
2633         if (cpus_empty(tmp))
2634                 tmp = TARGET_CPUS;
2635
2636         cpus_and(mask, tmp, CPU_MASK_ALL);
2637
2638         dest = cpu_mask_to_apicid(mask);
2639
2640         target_ht_irq(irq, dest);
2641         irq_desc[irq].affinity = mask;
2642 }
2643 #endif
2644
2645 static struct irq_chip ht_irq_chip = {
2646         .name           = "PCI-HT",
2647         .mask           = mask_ht_irq,
2648         .unmask         = unmask_ht_irq,
2649         .ack            = ack_ioapic_irq,
2650 #ifdef CONFIG_SMP
2651         .set_affinity   = set_ht_irq_affinity,
2652 #endif
2653         .retrigger      = ioapic_retrigger_irq,
2654 };
2655
2656 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2657 {
2658         int vector;
2659
2660         vector = assign_irq_vector(irq);
2661         if (vector >= 0) {
2662                 struct ht_irq_msg msg;
2663                 unsigned dest;
2664                 cpumask_t tmp;
2665
2666                 cpus_clear(tmp);
2667                 cpu_set(vector >> 8, tmp);
2668                 dest = cpu_mask_to_apicid(tmp);
2669
2670                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2671
2672                 msg.address_lo =
2673                         HT_IRQ_LOW_BASE |
2674                         HT_IRQ_LOW_DEST_ID(dest) |
2675                         HT_IRQ_LOW_VECTOR(vector) |
2676                         ((INT_DEST_MODE == 0) ?
2677                                 HT_IRQ_LOW_DM_PHYSICAL :
2678                                 HT_IRQ_LOW_DM_LOGICAL) |
2679                         HT_IRQ_LOW_RQEOI_EDGE |
2680                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2681                                 HT_IRQ_LOW_MT_FIXED :
2682                                 HT_IRQ_LOW_MT_ARBITRATED) |
2683                         HT_IRQ_LOW_IRQ_MASKED;
2684
2685                 write_ht_irq_msg(irq, &msg);
2686
2687                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2688                                               handle_edge_irq, "edge");
2689         }
2690         return vector;
2691 }
2692 #endif /* CONFIG_HT_IRQ */
2693
2694 /* --------------------------------------------------------------------------
2695                           ACPI-based IOAPIC Configuration
2696    -------------------------------------------------------------------------- */
2697
2698 #ifdef CONFIG_ACPI
2699
2700 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2701 {
2702         union IO_APIC_reg_00 reg_00;
2703         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2704         physid_mask_t tmp;
2705         unsigned long flags;
2706         int i = 0;
2707
2708         /*
2709          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2710          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2711          * supports up to 16 on one shared APIC bus.
2712          *
2713          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2714          *      advantage of new APIC bus architecture.
2715          */
2716
2717         if (physids_empty(apic_id_map))
2718                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2719
2720         spin_lock_irqsave(&ioapic_lock, flags);
2721         reg_00.raw = io_apic_read(ioapic, 0);
2722         spin_unlock_irqrestore(&ioapic_lock, flags);
2723
2724         if (apic_id >= get_physical_broadcast()) {
2725                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2726                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2727                 apic_id = reg_00.bits.ID;
2728         }
2729
2730         /*
2731          * Every APIC in a system must have a unique ID or we get lots of nice
2732          * 'stuck on smp_invalidate_needed IPI wait' messages.
2733          */
2734         if (check_apicid_used(apic_id_map, apic_id)) {
2735
2736                 for (i = 0; i < get_physical_broadcast(); i++) {
2737                         if (!check_apicid_used(apic_id_map, i))
2738                                 break;
2739                 }
2740
2741                 if (i == get_physical_broadcast())
2742                         panic("Max apic_id exceeded!\n");
2743
2744                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2745                         "trying %d\n", ioapic, apic_id, i);
2746
2747                 apic_id = i;
2748         }
2749
2750         tmp = apicid_to_cpu_present(apic_id);
2751         physids_or(apic_id_map, apic_id_map, tmp);
2752
2753         if (reg_00.bits.ID != apic_id) {
2754                 reg_00.bits.ID = apic_id;
2755
2756                 spin_lock_irqsave(&ioapic_lock, flags);
2757                 io_apic_write(ioapic, 0, reg_00.raw);
2758                 reg_00.raw = io_apic_read(ioapic, 0);
2759                 spin_unlock_irqrestore(&ioapic_lock, flags);
2760
2761                 /* Sanity check */
2762                 if (reg_00.bits.ID != apic_id) {
2763                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2764                         return -1;
2765                 }
2766         }
2767
2768         apic_printk(APIC_VERBOSE, KERN_INFO
2769                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2770
2771         return apic_id;
2772 }
2773
2774
2775 int __init io_apic_get_version (int ioapic)
2776 {
2777         union IO_APIC_reg_01    reg_01;
2778         unsigned long flags;
2779
2780         spin_lock_irqsave(&ioapic_lock, flags);
2781         reg_01.raw = io_apic_read(ioapic, 1);
2782         spin_unlock_irqrestore(&ioapic_lock, flags);
2783
2784         return reg_01.bits.version;
2785 }
2786
2787
2788 int __init io_apic_get_redir_entries (int ioapic)
2789 {
2790         union IO_APIC_reg_01    reg_01;
2791         unsigned long flags;
2792
2793         spin_lock_irqsave(&ioapic_lock, flags);
2794         reg_01.raw = io_apic_read(ioapic, 1);
2795         spin_unlock_irqrestore(&ioapic_lock, flags);
2796
2797         return reg_01.bits.entries;
2798 }
2799
2800
2801 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2802 {
2803         struct IO_APIC_route_entry entry;
2804         unsigned long flags;
2805
2806         if (!IO_APIC_IRQ(irq)) {
2807                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2808                         ioapic);
2809                 return -EINVAL;
2810         }
2811
2812         /*
2813          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2814          * Note that we mask (disable) IRQs now -- these get enabled when the
2815          * corresponding device driver registers for this IRQ.
2816          */
2817
2818         memset(&entry,0,sizeof(entry));
2819
2820         entry.delivery_mode = INT_DELIVERY_MODE;
2821         entry.dest_mode = INT_DEST_MODE;
2822         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2823         entry.trigger = edge_level;
2824         entry.polarity = active_high_low;
2825         entry.mask  = 1;
2826
2827         /*
2828          * IRQs < 16 are already in the irq_2_pin[] map
2829          */
2830         if (irq >= 16)
2831                 add_pin_to_irq(irq, ioapic, pin);
2832
2833         entry.vector = assign_irq_vector(irq);
2834
2835         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2836                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2837                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2838                 edge_level, active_high_low);
2839
2840         ioapic_register_intr(irq, entry.vector, edge_level);
2841
2842         if (!ioapic && (irq < 16))
2843                 disable_8259A_irq(irq);
2844
2845         spin_lock_irqsave(&ioapic_lock, flags);
2846         __ioapic_write_entry(ioapic, pin, entry);
2847         spin_unlock_irqrestore(&ioapic_lock, flags);
2848
2849         return 0;
2850 }
2851
2852 #endif /* CONFIG_ACPI */
2853
2854 static int __init parse_disable_timer_pin_1(char *arg)
2855 {
2856         disable_timer_pin_1 = 1;
2857         return 0;
2858 }
2859 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2860
2861 static int __init parse_enable_timer_pin_1(char *arg)
2862 {
2863         disable_timer_pin_1 = -1;
2864         return 0;
2865 }
2866 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2867
2868 static int __init parse_noapic(char *arg)
2869 {
2870         /* disable IO-APIC */
2871         disable_ioapic_setup();
2872         return 0;
2873 }
2874 early_param("noapic", parse_noapic);